| /* |
| * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #ifndef __ARCH_HELPERS_H__ |
| #define __ARCH_HELPERS_H__ |
| |
| #include <arch.h> /* for additional register definitions */ |
| #include <cdefs.h> /* For __dead2 */ |
| #include <misc_utils.h> |
| #include <stdint.h> |
| #include <sys/types.h> |
| |
| /********************************************************************** |
| * Macros which create inline functions to read or write CPU system |
| * registers |
| *********************************************************************/ |
| |
| #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ |
| static inline u_register_t read_ ## _name(void) \ |
| { \ |
| u_register_t v; \ |
| __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ |
| return v; \ |
| } |
| |
| #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ |
| static inline void write_ ## _name(u_register_t v) \ |
| { \ |
| __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ |
| } |
| |
| #define SYSREG_WRITE_CONST(reg_name, v) \ |
| __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) |
| |
| /* Define read function for system register */ |
| #define DEFINE_SYSREG_READ_FUNC(_name) \ |
| _DEFINE_SYSREG_READ_FUNC(_name, _name) |
| |
| /* Define read & write function for system register */ |
| #define DEFINE_SYSREG_RW_FUNCS(_name) \ |
| _DEFINE_SYSREG_READ_FUNC(_name, _name) \ |
| _DEFINE_SYSREG_WRITE_FUNC(_name, _name) |
| |
| /* Define read & write function for renamed system register */ |
| #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ |
| _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ |
| _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) |
| |
| /* Define read function for renamed system register */ |
| #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ |
| _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) |
| |
| /* Define write function for renamed system register */ |
| #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ |
| _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) |
| |
| /********************************************************************** |
| * Macros to create inline functions for system instructions |
| *********************************************************************/ |
| |
| /* Define function for simple system instruction */ |
| #define DEFINE_SYSOP_FUNC(_op) \ |
| static inline void _op(void) \ |
| { \ |
| __asm__ (#_op); \ |
| } |
| |
| /* Define function for system instruction with type specifier */ |
| #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ |
| static inline void _op ## _type(void) \ |
| { \ |
| __asm__ (#_op " " #_type); \ |
| } |
| |
| /* Define function for system instruction with register parameter */ |
| #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ |
| static inline void _op ## _type(uint64_t v) \ |
| { \ |
| __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ |
| } |
| |
| /******************************************************************************* |
| * TLB maintenance accessor prototypes |
| ******************************************************************************/ |
| |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) |
| DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) |
| |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) |
| |
| /******************************************************************************* |
| * Cache maintenance accessor prototypes |
| ******************************************************************************/ |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) |
| DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) |
| |
| void flush_dcache_range(uintptr_t addr, size_t size); |
| void clean_dcache_range(uintptr_t addr, size_t size); |
| void inv_dcache_range(uintptr_t addr, size_t size); |
| |
| void dcsw_op_louis(u_register_t op_type); |
| void dcsw_op_all(u_register_t op_type); |
| |
| void disable_mmu(void); |
| void disable_mmu_icache(void); |
| |
| /******************************************************************************* |
| * Misc. accessor prototypes |
| ******************************************************************************/ |
| |
| DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) |
| DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) |
| DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) |
| DEFINE_SYSREG_READ_FUNC(CurrentEl) |
| DEFINE_SYSREG_READ_FUNC(ctr_el0) |
| DEFINE_SYSREG_RW_FUNCS(daif) |
| DEFINE_SYSREG_RW_FUNCS(spsr_el1) |
| DEFINE_SYSREG_RW_FUNCS(spsr_el2) |
| DEFINE_SYSREG_RW_FUNCS(elr_el1) |
| DEFINE_SYSREG_RW_FUNCS(elr_el2) |
| |
| DEFINE_SYSOP_FUNC(wfi) |
| DEFINE_SYSOP_FUNC(wfe) |
| DEFINE_SYSOP_FUNC(sev) |
| DEFINE_SYSOP_TYPE_FUNC(dsb, sy) |
| DEFINE_SYSOP_TYPE_FUNC(dsb, ish) |
| DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) |
| DEFINE_SYSOP_FUNC(isb) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, osh) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, ish) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, ld) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, st) |
| DEFINE_SYSOP_TYPE_FUNC(dmb, sy) |
| |
| #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) |
| #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) |
| |
| static inline void enable_irq(void) |
| { |
| /* |
| * The compiler memory barrier will prevent the compiler from |
| * scheduling non-volatile memory access after the write to the |
| * register. |
| * |
| * This could happen if some initialization code issues non-volatile |
| * accesses to an area used by an interrupt handler, in the assumption |
| * that it is safe as the interrupts are disabled at the time it does |
| * that (according to program order). However, non-volatile accesses |
| * are not necessarily in program order relatively with volatile inline |
| * assembly statements (and volatile accesses). |
| */ |
| COMPILER_BARRIER(); |
| write_daifclr(DAIF_IRQ_BIT); |
| isb(); |
| } |
| |
| static inline void enable_fiq(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifclr(DAIF_FIQ_BIT); |
| isb(); |
| } |
| |
| static inline void enable_serror(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifclr(DAIF_ABT_BIT); |
| isb(); |
| } |
| |
| static inline void enable_debug_exceptions(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifclr(DAIF_DBG_BIT); |
| isb(); |
| } |
| |
| static inline void disable_irq(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifset(DAIF_IRQ_BIT); |
| isb(); |
| } |
| |
| static inline void disable_fiq(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifset(DAIF_FIQ_BIT); |
| isb(); |
| } |
| |
| static inline void disable_serror(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifset(DAIF_ABT_BIT); |
| isb(); |
| } |
| |
| static inline void disable_debug_exceptions(void) |
| { |
| COMPILER_BARRIER(); |
| write_daifset(DAIF_DBG_BIT); |
| isb(); |
| } |
| |
| uint32_t get_afflvl_shift(uint32_t); |
| uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); |
| |
| void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, |
| uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); |
| void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, |
| uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); |
| |
| /******************************************************************************* |
| * System register accessor prototypes |
| ******************************************************************************/ |
| DEFINE_SYSREG_READ_FUNC(midr_el1) |
| DEFINE_SYSREG_READ_FUNC(mpidr_el1) |
| DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) |
| |
| DEFINE_SYSREG_RW_FUNCS(hcr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(vbar_el1) |
| DEFINE_SYSREG_RW_FUNCS(vbar_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(sctlr_el1) |
| DEFINE_SYSREG_RW_FUNCS(sctlr_el2) |
| DEFINE_SYSREG_RW_FUNCS(sctlr_el3) |
| |
| DEFINE_SYSREG_RW_FUNCS(actlr_el1) |
| DEFINE_SYSREG_RW_FUNCS(actlr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(esr_el1) |
| DEFINE_SYSREG_RW_FUNCS(esr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(afsr0_el1) |
| DEFINE_SYSREG_RW_FUNCS(afsr0_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(afsr1_el1) |
| DEFINE_SYSREG_RW_FUNCS(afsr1_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(far_el1) |
| DEFINE_SYSREG_RW_FUNCS(far_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(mair_el1) |
| DEFINE_SYSREG_RW_FUNCS(mair_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(amair_el1) |
| DEFINE_SYSREG_RW_FUNCS(amair_el2) |
| |
| DEFINE_SYSREG_READ_FUNC(rvbar_el1) |
| DEFINE_SYSREG_READ_FUNC(rvbar_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(rmr_el1) |
| DEFINE_SYSREG_RW_FUNCS(rmr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(tcr_el1) |
| DEFINE_SYSREG_RW_FUNCS(tcr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) |
| DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) |
| |
| DEFINE_SYSREG_RW_FUNCS(cptr_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(cpacr_el1) |
| DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) |
| DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) |
| DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) |
| DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) |
| DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) |
| DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) |
| DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) |
| DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) |
| DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) |
| DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) |
| DEFINE_SYSREG_READ_FUNC(cntpct_el0) |
| DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) |
| |
| DEFINE_SYSREG_RW_FUNCS(vpidr_el2) |
| DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) |
| |
| /* GICv3 System Registers */ |
| |
| DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) |
| DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) |
| DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) |
| DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) |
| |
| DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) |
| DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) |
| |
| /* Armv8.3 Pointer Authentication Registers */ |
| DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) |
| |
| #define IS_IN_EL(x) \ |
| (GET_EL(read_CurrentEl()) == MODE_EL##x) |
| |
| #define IS_IN_EL1() IS_IN_EL(1) |
| #define IS_IN_EL2() IS_IN_EL(2) |
| |
| #endif /* __ARCH_HELPERS_H__ */ |