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jaypit02ea3cd062018-10-05 12:22:38 +05301/** @file
2 * Copyright (c) 2018, Arm Limited or its affiliates. All rights reserved.
3 * SPDX-License-Identifier : Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16**/
17
18#ifndef _VAL_COMMON_H_
19#define _VAL_COMMON_H_
20
21#include <string.h>
22#include <stdint.h>
23#include <stdlib.h>
24
25/* typedef's */
26typedef uint8_t bool_t;
27typedef uint32_t addr_t;
28typedef uint32_t test_id_t;
29typedef uint32_t block_id_t;
30typedef char char8_t;
31typedef uint32_t cfg_id_t;
32
33
34#ifndef VAL_NSPE_BUILD
35#define STATIC_DECLARE static
36#else
37#define STATIC_DECLARE
38#endif
39
40#ifndef __WEAK
41#define __WEAK __attribute__((weak))
42#endif
43
44#ifndef __UNUSED
45#define __UNUSED __attribute__((unused))
46#endif
47
48#ifndef TRUE
49#define TRUE 0
50#endif
51#ifndef FALSE
52#define FALSE 1
53#endif
54
55/* test status defines */
56#define TEST_START 0x01
57#define TEST_END 0x02
58#define TEST_PASS 0x04
59#define TEST_FAIL 0x08
60#define TEST_SKIP 0x10
61#define TEST_PENDING 0x20
62
63#define TEST_NUM_BIT 32
64#define TEST_STATE_BIT 8
65#define TEST_STATUS_BIT 0
66
67#define TEST_NUM_MASK 0xFFFFFFFF
68#define TEST_STATE_MASK 0xFF
69#define TEST_STATUS_MASK 0xFF
70
71#define RESULT_START(status) (((TEST_START) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
72#define RESULT_END(status) (((TEST_END) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
73#define RESULT_PASS(status) (((TEST_PASS) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
74#define RESULT_FAIL(status) (((TEST_FAIL) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
75#define RESULT_SKIP(status) (((TEST_SKIP) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
76#define RESULT_PENDING(status) (((TEST_PENDING) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
77
78#define IS_TEST_FAIL(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_FAIL)
79#define IS_TEST_PASS(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PASS)
80#define IS_TEST_SKIP(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_SKIP)
81#define IS_TEST_PENDING(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PENDING)
82#define IS_TEST_START(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_START)
83#define IS_TEST_END(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_END)
84#define VAL_ERROR(status) (status?1:0)
85
86
87
88/* Test Defines */
89#define TEST_PUBLISH(test_id, entry) \
90 const val_test_info_t __attribute__((section(".acs_test_info"))) acs_test_info = {test_id, entry}
91
92#define VAL_MAX_TEST_PER_COMP 200
93#define VAL_FF_BASE 0
94#define VAL_CRYPTO_BASE 1
95#define VAL_GET_COMP_NUM(test_id) \
96 ((test_id - (test_id % VAL_MAX_TEST_PER_COMP)) / VAL_MAX_TEST_PER_COMP)
97#define VAL_GET_TEST_NUM(test_id) (test_id % VAL_MAX_TEST_PER_COMP)
98#define VAL_CREATE_TEST_ID(comp,num) ((comp*VAL_MAX_TEST_PER_COMP) + num)
99
100#define TEST_FIELD(num1,num2) (num2 << 8 | num1)
101#define GET_TEST_ISOLATION_LEVEL(num) (num & 0x3)
102#define GET_WD_TIMOUT_TYPE(num) ((num >> 8) & 0x3)
103
104#define TEST_CHECKPOINT_NUM(n) n
105#define TEST(n) n
106#define BLOCK(n) n
107
108#define BLOCK_NUM_POS 8
109#define ACTION_POS 16
110#define GET_TEST_NUM(n) (0xff & n)
111#define GET_BLOCK_NUM(n) ((n >> BLOCK_NUM_POS) & 0xff)
112
113#define GET_ACTION_NUM(n) ((n >> ACTION_POS) & 0xff)
114#define TEST_EXECUTE_FUNC 1
115#define TEST_RETURN_RESULT 2
116#define INVALID_HANDLE 0x1234DEAD
117
118#define VAL_NVMEM_BLOCK_SIZE 4
119#define VAL_NVMEM_OFFSET(nvmem_idx) (nvmem_idx * VAL_NVMEM_BLOCK_SIZE)
120
121#define UART_INIT_SIGN 0xff
122
123/* enums */
124typedef enum {
125 NONSECURE = 0x0,
126 SECURE = 0x1,
127} security_t;
128
129typedef enum {
130 TEST_ISOLATION_L1 = 0x1,
131 TEST_ISOLATION_L2 = 0x2,
132 TEST_ISOLATION_L3 = 0x3,
133} test_isolation_level_t;
134
135typedef enum {
136 BOOT_UNKNOWN = 0x1,
137 BOOT_NOT_EXPECTED = 0x2,
138 BOOT_EXPECTED_NS = 0x3,
139 BOOT_EXPECTED_S = 0x4,
140 BOOT_EXPECTED_BUT_FAILED = 0x5,
141 BOOT_EXPECTED_CRYPTO = 0x6,
142} boot_state_t;
143
144typedef enum {
145 NV_BOOT = 0x0,
146 NV_TEST_ID_PREVIOUS = 0x1,
147 NV_TEST_ID_CURRENT = 0x2,
148 NV_TEST_CNT = 0x3,
149} nvmem_index_t;
150
151typedef enum {
152 WD_INIT_SEQ = 0x1,
153 WD_ENABLE_SEQ = 0x2,
154 WD_DISABLE_SEQ = 0x3,
155 WD_STATUS_SEQ = 0x4,
156} wd_fn_type_t;
157
158typedef enum {
159 WD_LOW_TIMEOUT = 0x1,
160 WD_MEDIUM_TIMEOUT = 0x2,
161 WD_HIGH_TIMEOUT = 0x3,
162} wd_timeout_type_t;
163
164typedef enum {
165 NVMEM_READ = 0x1,
166 NVMEM_WRITE = 0x2,
167} nvmem_fn_type_t;
168
169/* enums to report test sub-state */
170typedef enum {
171 VAL_STATUS_SUCCESS = 0x0,
172 VAL_STATUS_INVALID = 0x10,
173 VAL_STATUS_ERROR = 0x11,
174 VAL_STATUS_NOT_FOUND = 0x12,
175 VAL_STATUS_LOAD_ERROR = 0x13,
176 VAL_STATUS_INSUFFICIENT_SIZE = 0x14,
177 VAL_STATUS_CONNECTION_FAILED = 0x15,
178 VAL_STATUS_CALL_FAILED = 0x16,
179 VAL_STATUS_READ_FAILED = 0x17,
180 VAL_STATUS_WRITE_FAILED = 0x18,
181 VAL_STATUS_ISOLATION_LEVEL_NOT_SUPP = 0x19,
182 VAL_STATUS_INIT_FAILED = 0x1A,
183 VAL_STATUS_SPM_FAILED = 0x1B,
184 VAL_STATUS_SPM_UNEXPECTED_BEH = 0x1C,
185 VAL_STATUS_FRAMEWORK_VERSION_FAILED = 0x1D,
186 VAL_STATUS_VERSION_API_FAILED = 0x1E,
187 VAL_STATUS_INVALID_HANDLE = 0x1F,
188 VAL_STATUS_INVALID_MSG_TYPE = 0x20,
189 VAL_STATUS_WRONG_IDENTITY = 0x21,
190 VAL_STATUS_MSG_INSIZE_FAILED = 0x22,
191 VAL_STATUS_MSG_OUTSIZE_FAILED = 0x23,
192 VAL_STATUS_SKIP_FAILED = 0x24,
193 VAL_STATUS_CRYPTO_FAILURE = 0x25,
194 VAL_STATUS_INVALID_SIZE = 0x26,
195 VAL_STATUS_DATA_MISMATCH = 0x27,
196 VAL_STATUS_BOOT_EXPECTED_BUT_FAILED = 0x28,
197} val_status_t;
198
199/* verbosity enums */
200typedef enum {
201 PRINT_INFO = 1,
202 PRINT_DEBUG = 2,
203 PRINT_TEST = 3,
204 PRINT_WARN = 4,
205 PRINT_ERROR = 5,
206 PRINT_ALWAYS = 9
207} print_verbosity_t;
208
209/* typedef's */
210typedef struct {
211 boot_state_t state;
212} boot_t;
213
214typedef struct {
215 uint32_t pass_cnt:8;
216 uint32_t skip_cnt:8;
217 uint32_t fail_cnt:8;
218 uint32_t sim_error_cnt:8;
219} test_count_t;
220
221typedef struct {
222 wd_fn_type_t wd_fn_type;
223 wd_timeout_type_t wd_timeout_type;
224} wd_param_t;
225
226typedef struct {
227 nvmem_fn_type_t nvmem_fn_type;
228 uint32_t offset;
229 int size;
230} nvmem_param_t;
231
232typedef struct {
233 addr_t wd_base_addr;
234 uint32_t wd_time_us_low;
235 uint32_t wd_time_us_medium;
236 uint32_t wd_time_us_high;
237 uint32_t wd_timer_tick_us;
238 addr_t nvmem_base_addr;
239 addr_t uart_base_addr;
240} target_param_t;
241
242
243typedef struct {
244 uint16_t test_num;
245 uint8_t block_num;
246} test_info_t;
247
248
249/* struture to capture test state */
250typedef struct {
251 uint16_t reserved;
252 uint8_t state;
253 uint8_t status;
254} test_status_buffer_t;
255
256typedef int32_t (*client_test_t)(security_t caller);
257typedef int32_t (*server_test_t)(void);
258#endif /* VAL_COMMON_H */