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review.trustedfirmware.org / mirror / psa-arch-tests / 01ee3ffef2a0a7d72ba8e2760a99c43c60a0f956 / . / secure-debug / val / include / val.h
blob: 4082c5c3527235d062a52cc924662921b38811bb [file] [log] [blame]
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]1/** @file
2 * Copyright (c) 2021 Arm Limited or its affiliates. All rights reserved.
3 * SPDX-License-Identifier : Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16**/
17
18#ifndef _VAL_COMMON_H_
19#define _VAL_COMMON_H_
20
21#include <string.h>
22#include <stdint.h>
23#include <stdlib.h>
24#include <limits.h>
25#include <stdarg.h>
26
27typedef uint8_t bool_t;
28typedef uintptr_t addr_t;
29typedef uint32_t test_id_t;
30typedef uint32_t block_id_t;
31typedef char char8_t;
32typedef uint32_t cfg_id_t;
33
34/* Print verbosity = TEST */
35#ifndef VERBOSE
36#define VERBOSE 9
37#endif
38
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]39#ifndef __WEAK
40#define __WEAK __attribute__((weak))
41#endif
42
43#ifndef __UNUSED
44#define __UNUSED __attribute__((unused))
45#endif
46
47#ifndef TRUE
48#define TRUE 0
49#endif
50#ifndef FALSE
51#define FALSE 1
52#endif
53
54#define _CONCAT(A, B) A##B
55#define CONCAT(A, B) _CONCAT(A, B)
56
57/* test status defines */
58#define TEST_START 0x01
59#define TEST_END 0x02
60#define TEST_PASS 0x04
61#define TEST_FAIL 0x08
62#define TEST_SKIP 0x10
63#define TEST_PENDING 0x20
64
65#define TEST_NUM_BIT 32
66#define TEST_STATE_BIT 8
67#define TEST_STATUS_BIT 0
68
69#define TEST_NUM_MASK 0xFFFFFFFF
70#define TEST_STATE_MASK 0xFF
71#define TEST_STATUS_MASK 0xFF
72
73#define RESULT_START(status) (((TEST_START) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
74#define RESULT_END(status) (((TEST_END) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
75#define RESULT_PASS(status) (((TEST_PASS) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
76#define RESULT_FAIL(status) (((TEST_FAIL) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
77#define RESULT_SKIP(status) (((TEST_SKIP) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
78#define RESULT_PENDING(status) (((TEST_PENDING) << TEST_STATE_BIT) | ((status) << TEST_STATUS_BIT))
79
80#define IS_TEST_FAIL(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_FAIL)
81#define IS_TEST_PASS(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PASS)
82#define IS_TEST_SKIP(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_SKIP)
83#define IS_TEST_PENDING(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_PENDING)
84#define IS_TEST_START(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_START)
85#define IS_TEST_END(status) (((status >> TEST_STATE_BIT) & TEST_STATE_MASK) == TEST_END)
86#define VAL_ERROR(status) ((status & TEST_STATUS_MASK) ? 1 : 0)
87
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]88/* Test Defines */
89#define TEST_PUBLISH(test_id, entry) \
90 const val_test_info_t __attribute__((section(".acs_test_info"))) \
91 CONCAT(acs_test_info, entry) = {test_id, entry}
92
93#define VAL_MAX_TEST_PER_COMP 200
94#define VAL_SECURE_DEBUG_BASE 4
95
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]96#define VAL_GET_COMP_NUM(test_id) \
97 ((test_id - (test_id % VAL_MAX_TEST_PER_COMP)) / VAL_MAX_TEST_PER_COMP)
98#define VAL_GET_TEST_NUM(test_id) (test_id % VAL_MAX_TEST_PER_COMP)
99#define VAL_CREATE_TEST_ID(comp, num) ((comp*VAL_MAX_TEST_PER_COMP) + num)
100
101#define TEST_FIELD(num1, num2) (num2 << 8 | num1)
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]102
103#define TEST_CHECKPOINT_NUM(n) n
104#define TEST(n) n
105#define BLOCK(n) n
106
107#define BLOCK_NUM_POS 8
108#define ACTION_POS 16
109#define GET_TEST_NUM(n) (0xff & n)
110#define GET_BLOCK_NUM(n) ((n >> BLOCK_NUM_POS) & 0xff)
111
112#define GET_ACTION_NUM(n) ((n >> ACTION_POS) & 0xff)
113#define TEST_EXECUTE_FUNC 1
114#define TEST_RETURN_RESULT 2
115#define INVALID_HANDLE 0x1234DEAD
116
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]117#define UART_INIT_SIGN 0xff
118#define UART_PRINT_SIGN 0xfe
119
120#define TEST_PANIC() \
121 do { \
122 } while (1)
123
124#define TEST_ASSERT_EQUAL(arg1, arg2, checkpoint) \
125 do { \
126 if ((arg1) != arg2) \
127 { \
128 val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
129 val->print(PRINT_ERROR, "\tActual: %d\n", arg1); \
130 val->print(PRINT_ERROR, "\tExpected: %d\n", arg2); \
131 return 1; \
132 } \
133 } while (0)
134
135#define TEST_ASSERT_DUAL(arg1, status1, status2, checkpoint) \
136 do { \
137 if ((arg1) != status1 && (arg1) != status2) \
138 { \
139 val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
140 val->print(PRINT_ERROR, "\tActual: %d\n", arg1); \
141 val->print(PRINT_ERROR, "\tExpected: %d", status1); \
142 val->print(PRINT_ERROR, "or %d\n", status2); \
143 return 1; \
144 } \
145 } while (0)
146
147#define TEST_ASSERT_NOT_EQUAL(arg1, arg2, checkpoint) \
148 do { \
149 if ((arg1) == arg2) \
150 { \
151 val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
152 val->print(PRINT_ERROR, "\tValue: %d\n", arg1); \
153 return 1; \
154 } \
155 } while (0)
156
157#define TEST_ASSERT_MEMCMP(buf1, buf2, size, checkpoint) \
158 do { \
159 if (memcmp(buf1, buf2, size)) \
160 { \
161 val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d : ", checkpoint); \
162 val->print(PRINT_ERROR, "Unequal data in compared buffers\n", 0); \
163 return 1; \
164 } \
165 } while (0)
166
167#define TEST_ASSERT_RANGE(arg1, range1, range2, checkpoint) \
168 do { \
169 if ((arg1) < range1 || (arg1) > range2) \
170 { \
171 val->print(PRINT_ERROR, "\tFailed at Checkpoint: %d\n", checkpoint); \
172 val->print(PRINT_ERROR, "\tActual: %d\n", arg1); \
173 val->print(PRINT_ERROR, "\tExpected range: %d to ", range1); \
174 val->print(PRINT_ERROR, "%d", range2); \
175 return 1; \
176 } \
177 } while (0)
178
179/* enums */
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]180
181/* enums to report test sub-state */
182typedef enum {
183 VAL_STATUS_SUCCESS = 0x0,
184 VAL_STATUS_INVALID = 0x10,
185 VAL_STATUS_ERROR = 0x11,
186 VAL_STATUS_NOT_FOUND = 0x12,
187 VAL_STATUS_LOAD_ERROR = 0x13,
188 VAL_STATUS_INSUFFICIENT_SIZE = 0x14,
189 VAL_STATUS_CONNECTION_FAILED = 0x15,
190 VAL_STATUS_CALL_FAILED = 0x16,
191 VAL_STATUS_READ_FAILED = 0x17,
192 VAL_STATUS_WRITE_FAILED = 0x18,
193 VAL_STATUS_ISOLATION_LEVEL_NOT_SUPP = 0x19,
194 VAL_STATUS_INIT_FAILED = 0x1A,
195 VAL_STATUS_SPM_FAILED = 0x1B,
196 VAL_STATUS_SPM_UNEXPECTED_BEH = 0x1C,
197 VAL_STATUS_FRAMEWORK_VERSION_FAILED = 0x1D,
198 VAL_STATUS_VERSION_API_FAILED = 0x1E,
199 VAL_STATUS_INVALID_HANDLE = 0x1F,
200 VAL_STATUS_INVALID_MSG_TYPE = 0x20,
201 VAL_STATUS_WRONG_IDENTITY = 0x21,
202 VAL_STATUS_MSG_INSIZE_FAILED = 0x22,
203 VAL_STATUS_MSG_OUTSIZE_FAILED = 0x23,
204 VAL_STATUS_SKIP_FAILED = 0x24,
205 VAL_STATUS_CRYPTO_FAILURE = 0x25,
206 VAL_STATUS_INVALID_SIZE = 0x26,
207 VAL_STATUS_DATA_MISMATCH = 0x27,
208 VAL_STATUS_BOOT_EXPECTED_BUT_FAILED = 0x28,
209 VAL_STATUS_INIT_ALREADY_DONE = 0x29,
210 VAL_STATUS_HEAP_NOT_AVAILABLE = 0x2A,
211 VAL_STATUS_UNSUPPORTED = 0x2B,
212 VAL_STATUS_DRIVER_FN_FAILED = 0x2C,
213 VAL_STATUS_NO_TESTS = 0X2D,
214 VAL_STATUS_TEST_FAILED = 0x2E,
215 VAL_STATUS_ERROR_MAX = INT_MAX,
216} val_status_t;
217
218/* verbosity enums */
219typedef enum {
220 PRINT_INFO = 1,
221 PRINT_DEBUG = 2,
222 PRINT_TEST = 3,
223 PRINT_WARN = 4,
224 PRINT_ERROR = 5,
225 PRINT_ALWAYS = 9
226} print_verbosity_t;
227
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]228/* typedef's */
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]229
230typedef struct {
231 uint32_t pass_cnt:8;
232 uint32_t skip_cnt:8;
233 uint32_t fail_cnt:8;
234 uint32_t sim_error_cnt:8;
235} test_count_t;
236
237typedef struct {
238 uint16_t test_num;
239 uint8_t block_num;
240} test_info_t;
241
242
243/* struture to capture test state */
244typedef struct {
245 uint16_t reserved;
246 uint8_t state;
247 uint8_t status;
248} test_status_buffer_t;
249
jk-arm957cfea2021-06-18 15:52:12 +0530[diff] [blame]250#endif /* VAL_COMMON_H */