blob: ee2bb386fd8634bbd714ae2450204beeed1eb70a [file] [log] [blame]
Roman Okhrimenko89ecdac2020-02-28 17:05:55 +02001/***************************************************************************//**
2* \file system_psoc6.h
3* \version 2.70
4*
5* \brief Device system header file.
6*
7********************************************************************************
8* \copyright
9* Copyright 2016-2019 Cypress Semiconductor Corporation
10* SPDX-License-Identifier: Apache-2.0
11*
12* Licensed under the Apache License, Version 2.0 (the "License");
13* you may not use this file except in compliance with the License.
14* You may obtain a copy of the License at
15*
16* http://www.apache.org/licenses/LICENSE-2.0
17*
18* Unless required by applicable law or agreed to in writing, software
19* distributed under the License is distributed on an "AS IS" BASIS,
20* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21* See the License for the specific language governing permissions and
22* limitations under the License.
23*******************************************************************************/
24
25
26#ifndef _SYSTEM_PSOC6_H_
27#define _SYSTEM_PSOC6_H_
28
29/**
30* \addtogroup group_system_config
31* \{
32* Provides device startup, system configuration, and linker script files.
33* The system startup provides the followings features:
34* - See \ref group_system_config_device_initialization for the:
35* * \ref group_system_config_dual_core_device_initialization
36* * \ref group_system_config_single_core_device_initialization
37* - \ref group_system_config_device_memory_definition
38* - \ref group_system_config_heap_stack_config
39* - \ref group_system_config_merge_apps
40* - \ref group_system_config_default_handlers
41* - \ref group_system_config_device_vector_table
42* - \ref group_system_config_cm4_functions
43*
44* \section group_system_config_configuration Configuration Considerations
45*
46* \subsection group_system_config_device_memory_definition Device Memory Definition
47* The flash and RAM allocation for each CPU is defined by the linker scripts.
48* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores.
49* 2 KB of RAM (allocated at the end of RAM) are reserved for system use.
50* For Single-Core devices the system reserves additional 80 bytes of RAM.
51* Using the reserved memory area for other purposes will lead to unexpected behavior.
52*
53* \note The linker files provided with the PDL are generic and handle all common
54* use cases. Your project may not use every section defined in the linker files.
55* In that case you may see warnings during the build process. To eliminate build
56* warnings in your project, you can simply comment out or remove the relevant
57* code in the linker file.
58*
59* <b>ARM GCC</b>\n
60* The flash and RAM sections for the CPU are defined in the linker files:
61* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example,
62* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'.
63* \note If the start of the Cortex-M4 application image is changed, the value
64* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
65* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the
66* Cy_SysEnableCM4() function call.
67*
68* Change the flash and RAM sizes by editing the macros value in the
69* linker files for both CPUs:
70* - 'xx_cm0plus.ld', where 'xx' is the device group:
71* \code
72* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000
73* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000
74* \endcode
75* - 'xx_cm4_dual.ld', where 'xx' is the device group:
76* \code
77* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000
78* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800
79* \endcode
80*
81* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's
82* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this
83* by either:
84* - Passing the following commands to the compiler:\n
85* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
86* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n
87* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
88*
89* <b>ARM MDK</b>\n
90* The flash and RAM sections for the CPU are defined in the linker files:
91* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example,
92* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'.
93* \note If the start of the Cortex-M4 application image is changed, the value
94* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
95* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
96* Cy_SysEnableCM4() function call.
97*
98* \note The linker files provided with the PDL are generic and handle all common
99* use cases. Your project may not use every section defined in the linker files.
100* In that case you may see the warnings during the build process:
101* L6314W (no section matches pattern) and/or L6329W
102* (pattern only matches removed unused sections). In your project, you can
103* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
104* the linker. You can also comment out or remove the relevant code in the linker
105* file.
106*
107* Change the flash and RAM sizes by editing the macros value in the
108* linker files for both CPUs:
109* - 'xx_cm0plus.scat', where 'xx' is the device group:
110* \code
111* #define FLASH_START 0x10000000
112* #define FLASH_SIZE 0x00080000
113* #define RAM_START 0x08000000
114* #define RAM_SIZE 0x00024000
115* \endcode
116* - 'xx_cm4_dual.scat', where 'xx' is the device group:
117* \code
118* #define FLASH_START 0x10080000
119* #define FLASH_SIZE 0x00080000
120* #define RAM_START 0x08024000
121* #define RAM_SIZE 0x00023800
122* \endcode
123*
124* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START
125* value in the 'xx_cm4_dual.scat' file,
126* where 'xx' is the device group. Do this by either:
127* - Passing the following commands to the compiler:\n
128* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
129* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
130* 'xx' is device family:\n
131* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
132*
133* <b>IAR</b>\n
134* The flash and RAM sections for the CPU are defined in the linker files:
135* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example,
136* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'.
137* \note If the start of the Cortex-M4 application image is changed, the value
138* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The
139* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref
140* Cy_SysEnableCM4() function call.
141*
142* Change the flash and RAM sizes by editing the macros value in the
143* linker files for both CPUs:
144* - 'xx_cm0plus.icf', where 'xx' is the device group:
145* \code
146* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
147* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000;
148* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
149* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000;
150* \endcode
151* - 'xx_cm4_dual.icf', where 'xx' is the device group:
152* \code
153* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000;
154* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000;
155* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000;
156* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800;
157* \endcode
158*
159* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the
160* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx'
161* is the device group. Do this by either:
162* - Passing the following commands to the compiler:\n
163* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode
164* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where
165* 'xx' is device family:\n
166* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode
167*
168* \subsection group_system_config_device_initialization Device Initialization
169* After a power-on-reset (POR), the boot process is handled by the boot code
170* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot
171* code passes the control to the Cortex-M0+ startup code located in flash.
172*
173* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices
174* The Cortex-M0+ startup code performs the device initialization by a call to
175* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled
176* by default. Enable the core using the \ref Cy_SysEnableCM4() function.
177* See \ref group_system_config_cm4_functions for more details.
178* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores.
179* The function has a separate implementation on each core.
180* Both function implementations unlock and disable the WDT.
181* Therefore enable the WDT after both cores have been initialized.
182*
183* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices
184* The Cortex-M0+ core is not user-accessible on these devices. In this case the
185* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core.
186*
187* \subsection group_system_config_heap_stack_config Heap and Stack Configuration
188* There are two ways to adjust heap and stack configurations:
189* -# Editing source code files
190* -# Specifying via command line
191*
192* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400.
193*
194* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC
195* - <b>Editing source code files</b>\n
196* The heap and stack sizes are defined in the assembler startup files
197* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
198* Change the heap and stack sizes by modifying the following lines:\n
199* \code .equ Stack_Size, 0x00001000 \endcode
200* \code .equ Heap_Size, 0x00000400 \endcode
201*
202* - <b>Specifying via command line</b>\n
203* Change the heap and stack sizes passing the following commands to the compiler:\n
204* \code -D __STACK_SIZE=0x000000400 \endcode
205* \code -D __HEAP_SIZE=0x000000100 \endcode
206*
207* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK
208* - <b>Editing source code files</b>\n
209* The heap and stack sizes are defined in the assembler startup files
210* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
211* Change the heap and stack sizes by modifying the following lines:\n
212* \code Stack_Size EQU 0x00001000 \endcode
213* \code Heap_Size EQU 0x00000400 \endcode
214*
215* - <b>Specifying via command line</b>\n
216* Change the heap and stack sizes passing the following commands to the assembler:\n
217* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode
218* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode
219*
220* \subsubsection group_system_config_heap_stack_config_iar IAR
221* - <b>Editing source code files</b>\n
222* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf',
223* where 'xx' is the device family, and 'yy' is the target CPU; for example,
224* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
225* Change the heap and stack sizes by modifying the following lines:\n
226* \code Stack_Size EQU 0x00001000 \endcode
227* \code Heap_Size EQU 0x00000400 \endcode
228*
229* - <b>Specifying via command line</b>\n
230* Change the heap and stack sizes passing the following commands to the
231* linker (including quotation marks):\n
232* \code --define_symbol __STACK_SIZE=0x000000400 \endcode
233* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode
234*
235* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables
236* The CM0+ project and linker script build the CM0+ application image. Similarly,
237* the CM4 linker script builds the CM4 application image. Each specifies
238* locations, sizes, and contents of sections in memory. See
239* \ref group_system_config_device_memory_definition for the symbols and default
240* values.
241*
242* The cymcuelftool is invoked by a post-build command. The precise project
243* setting is IDE-specific.
244*
245* The cymcuelftool combines the two executables. The tool examines the
246* executables to ensure that memory regions either do not overlap, or contain
247* identical bytes (shared). If there are no problems, it creates a new ELF file
248* with the merged image, without changing any of the addresses or data.
249*
250* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition
251* The default interrupt handler functions are defined as weak functions to a dummy
252* handler in the startup file. The naming convention for the interrupt handler names
253* is \<interrupt_name\>_IRQHandler. A default interrupt handler can be overwritten in
254* user code by defining the handler function using the same name. For example:
255* \code
256* void scb_0_interrupt_IRQHandler(void)
257*{
258* ...
259*}
260* \endcode
261*
262* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM
263* This process uses memory sections defined in the linker script. The startup
264* code actually defines the contents of the vector table and performs the copy.
265* \subsubsection group_system_config_device_vector_table_gcc ARM GCC
266* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and
267* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld.
268* It defines sections and locations in memory.\n
269* Copy interrupt vectors from flash to RAM: \n
270* From: \code LONG (__Vectors) \endcode
271* To: \code LONG (__ram_vectors_start__) \endcode
272* Size: \code LONG (__Vectors_End - __Vectors) \endcode
273* The vector table address (and the vector table itself) are defined in the
274* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S).
275* The code in these files copies the vector table from Flash to RAM.
276* \subsubsection group_system_config_device_vector_table_mdk ARM MDK
277* The linker script file is 'xx_yy.scat', where 'xx' is the device family,
278* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and
279* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table
280* (RESET_RAM) shall be first in the RAM section.\n
281* RESET_RAM represents the vector table. It is defined in the assembler startup
282* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
283* The code in these files copies the vector table from Flash to RAM.
284*
285* \subsubsection group_system_config_device_vector_table_iar IAR
286* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and
287* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf.
288* This file defines the .intvec_ram section and its location.
289* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode
290* The vector table address (and the vector table itself) are defined in the
291* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s).
292* The code in these files copies the vector table from Flash to RAM.
293*
294* \section group_system_config_more_information More Information
295* Refer to the <a href="..\..\pdl_user_guide.pdf">PDL User Guide</a> for the
296* more details.
297*
298* \section group_system_config_MISRA MISRA Compliance
299*
300* <table class="doxtable">
301* <tr>
302* <th>MISRA Rule</th>
303* <th>Rule Class (Required/Advisory)</th>
304* <th>Rule Description</th>
305* <th>Description of Deviation(s)</th>
306* </tr>
307* <tr>
308* <td>2.3</td>
309* <td>R</td>
310* <td>The character sequence // shall not be used within a comment.</td>
311* <td>The comments provide a useful WEB link to the documentation.</td>
312* </tr>
313* </table>
314*
315* \section group_system_config_changelog Changelog
316* <table class="doxtable">
317* <tr>
318* <th>Version</th>
319* <th>Changes</th>
320* <th>Reason for Change</th>
321* </tr>
322* <tr>
323* <td rowspan="4">2.70</td>
324* <td>Updated \ref SystemCoreClockUpdate() implementation - The SysClk API is reused.</td>
325* <td>Code optimization.</td>
326* </tr>
327* <tr>
328* <td>Updated \ref SystemInit() implementation - The IPC7 structure is initialized for both cores.</td>
329* <td>Provided support for SysPM driver updates.</td>
330* </tr>
331* <tr>
332* <td>Updated the linker scripts.</td>
333* <td>Reserved FLASH area for the MCU boot headers.</td>
334* </tr>
335* <tr>
336* <td>Added System Pipe initialization for all devices. </td>
337* <td>Improved PDL usability according to user experience.</td>
338* </tr>
339* <tr>
340* <td>2.60</td>
341* <td>Updated linker scripts.</td>
342* <td>Provided support for new devices, updated usage of CM0p prebuilt image.</td>
343* </tr>
344* <tr>
345* <td>2.50</td>
346* <td>Updated assembler files, C files, linker scripts.</td>
347* <td>Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.</td>
348* </tr>
349* <tr>
350* <td>2.40</td>
351* <td>Updated assembler files, C files, linker scripts.</td>
352* <td>Added Arm Compiler 6 support.</td>
353* </tr>
354* <tr>
355* <td rowspan="2">2.30</td>
356* <td>Added assembler files, linker scripts for Mbed OS.</td>
357* <td>Added Arm Mbed OS embedded operating system support.</td>
358* </tr>
359* <tr>
360* <td>Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.</td>
361* <td>Enhanced PDL usability.</td>
362* </tr>
363* <tr>
364* <td>2.20</td>
365* <td>Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.</td>
366* <td>Changed the IPC driver configuration method from compile time to run time.</td>
367* </tr>
368* <tr>
369* <td rowspan="2"> 2.10</td>
370* <td>Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n
371* Removed $Sub$$main symbol for ARM MDK compiler.
372* </td>
373* <td>uVision Debugger support.</td>
374* </tr>
375* <tr>
376* <td>Updated description of the Startup behavior for Single-Core Devices. \n
377* Added note about WDT disabling by SystemInit() function.
378* </td>
379* <td>Documentation improvement.</td>
380* </tr>
381* <tr>
382* <td rowspan="4"> 2.0</td>
383* <td>Added restoring of FLL registers to the default state in SystemInit() API for single core devices.
384* Single core device support.
385* </td>
386* <td></td>
387* </tr>
388* <tr>
389* <td>Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n
390* Renamed 'wflash' memory region to 'em_eeprom'.
391* </td>
392* <td>Linker scripts usability improvement.</td>
393* </tr>
394* <tr>
395* <td>Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.</td>
396* <td>Reserved system resources for internal operations.</td>
397* </tr>
398* <tr>
399* <td>Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.</td>
400* <td>To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.</td>
401* </tr>
402* <tr>
403* <td>1.0</td>
404* <td>Initial version</td>
405* <td></td>
406* </tr>
407* </table>
408*
409*
410* \defgroup group_system_config_macro Macro
411* \{
412* \defgroup group_system_config_system_macro System
413* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status
414* \defgroup group_system_config_user_settings_macro User Settings
415* \}
416* \defgroup group_system_config_functions Functions
417* \{
418* \defgroup group_system_config_system_functions System
419* \defgroup group_system_config_cm4_functions Cortex-M4 Control
420* \}
421* \defgroup group_system_config_globals Global Variables
422*
423* \}
424*/
425
426/**
427* \addtogroup group_system_config_system_functions
428* \{
429* \details
430* The following system functions implement CMSIS Core functions.
431* Refer to the [CMSIS documentation]
432* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration")
433* for more details.
434* \}
435*/
436
437#ifdef __cplusplus
438extern "C" {
439#endif
440
441
442/*******************************************************************************
443* Include files
444*******************************************************************************/
445#include <stdint.h>
446
447
448/*******************************************************************************
449* Global preprocessor symbols/macros ('define')
450*******************************************************************************/
451#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
452 (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \
453 (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)))
454 #define CY_SYSTEM_CPU_CM0P 1UL
455#else
456 #define CY_SYSTEM_CPU_CM0P 0UL
457#endif
458
459
460/*******************************************************************************
461*
462* START OF USER SETTINGS HERE
463* ===========================
464*
465* All lines with '<<<' can be set by user.
466*
467*******************************************************************************/
468
469/**
470* \addtogroup group_system_config_user_settings_macro
471* \{
472*/
473
474
475/***************************************************************************//**
476* \brief Start address of the Cortex-M4 application ([address]UL)
477* <i>(USER SETTING)</i>
478*******************************************************************************/
479#if !defined (CY_CORTEX_M4_APPL_ADDR)
480 #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */
481#endif /* (CY_CORTEX_M4_APPL_ADDR) */
482
483
484/***************************************************************************//**
485* \brief IPC Semaphores allocation ([value]UL).
486* <i>(USER SETTING)</i>
487*******************************************************************************/
488#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */
489
490
491/***************************************************************************//**
492* \brief IPC Pipe definitions ([value]UL).
493* <i>(USER SETTING)</i>
494*******************************************************************************/
495#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */
496
497
498/*******************************************************************************
499*
500* END OF USER SETTINGS HERE
501* =========================
502*
503*******************************************************************************/
504
505/** \} group_system_config_user_settings_macro */
506
507
508/**
509* \addtogroup group_system_config_system_macro
510* \{
511*/
512
513#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
514 /** The Cortex-M0+ startup driver identifier */
515 #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U))
516#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
517
518#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN)
519 /** The Cortex-M4 startup driver identifier */
520 #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U))
521#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */
522
523/** \} group_system_config_system_macro */
524
525
526/**
527* \addtogroup group_system_config_system_functions
528* \{
529*/
530#if defined(__ARMCC_VERSION)
531 extern void SystemInit(void) __attribute__((constructor));
532#else
533 extern void SystemInit(void);
534#endif /* (__ARMCC_VERSION) */
535
536extern void SystemCoreClockUpdate(void);
537/** \} group_system_config_system_functions */
538
539
540/**
541* \addtogroup group_system_config_cm4_functions
542* \{
543*/
544extern uint32_t Cy_SysGetCM4Status(void);
545extern void Cy_SysEnableCM4(uint32_t vectorTableOffset);
546extern void Cy_SysDisableCM4(void);
547extern void Cy_SysRetainCM4(void);
548extern void Cy_SysResetCM4(void);
549/** \} group_system_config_cm4_functions */
550
551
552/** \cond */
553extern void Default_Handler (void);
554
555void Cy_SysIpcPipeIsrCm0(void);
556void Cy_SysIpcPipeIsrCm4(void);
557
558extern void Cy_SystemInit(void);
559extern void Cy_SystemInitFpuEnable(void);
560
561extern uint32_t cy_delayFreqKhz;
562extern uint8_t cy_delayFreqMhz;
563extern uint32_t cy_delay32kMs;
564/** \endcond */
565
566
567#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN)
568/**
569* \addtogroup group_system_config_cm4_status_macro
570* \{
571*/
572#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */
573#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */
574#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */
575#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */
576/** \} group_system_config_cm4_status_macro */
577
578#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */
579
580
581/*******************************************************************************
582* IPC Configuration
583* =========================
584*******************************************************************************/
585/* IPC CY_PIPE default configuration */
586#define CY_SYS_CYPIPE_CLIENT_CNT (8UL)
587
588#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */
589#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */
590#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */
591
592#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0)
593#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1)
594
595
596/******************************************************************************/
597/*
598 * The System pipe configuration defines the IPC channel number, interrupt
599 * number, and the pipe interrupt mask for the endpoint.
600 *
601 * The format of the endPoint configuration
602 * Bits[31:16] Interrupt Mask
603 * Bits[15:8 ] IPC interrupt
604 * Bits[ 7:0 ] IPC channel
605 */
606
607/* System Pipe addresses */
608/* CyPipe defines */
609
610#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 )
611
612#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
613 | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \
614 | CY_IPC_CHAN_CYPIPE_EP0)
615#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \
616 | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \
617 | CY_IPC_CHAN_CYPIPE_EP1)
618
619/******************************************************************************/
620
621
622/** \addtogroup group_system_config_globals
623* \{
624*/
625
626extern uint32_t SystemCoreClock;
627extern uint32_t cy_BleEcoClockFreqHz;
628extern uint32_t cy_Hfclk0FreqHz;
629extern uint32_t cy_PeriClkFreqHz;
630
631/** \} group_system_config_globals */
632
633
634
635/** \cond INTERNAL */
636/*******************************************************************************
637* Backward compatibility macros. The following code is DEPRECATED and must
638* not be used in new projects
639*******************************************************************************/
640
641/* BWC defines for functions related to enter/exit critical section */
642#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection
643#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection
644#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0)
645#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1)
646#define cy_delayFreqHz (SystemCoreClock)
647
648/** \endcond */
649
650#ifdef __cplusplus
651}
652#endif
653
654#endif /* _SYSTEM_PSOC6_H_ */
655
656
657/* [] END OF FILE */