| INFINEON\DovhalA | 21babb7 | 2025-07-18 10:36:03 +0300 | [diff] [blame^] | 1 | /******************************************************************************** |
| 2 | * \copyright |
| 3 | * (c) 2025, Cypress Semiconductor Corporation (an Infineon company) or |
| 4 | * an affiliate of Cypress Semiconductor Corporation. |
| 5 | * |
| 6 | * SPDX-License-Identifier: Apache-2.0 |
| 7 | * |
| 8 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 9 | * you may not use this file except in compliance with the License. |
| 10 | * You may obtain a copy of the License at |
| 11 | * |
| 12 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 13 | * |
| 14 | * Unless required by applicable law or agreed to in writing, software |
| 15 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 16 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 17 | * See the License for the specific language governing permissions and |
| 18 | * limitations under the License. |
| 19 | *******************************************************************************/ |
| 20 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 21 | #ifndef PLATFORM_H |
| 22 | #define PLATFORM_H |
| 23 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 24 | #include <inttypes.h> |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 25 | #include <stdio.h> |
| 26 | |
| 27 | #include "cy_pdl.h" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 28 | #include "cy_retarget_io.h" |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 29 | #include "cybsp.h" |
| 30 | #include "cycfg.h" |
| 31 | #include "cyhal.h" |
| 32 | #include "cyhal_wdt.h" |
| INFINEON\DovhalA | 3b578f3 | 2024-11-29 01:06:04 +0200 | [diff] [blame] | 33 | #include "cy_wdt.h" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 34 | |
| 35 | #if defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) |
| 36 | #include "flash_qspi.h" |
| 37 | #endif /* defined(CY_BOOT_USE_EXTERNAL_FLASH) || defined(CYW20829) */ |
| 38 | |
| 39 | #ifdef BOOT_IMAGE |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 40 | #define IMAGE_TYPE "BOOT" |
| 41 | #define BLINK_PERIOD (1000u) |
| 42 | #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 1 sec period\r\n" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 43 | #elif defined(UPGRADE_IMAGE) |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 44 | #define IMAGE_TYPE "UPGRADE" |
| 45 | #define BLINK_PERIOD (250u) |
| 46 | #define GREETING_MESSAGE_INFO "[BlinkyApp] Red led blinks with 0.25 sec period\r\n" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 47 | #else |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 48 | #error "[BlinkyApp] Please specify type of image: -DBOOT_IMAGE or -DUPGRADE_IMAGE\r\n" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 49 | #endif /* BOOT_IMAGE */ |
| 50 | |
| INFINEON\DovhalA | 21babb7 | 2025-07-18 10:36:03 +0300 | [diff] [blame^] | 51 | #if defined(MCUBOOT_DIRECT_XIP) |
| 52 | #undef IMAGE_TYPE |
| 53 | #if APP_SLOT == 1 |
| 54 | #define IMAGE_TYPE "Primary slot" |
| 55 | #else |
| 56 | #define IMAGE_TYPE "Secondary slot" |
| 57 | #endif |
| 58 | #endif |
| 59 | |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 60 | #define GREETING_MESSAGE_VER "[BlinkyApp] Version:" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 61 | |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 62 | #define WATCHDOG_FREE_MESSAGE "[BlinkyApp] Turn off watchdog timer\r\n" |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 63 | |
| 64 | #define SMIF_ID (1U) /* Assume SlaveSelect_0 is used for External Memory */ |
| 65 | |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 66 | static const char* core33_message = "CM33"; |
| 67 | static const char* core0p_message = "CM0P"; |
| 68 | static const char* core4_message = "CM4"; |
| 69 | static const char* core7_message = "CM7"; |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 70 | |
| 71 | #if defined(__cplusplus) |
| 72 | extern "C" { |
| 73 | #endif /* defined(__cplusplus) */ |
| 74 | |
| 75 | static inline const char* test_app_init_hardware(void) |
| 76 | { |
| 77 | const char* detect_core_message = NULL; |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 78 | (void)core33_message; |
| 79 | (void)core0p_message; |
| 80 | (void)core4_message; |
| 81 | (void)core7_message; |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 82 | cy_rslt_t res = CY_RSLT_TYPE_ERROR; |
| 83 | |
| 84 | const cy_stc_gpio_pin_config_t LED_config = { |
| 85 | .outVal = 1, |
| 86 | .driveMode = CY_GPIO_DM_STRONG_IN_OFF, |
| 87 | .hsiom = HSIOM_SEL_GPIO, |
| 88 | .intEdge = CY_GPIO_INTR_DISABLE, |
| 89 | .intMask = 0UL, |
| 90 | .vtrip = CY_GPIO_VTRIP_CMOS, |
| 91 | .slewRate = CY_GPIO_SLEW_FAST, |
| 92 | .driveSel = CY_GPIO_DRIVE_FULL, |
| 93 | .vregEn = 0UL, |
| 94 | .ibufMode = 0UL, |
| 95 | .vtripSel = 0UL, |
| 96 | .vrefSel = 0UL, |
| 97 | .vohSel = 0UL, |
| 98 | }; |
| 99 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 100 | cybsp_init(); |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 101 | /* enable interrupts */ |
| 102 | __enable_irq(); |
| 103 | |
| 104 | /* Initialize led port */ |
| 105 | Cy_GPIO_Pin_Init(LED_PORT, LED_PIN, &LED_config); |
| 106 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 107 | res = cy_retarget_io_init(CY_DEBUG_UART_TX, CY_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE); |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 108 | |
| 109 | if (res != CY_RSLT_SUCCESS) { |
| 110 | CY_ASSERT(0); |
| 111 | /* Loop forever... */ |
| 112 | for (;;) { |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | printf("\n===========================\r\n"); |
| 117 | printf("%s %s\r\n", GREETING_MESSAGE_VER, IMG_VER_MSG); |
| 118 | |
| 119 | #ifdef CYW20829 |
| 120 | detect_core_message = core33_message; |
| 121 | |
| 122 | printf("===========================\r\n"); |
| 123 | |
| 124 | cy_en_smif_status_t rc = CY_SMIF_CMD_NOT_FOUND; |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 125 | |
| 126 | rc = qspi_init_sfdp(SMIF_ID); |
| 127 | if (CY_SMIF_SUCCESS == rc) { |
| 128 | printf("[BlinkyApp] External Memory initialized w/ SFDP. \r\n"); |
| 129 | } else { |
| 130 | printf("[BlinkyApp] External Memory initialization w/ SFDP FAILED: 0x%" PRIx32 " \r\n", (uint32_t)rc); |
| 131 | } |
| 132 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 133 | #else |
| 134 | /* Determine on which core this app is running by polling CPUSS_IDENTITY register. |
| 135 | * This register contains bits field [8:11]. This field specifies the bus master |
| 136 | * identifier of the transfer that reads the register. |
| 137 | */ |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 138 | |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 139 | #ifdef APP_CM0P |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 140 | en_prot_master_t core = _FLD2VAL(CPUSS_IDENTITY_MS, CPUSS->IDENTITY); |
| 141 | |
| 142 | if (CPUSS_MS_ID_CM4 == core) { |
| 143 | printf("\n[BlinkyApp] is compiled for CM0P core, started on CM4 instead. Execution Halted.\n"); |
| 144 | CY_ASSERT(0); |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 145 | } else if (CPUSS_MS_ID_CM0 == core) { |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 146 | detect_core_message = core0p_message; |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 147 | } else |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 148 | #endif /* APP_CM0P */ |
| 149 | { |
| 150 | detect_core_message = core4_message; |
| 151 | } |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 152 | #ifdef APP_CM7 |
| 153 | if (CPUSS_MS_ID_CM7_0 == _FLD2VAL(CPUSS_IDENTITY_MS, CPUSS->IDENTITY)) { |
| 154 | detect_core_message = core7_message; |
| 155 | } |
| 156 | #endif |
| 157 | |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 158 | printf("===========================\r\n"); |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 159 | #endif /* CYW20829 */ |
| 160 | printf("[BlinkyApp] GPIO initialized \r\n"); |
| 161 | printf("[BlinkyApp] UART initialized \r\n"); |
| 162 | printf("[BlinkyApp] Retarget I/O set to 115200 baudrate \r\n"); |
| INFINEON\DovhalA | 3b578f3 | 2024-11-29 01:06:04 +0200 | [diff] [blame] | 163 | #if defined(USE_WDT_PDL) |
| 164 | Cy_WDT_ClearWatchdog(); |
| 165 | #else |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 166 | cyhal_wdt_kick(NULL); |
| INFINEON\DovhalA | 3b578f3 | 2024-11-29 01:06:04 +0200 | [diff] [blame] | 167 | #endif |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 168 | |
| Roman Okhrimenko | dc0ca08 | 2023-06-21 20:49:51 +0300 | [diff] [blame] | 169 | return (detect_core_message); |
| Dovhal Artem (CSUKR CSS ICW SW FW 1) | f7a3d1b | 2022-04-01 15:07:37 +0000 | [diff] [blame] | 170 | } |
| 171 | |
| 172 | #if defined(__cplusplus) |
| 173 | } |
| 174 | #endif /* defined(__cplusplus) */ |
| 175 | |
| 176 | #endif /* PLATFORM_H */ |