More work on CMSIS-RTOS documentation including RTX Implementation
diff --git a/CMSIS/RTOS/Template/CPP/Mail.h b/CMSIS/RTOS/Template/CPP/Mail.h
new file mode 100644
index 0000000..d4056f4
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mail.h
@@ -0,0 +1,89 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MAIL_H
+#define MAIL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Mail class allow to control, send, receive, or wait for mail.
+ A mail is a memory block that is send to a thread or interrupt service routine.
+ \tparam T data type of a single message element.
+ \tparam queue_sz maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Mail {
+public:
+ /*! Create and Initialise Mail queue. */
+ Mail() {
+ #ifdef CMSIS_OS_RTX
+ memset(_mail_q, 0, sizeof(_mail_q));
+ _mail_p[0] = _mail_q;
+
+ memset(_mail_m, 0, sizeof(_mail_m));
+ _mail_p[1] = _mail_m;
+
+ _mail_def.pool = _mail_p;
+ _mail_def.queue_sz = queue_sz;
+ _mail_def.item_sz = sizeof(T);
+ #endif
+ _mail_id = osMailCreate(&_mail_def, NULL);
+ }
+
+ /*! Allocate a memory block of type T
+ \param millisec timeout value or 0 in case of no time-out. (default: 0).
+ \return pointer to memory block that can be filled with mail or NULL in case error.
+ */
+ T* alloc(uint32_t millisec=0) {
+ return (T*)osMailAlloc(_mail_id, millisec);
+ }
+
+ /*! Allocate a memory block of type T and set memory block to zero.
+ \param millisec timeout value or 0 in case of no time-out. (default: 0).
+ \return pointer to memory block that can be filled with mail or NULL in case error.
+ */
+ T* calloc(uint32_t millisec=0) {
+ return (T*)osMailCAlloc(_mail_id, millisec);
+ }
+
+ /*! Put a mail in the queue.
+ \param mptr memory block previously allocated with Mail::alloc or Mail::calloc.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus put(T *mptr) {
+ return osMailPut(_mail_id, (void*)mptr);
+ }
+
+ /*! Get a mail from a queue.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event that contains mail information or error code.
+ */
+ osEvent get(uint32_t millisec=osWaitForever) {
+ return osMailGet(_mail_id, millisec);
+ }
+
+ /*! Free a memory block from a mail.
+ \param mptr pointer to the memory block that was obtained with Mail::get.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus free(T *mptr) {
+ return osMailFree(_mail_id, (void*)mptr);
+ }
+
+private:
+ osMailQId _mail_id;
+ osMailQDef_t _mail_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _mail_q[4+(queue_sz)];
+ uint32_t _mail_m[3+((sizeof(T)+3)/4)*(queue_sz)];
+ void *_mail_p[2];
+#endif
+};
+
+}
+
+#endif
+
diff --git a/CMSIS/RTOS/Template/CPP/MemoryPool.h b/CMSIS/RTOS/Template/CPP/MemoryPool.h
new file mode 100644
index 0000000..f8325e8
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/MemoryPool.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MEMORYPOOL_H
+#define MEMORYPOOL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! Define and manage fixed-size memory pools of objects of a given type.
+ \tparam T data type of a single object (element).
+ \tparam queue_sz maximum number of objects (elements) in the memory pool.
+*/
+template<typename T, uint32_t pool_sz>
+class MemoryPool {
+public:
+ /*! Create and Initialize a memory pool. */
+ MemoryPool() {
+ #ifdef CMSIS_OS_RTX
+ memset(_pool_m, 0, sizeof(_pool_m));
+ _pool_def.pool = _pool_m;
+
+ _pool_def.pool_sz = pool_sz;
+ _pool_def.item_sz = sizeof(T);
+ #endif
+ _pool_id = osPoolCreate(&_pool_def);
+ }
+
+ /*! Allocate a memory block of type T from a memory pool.
+ \return address of the allocated memory block or NULL in case of no memory available.
+ */
+ T* alloc(void) {
+ return (T*)osPoolAlloc(_pool_id);
+ }
+
+ /*! Allocate a memory block of type T from a memory pool and set memory block to zero.
+ \return address of the allocated memory block or NULL in case of no memory available.
+ */
+ T* calloc(void) {
+ return (T*)osPoolCAlloc(_pool_id);
+ }
+
+ /*! Return an allocated memory block back to a specific memory pool.
+ \param address of the allocated memory block that is returned to the memory pool.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus free(T *block) {
+ return osPoolFree(_pool_id, (void*)block);
+ }
+
+private:
+ osPoolId _pool_id;
+ osPoolDef_t _pool_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _pool_m[3+((sizeof(T)+3)/4)*(pool_sz)];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Mutex.cpp b/CMSIS/RTOS/Template/CPP/Mutex.cpp
new file mode 100644
index 0000000..17469f2
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mutex.cpp
@@ -0,0 +1,31 @@
+#include "Mutex.h"
+
+#include <string.h>
+//#include "error.h"
+
+namespace rtos {
+
+Mutex::Mutex() {
+#ifdef CMSIS_OS_RTX
+ memset(_mutex_data, 0, sizeof(_mutex_data));
+ _osMutexDef.mutex = _mutex_data;
+#endif
+ _osMutexId = osMutexCreate(&_osMutexDef);
+ if (_osMutexId == NULL) {
+// error("Error initializing the mutex object\n");
+ }
+}
+
+osStatus Mutex::lock(uint32_t millisec) {
+ return osMutexWait(_osMutexId, millisec);
+}
+
+bool Mutex::trylock() {
+ return (osMutexWait(_osMutexId, 0) == osOK);
+}
+
+osStatus Mutex::unlock() {
+ return osMutexRelease(_osMutexId);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Mutex.h b/CMSIS/RTOS/Template/CPP/Mutex.h
new file mode 100644
index 0000000..09d3802
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mutex.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MUTEX_H
+#define MUTEX_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Mutex class is used to synchronise the execution of threads.
+ This is for example used to protect access to a shared resource.
+*/
+class Mutex {
+public:
+ /*! Create and Initialize a Mutex object */
+ Mutex();
+
+ /*! Wait until a Mutex becomes available.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever)
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus lock(uint32_t millisec=osWaitForever);
+
+ /*! Try to lock the mutex, and return immediately
+ \return true if the mutex was acquired, false otherwise.
+ */
+ bool trylock();
+
+ /*! Unlock the mutex that has previously been locked by the same thread
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus unlock();
+
+private:
+ osMutexId _osMutexId;
+ osMutexDef_t _osMutexDef;
+#ifdef CMSIS_OS_RTX
+ int32_t _mutex_data[3];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Queue.h b/CMSIS/RTOS/Template/CPP/Queue.h
new file mode 100644
index 0000000..f001131
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Queue.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+#include "error.h"
+
+namespace rtos {
+
+/*! The Queue class allow to control, send, receive, or wait for messages.
+ A message can be a integer or pointer value to a certain type T that is send
+ to a thread or interrupt service routine.
+ \tparam T data type of a single message element.
+ \tparam queue_sz maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Queue {
+public:
+ /*! Create and initialise a message Queue. */
+ Queue() {
+ #ifdef CMSIS_OS_RTX
+ memset(_queue_q, 0, sizeof(_queue_q));
+ _queue_def.pool = _queue_q;
+ _queue_def.queue_sz = queue_sz;
+ #endif
+ _queue_id = osMessageCreate(&_queue_def, NULL);
+ if (_queue_id == NULL) {
+ error("Error initialising the queue object\n");
+ }
+ }
+
+ /*! Put a message in a Queue.
+ \param data message pointer.
+ \param millisec timeout value or 0 in case of no time-out. (default: 0)
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus put(T* data, uint32_t millisec=0) {
+ return osMessagePut(_queue_id, (uint32_t)data, millisec);
+ }
+
+ /*! Get a message or Wait for a message from a Queue.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event information that includes the message and the status code.
+ */
+ osEvent get(uint32_t millisec=osWaitForever) {
+ return osMessageGet(_queue_id, millisec);
+ }
+
+private:
+ osMessageQId _queue_id;
+ osMessageQDef_t _queue_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _queue_q[4+(queue_sz)];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/RtosTimer.cpp b/CMSIS/RTOS/Template/CPP/RtosTimer.cpp
new file mode 100644
index 0000000..0f83215
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/RtosTimer.cpp
@@ -0,0 +1,28 @@
+#include "RtosTimer.h"
+
+#include <string.h>
+
+#include "cmsis_os.h"
+//#include "error.h"
+
+namespace rtos {
+
+RtosTimer::RtosTimer(void (*periodic_task)(void const *argument), os_timer_type type, void *argument) {
+#ifdef CMSIS_OS_RTX
+ _timer.ptimer = periodic_task;
+
+ memset(_timer_data, 0, sizeof(_timer_data));
+ _timer.timer = _timer_data;
+#endif
+ _timer_id = osTimerCreate(&_timer, type, argument);
+}
+
+osStatus RtosTimer::start(uint32_t millisec) {
+ return osTimerStart(_timer_id, millisec);
+}
+
+osStatus RtosTimer::stop(void) {
+ return osTimerStop(_timer_id);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/RtosTimer.h b/CMSIS/RTOS/Template/CPP/RtosTimer.h
new file mode 100644
index 0000000..6e989c1
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/RtosTimer.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef TIMER_H
+#define TIMER_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The RtosTimer class allow creating and and controlling of timer functions in the system.
+ A timer function is called when a time period expires whereby both on-shot and
+ periodic timers are possible. A timer can be started, restarted, or stopped.
+
+ Timers are handled in the thread osTimerThread.
+ Callback functions run under control of this thread and may use CMSIS-RTOS API calls.
+*/
+class RtosTimer {
+public:
+ /*! Create and Start timer.
+ \param task name of the timer call back function.
+ \param type osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+ \param argument argument to the timer call back function. (default: NULL)
+ */
+ RtosTimer(void (*task)(void const *argument),
+ os_timer_type type=osTimerPeriodic,
+ void *argument=NULL);
+
+ /*! Stop the timer.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus stop(void);
+
+ /*! start a timer.
+ \param millisec time delay value of the timer.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus start(uint32_t millisec);
+
+private:
+ osTimerId _timer_id;
+ osTimerDef_t _timer;
+#ifdef CMSIS_OS_RTX
+ uint32_t _timer_data[5];
+#endif
+};
+
+}
+
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Semaphore.cpp b/CMSIS/RTOS/Template/CPP/Semaphore.cpp
new file mode 100644
index 0000000..0b7a827
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Semaphore.cpp
@@ -0,0 +1,24 @@
+#include "Semaphore.h"
+
+#include <string.h>
+//#include "error.h"
+
+namespace rtos {
+
+Semaphore::Semaphore(int32_t count) {
+#ifdef CMSIS_OS_RTX
+ memset(_semaphore_data, 0, sizeof(_semaphore_data));
+ _osSemaphoreDef.semaphore = _semaphore_data;
+#endif
+ _osSemaphoreId = osSemaphoreCreate(&_osSemaphoreDef, count);
+}
+
+int32_t Semaphore::wait(uint32_t millisec) {
+ return osSemaphoreWait(_osSemaphoreId, millisec);
+}
+
+osStatus Semaphore::release(void) {
+ return osSemaphoreRelease(_osSemaphoreId);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Semaphore.h b/CMSIS/RTOS/Template/CPP/Semaphore.h
new file mode 100644
index 0000000..a94f277
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Semaphore.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Semaphore class is used to manage and protect access to a set of shared resources. */
+class Semaphore {
+public:
+ /*! Create and Initialize a Semaphore object used for managing resources.
+ \param number of available resources; maximum index value is (count-1).
+ */
+ Semaphore(int32_t count);
+
+ /*! Wait until a Semaphore resource becomes available.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return number of available tokens, or -1 in case of incorrect parameters
+ */
+ int32_t wait(uint32_t millisec=osWaitForever);
+
+ /*! Release a Semaphore resource that was obtain with Semaphore::wait.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus release(void);
+
+private:
+ osSemaphoreId _osSemaphoreId;
+ osSemaphoreDef_t _osSemaphoreDef;
+#ifdef CMSIS_OS_RTX
+ uint32_t _semaphore_data[2];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Thread.cpp b/CMSIS/RTOS/Template/CPP/Thread.cpp
new file mode 100644
index 0000000..97d8b7b
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Thread.cpp
@@ -0,0 +1,51 @@
+#include "Thread.h"
+
+namespace rtos {
+
+Thread::Thread(void (*task)(void const *argument),
+ void *argument,
+ osPriority priority,
+ uint32_t stacksize) {
+ // The actual fields of os_thread_def are implementation specific in every CMSIS-RTOS
+#ifdef CMSIS_OS_RTX
+ _thread_def.pthread = task;
+ _thread_def.tpriority = priority;
+ _thread_def.instances = 1;
+ _thread_def.stacksize = stacksize;
+#endif
+ _tid = osThreadCreate(&_thread_def, argument);
+}
+
+osStatus Thread::terminate() {
+ return osThreadTerminate(_tid);
+}
+
+osStatus Thread::set_priority(osPriority priority) {
+ return osThreadSetPriority(_tid, priority);
+}
+
+osPriority Thread::get_priority() {
+ return osThreadGetPriority(_tid);
+}
+
+int32_t Thread::signal_set(int32_t signals) {
+ return osSignalSet(_tid, signals);
+}
+
+osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {
+ return osSignalWait(signals, millisec);
+}
+
+osStatus Thread::wait(uint32_t millisec) {
+ return osDelay(millisec);
+}
+
+osStatus Thread::yield() {
+ return osThreadYield();
+}
+
+osThreadId Thread::gettid() {
+ return osThreadGetId();
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Thread.h b/CMSIS/RTOS/Template/CPP/Thread.h
new file mode 100644
index 0000000..d1fd6ee
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Thread.h
@@ -0,0 +1,78 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef THREAD_H
+#define THREAD_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+#define DEFAULT_STACK_SIZE 0x1000
+
+namespace rtos {
+
+/*! The Thread class allow defining, creating, and controlling thread functions in the system. */
+class Thread {
+public:
+ /*! Create a new thread, and start it executing the specified function.
+ \param task function to be executed by this thread.
+ \param argument pointer that is passed to the thread function as start argument. (default: NULL).
+ \param priority initial priority of the thread function. (default: osPriorityNormal).
+ \param stacksz stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+ */
+ Thread(void (*task)(void const *argument),
+ void *argument=NULL,
+ osPriority priority=osPriorityNormal,
+ uint32_t stacksize=DEFAULT_STACK_SIZE);
+
+ /*! Terminate execution of a thread and remove it from Active Threads
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus terminate();
+
+ /*! Set priority of an active thread
+ \param priority new priority value for the thread function.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus set_priority(osPriority priority);
+
+ /*! Get priority of an active thread
+ \ return current priority value of the thread function.
+ */
+ osPriority get_priority();
+
+ /*! Set the specified Signal Flags of an active thread.
+ \param signals specifies the signal flags of the thread that should be set.
+ \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+ */
+ int32_t signal_set(int32_t signals);
+
+ /*! Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
+ \param signals wait until all specified signal flags set or 0 for any single signal flag.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event flag information or error code.
+ */
+ static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);
+
+
+ /*! Wait for a specified time period in millisec:
+ \param millisec time delay value
+ \return status code that indicates the execution status of the function.
+ */
+ static osStatus wait(uint32_t millisec);
+
+ /*! Pass control to next thread that is in state READY.
+ \return status code that indicates the execution status of the function.
+ */
+ static osStatus yield();
+
+ /*! Get the thread id of the current running thread.
+ \return thread ID for reference by other functions or NULL in case of error.
+ */
+ static osThreadId gettid();
+
+private:
+ osThreadId _tid;
+ osThreadDef_t _thread_def;
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/rtos.h b/CMSIS/RTOS/Template/CPP/rtos.h
new file mode 100644
index 0000000..db1a785
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/rtos.h
@@ -0,0 +1,17 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited. All rights reserved.
+ */
+#ifndef RTOS_H
+#define RTOS_H
+
+#include "Thread.h"
+#include "Mutex.h"
+#include "RtosTimer.h"
+#include "Semaphore.h"
+#include "Mail.h"
+#include "MemoryPool.h"
+#include "Queue.h"
+
+using namespace rtos;
+
+#endif
diff --git a/CMSIS/RTOS/Template/Hist.txt b/CMSIS/RTOS/Template/Hist.txt
new file mode 100644
index 0000000..8aa5cff
--- /dev/null
+++ b/CMSIS/RTOS/Template/Hist.txt
@@ -0,0 +1,39 @@
+This file describes the changes of the CMSIS-RTOS API interface for internal use
+================================================================================
+
+changes V1.0 -> V1.01
+=====================
+
+Preparation for C++ class interface
+===================================
+---> const attribute moved to macros (to support C++ interface).
+const attribute removed from typedef's (to allow C++ class interface).
+osThreadDef_t, osTimerDef_t, osMutexDef_t, osSemaphoreDef_t, osPoolDef_t, osMessageQDef_t, osMailQDef_t.
+
+const added to the osXxxxDef macros:
+osThreadDef, osTimerDef, osMutexDef, osSemaphoreDef, osPoolDef, osMessageQDef, osMailQDef
+
+Allow to remove Timer/Mutex/Semaphore objects
+=============================================
+Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+
+
+Added function that initializes (but does not start) the osKernel
+=================================================================
+Added: osKernelInitialize
+osKernelStart changed to osKernelStart (void)
+
+====================================================================
+
+Version 1.02
+ Control functions for short timeouts in microsecond resolution:
+ Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTick_uSec
+ Removed: osSignalGet
+
+Still open for discussion
+=========================
+Adding Low Power extensions
+We have added Low Power extensions to RTX a while ago.
+http://www.keil.com/support/man/docs/rlarm/rlarm_ar_low_power.htm
+
+We should look into this solution (os_suspend/os_resume) and add this functionality to CMSIS RTOS by extending the API. Probably we can use the same two functions (renamed to fit CMSIS RTOS) but we need to check if this fits (for example os_resume parameter is in system ticks same as in os_time_get)
diff --git a/CMSIS/RTOS/Template/Template.uvopt b/CMSIS/RTOS/Template/Template.uvopt
new file mode 100644
index 0000000..eb96e04
--- /dev/null
+++ b/CMSIS/RTOS/Template/Template.uvopt
@@ -0,0 +1,364 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Target 1</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
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diff --git a/CMSIS/RTOS/Template/Template.uvproj b/CMSIS/RTOS/Template/Template.uvproj
new file mode 100644
index 0000000..56c7533
--- /dev/null
+++ b/CMSIS/RTOS/Template/Template.uvproj
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+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x10000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\Template</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x10000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Source Group 1</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_LPC177x_8x.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_LPC177x_8x.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_LPC177x_8x.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_LPC177x_8x.c</FilePath>
+ </File>
+ <File>
+ <FileName>os_sample.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\os_sample.c</FilePath>
+ </File>
+ <File>
+ <FileName>os_sample1.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\os_sample1.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>CPP</GroupName>
+ <Files>
+ <File>
+ <FileName>Mutex.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Mutex.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>RtosTimer.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\RtosTimer.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>Semaphore.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Semaphore.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>Thread.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Thread.cpp</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Documentation</GroupName>
+ <Files>
+ <File>
+ <FileName>cmsis_os.txt</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\src\cmsis_os.txt</FilePath>
+ </File>
+ <File>
+ <FileName>doxygen_rtos.bat</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\doxygen_rtos.bat</FilePath>
+ </File>
+ <File>
+ <FileName>index.html</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\html\index.html</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/Template/my_objects.h b/CMSIS/RTOS/Template/my_objects.h
new file mode 100644
index 0000000..d99810c
--- /dev/null
+++ b/CMSIS/RTOS/Template/my_objects.h
@@ -0,0 +1,15 @@
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+extern void thread_sample (void const *argument); // prototype
+
+typedef struct a {
+ char y[100];
+} a_element;
+
+osThreadDef (thread_sample, osPriorityBelowNormal, 2, 100);
+
+osPoolDef(MyPool, 10, struct a);
+osMessageQDef(MyMessage, 10, a_element *);
+osMailQDef(MyMail, 10, a_element);
+
+
diff --git a/CMSIS/RTOS/Template/os_sample.c b/CMSIS/RTOS/Template/os_sample.c
new file mode 100644
index 0000000..a6d0767
--- /dev/null
+++ b/CMSIS/RTOS/Template/os_sample.c
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 30. November 2011
+ * $Revision: V0.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: os_sample.c
+ *
+ * Description: This file shows the usage of the CMSIS-RTOS API.
+ *
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * -------------------------------------------------------------------- */
+
+
+#include "my_objects.h" // Define CMSIS OS Objects
+
+// dummy functions since there is no OS today
+
+/// Add a thread to ActiveThreads and set it to state READY
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { return osOK; }
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus osThreadTerminate (osThreadId thread_id) { return osOK; }
+
+/// Change prority of an existing thread
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) { return osOK; }
+
+/// Get current prority of an existing thread
+osPriority osThreadGetPriority (osThreadId thread_id) { return osPriorityNormal; }
+
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { return NULL; }
+
+osThreadId osThreadGetId (void) { return 0; }
+
+
+osStatus status;
+osThreadId thread_sample1;
+osThreadId thread_sample2;
+
+osMessageQDef(TcpMessageQ0, 10, a_element *);
+osMessageQDef(TcpMessageQ1, 10, a_element *);
+osMessageQDef(TcpMessageQ2, 10, a_element *);
+osMessageQDef(TcpMessageQ3, 10, a_element *);
+
+const osMessageQDef_t *TcpMessageQDef[4]
+#if 1
+ = {
+ osMessageQ(TcpMessageQ0),
+ osMessageQ(TcpMessageQ1),
+ osMessageQ(TcpMessageQ2),
+ osMessageQ(TcpMessageQ3),
+}
+#endif
+;
+
+osMessageQId TcpMessageQ[4];
+
+void CreateMessageQueues (void) {
+ uint32_t i;
+
+ for (i = 0; i < 4; i++) {
+ TcpMessageQ[i] = osMessageCreate (TcpMessageQDef[i], NULL);
+ }
+}
+
+
+int main (void) {
+ thread_sample1 = osThreadCreate (osThread (thread_sample), NULL);
+ thread_sample2 = osThreadCreate (osThread (thread_sample), NULL);
+}
+
diff --git a/CMSIS/RTOS/Template/os_sample1.c b/CMSIS/RTOS/Template/os_sample1.c
new file mode 100644
index 0000000..c78912c
--- /dev/null
+++ b/CMSIS/RTOS/Template/os_sample1.c
@@ -0,0 +1,34 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 30. November 2011
+ * $Revision: V0.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: os_sample1.c
+ *
+ * Description: This file shows the usage of the CMSIS-RTOS API.
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * -------------------------------------------------------------------- */
+
+
+#define osObjectsExternal
+#include "my_objects.h" // Reference CMSIS OS Objects
+
+
+void thread_sample (void const *argument) {
+ osThreadId my_thread;
+ osPriority my_priority;
+ int i = 1000;
+
+ my_thread = osThreadGetId();
+ my_priority = osThreadGetPriority (my_thread); // Get priority of own thread
+ while (i > 0) {
+ osThreadSetPriority (my_thread, osPriorityAboveNormal);
+ i--;
+ }
+ osThreadSetPriority (my_thread, my_priority);
+ osThreadTerminate (my_thread); // terminate own thread
+}
diff --git a/CMSIS/RTOS/Template/startup_LPC177x_8x.s b/CMSIS/RTOS/Template/startup_LPC177x_8x.s
new file mode 100644
index 0000000..536adce
--- /dev/null
+++ b/CMSIS/RTOS/Template/startup_LPC177x_8x.s
@@ -0,0 +1,301 @@
+;/*****************************************************************************
+; * @file: startup_LPC177x_8x.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC177x_8x Device Series
+; * @version: V1.20
+; * @date: 07. October 2010
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPIFI_IRQHandler ; 29: SPIFI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD MCI_IRQHandler ; 45: SD/MMC card I/F
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+ DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
+ DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
+ DCD UART4_IRQHandler ; 51: UART4
+ DCD SSP2_IRQHandler ; 52: SSP2
+ DCD LCD_IRQHandler ; 53: LCD
+ DCD GPIO_IRQHandler ; 54: GPIO
+ DCD PWM0_IRQHandler ; 55: PWM0
+ DCD EEPROM_IRQHandler ; 56: EEPROM
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT MCI_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+ EXPORT USBActivity_IRQHandler [WEAK]
+ EXPORT CANActivity_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT SSP2_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT GPIO_IRQHandler [WEAK]
+ EXPORT PWM0_IRQHandler [WEAK]
+ EXPORT EEPROM_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPIFI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+MCI_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+USBActivity_IRQHandler
+CANActivity_IRQHandler
+UART4_IRQHandler
+SSP2_IRQHandler
+LCD_IRQHandler
+GPIO_IRQHandler
+PWM0_IRQHandler
+EEPROM_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/RTOS/Template/system_LPC177x_8x.c b/CMSIS/RTOS/Template/system_LPC177x_8x.c
new file mode 100644
index 0000000..ca9e2ff
--- /dev/null
+++ b/CMSIS/RTOS/Template/system_LPC177x_8x.c
@@ -0,0 +1,455 @@
+/***********************************************************************//**
+ * @file system_LPC177x_8x.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC177x_8x Device Series
+ * @version V1.11
+ * @date 10. November. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+
+#include <stdint.h>
+#include "LPC177x_8x.h"
+#include "system_LPC177x_8x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.0> EMC_SHIFT: EMC Shift enable
+// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
+// <1=> Static CS addresses start at LSB 0 regardless of memory width
+// <o1.1> EMC_RESET: EMC Reset disable
+// <0=> EMC will be reset by any chip reset
+// <1=> Portions of EMC will only be reset by POR or BOR
+// <o1.2> EMC_BURST: EMC Burst disable
+// <o1.3> MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
+// <0=> SD_PWR is active low
+// <1=> SD_PWR is active high
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 25 MHz
+// <o1.5> OSCEN: Main Oscillator enable
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0> CLKSRC: sysclk and PLL0 clock source selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> PLL out clock = (F_cco / (2 * P))
+// <i> F_cco = (F_in * M * 2 * P)
+// <i> F_in must be in the range of 1 MHz to 25 MHz
+// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+// <o4.0..4> MSEL: PLL Multiplier Selection
+// <i> M Value
+// <1-32><#-1>
+// <o4.5..6> PSEL: PLL Divider Selection
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (Alt PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> PLL out clock = (F_cco / (2 * P))
+// <i> F_cco = (F_in * M * 2 * P)
+// <i> F_in must be in the range of 1 MHz to 25 MHz
+// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <i> M Value
+// <1-32><#-1>
+// <o6.5..6> PSEL: PLL Divider Selection
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </h>
+// </e>
+//
+// <h> CPU Clock Selection Register (CCLKSEL)
+// <o7.0..4> CCLKDIV: CPU clock (CCLK) divider
+// <i> 0: The divider is turned off. No clock will be provided to the CPU
+// <i> n: The input clock is divided by n to produce the CPU clock
+// <0-31>
+// <o7.8> CCLKSEL: CPU clock divider input clock selection
+// <0=> sysclk clock
+// <1=> PLL0 clock
+// </h>
+//
+// <h> USB Clock Selection Register (USBCLKSEL)
+// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
+// <0=> USB clock off
+// <4=> PLL0 / 4 (PLL0 must be 192Mhz)
+// <6=> PLL0 / 6 (PLL0 must be 288Mhz)
+// <o8.8..9> USBSEL: USB clock divider input clock selection
+// <i> When CPU clock is selected, the USB can be accessed
+// <i> by software but cannot perform USB functions
+// <0=> CPU clock
+// <1=> PLL0 clock
+// <2=> PLL1 clock
+// </h>
+//
+// <h> EMC Clock Selection Register (EMCCLKSEL)
+// <o9.0> EMCDIV: EMC clock selection
+// <0=> CPU clock
+// <1=> CPU clock / 2
+// </h>
+//
+// <h> Peripheral Clock Selection Register (PCLKSEL)
+// <o10.0..4> PCLKDIV: APB Peripheral clock divider
+// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
+// <i> n: The input clock is divided by n to produce the APB peripheral clock
+// <0-31>
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.0> PCLCD: LCD controller power/clock enable
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.5> PCPWM0: PWM0 power/clock enable
+// <o11.6> PCPWM1: PWM1 power/clock enable
+// <o11.7> PCI2C0: I2C 0 interface power/clock enable
+// <o11.8> PCUART4: UART 4 power/clock enable
+// <o11.9> PCRTC: RTC and Event Recorder power/clock enable
+// <o11.10> PCSSP1: SSP 1 interface power/clock enable
+// <o11.11> PCEMC: External Memory Controller power/clock enable
+// <o11.12> PCADC: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
+// <o11.17> PCMCPWM: Motor Control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C 1 interface power/clock enable
+// <o11.20> PCSSP2: SSP 2 interface power/clock enable
+// <o11.21> PCSSP0: SSP 0 interface power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C 2 interface power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.28> PCSDC: SD Card interface power/clock enable
+// <o11.29> PCGPDMA: GPDMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
+// <0=> CPU clock
+// <1=> Main Oscillator
+// <2=> Internal RC Oscillator
+// <3=> USB clock
+// <4=> RTC Oscillator
+// <5=> unused
+// <6=> Watchdog Oscillator
+// <o12.4..7> CLKOUTDIV: Output Clock Divider
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable
+// </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000021
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00000009
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKSEL_Val (0x00000001|(1<<8))
+#define USBCLK_SETUP 1
+#define USBCLKSEL_Val (0x00000001|(0x02<<8))
+#define EMCCLKSEL_Val 0x00000001
+#define PCLKSEL_Val 0x00000002
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000100
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00005000
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
+ #error "CCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
+ #error "USBCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
+ #error "EMCCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
+ #error "PCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #warning "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+/* pll_out_clk = F_cco / (2 × P)
+ F_cco = pll_in_clk × M × 2 × P */
+#define __M ((PLL0CFG_Val & 0x1F) + 1)
+#define __PLL0_CLK(__F_IN) (__F_IN * __M)
+#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
+#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
+#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
+
+/* Determine core clock frequency according to settings */
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
+ #error "Main Oscillator is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
+ #error "Main PLL is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
+ #define __EMC_CLK (IRC_OSC/ __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
+ #define __EMC_CLK (OSC_CLK/ __ECLK_DIV)
+ #endif
+ #else /* cclk = pll_clk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
+ #define __EMC_CLK (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
+ #define __EMC_CLK (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
+ #endif
+ #endif
+
+#else
+ #define __CORE_CLK (IRC_OSC)
+ #define __PER_CLK (IRC_OSC)
+ #define __EMC_CLK (IRC_OSC)
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
+uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
+uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
+ be updated after call SystemCoreClockUpdate, should be 48MHz*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ else { /* cclk = pll_clk */
+ if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ }
+ /* ---update USBClock------------------*/
+ if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
+ {
+ switch (LPC_SC->USBCLKSEL & 0x1F)
+ {
+ case 0:
+ USBClock = 0; //no clock will be provided to the USB subsystem
+ break;
+ case 4:
+ case 6:
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+ else //pll_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+ break;
+ default:
+ USBClock = 0; /* this should never happen! */
+ }
+ }
+ else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
+ {
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
+ else //pll1_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
+ }
+ else
+ USBClock = 0; /* this should never happen! */
+}
+
+ /* Determine clock frequency according to clock register values */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+#endif
+
+ LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
+ LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
+ LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
+ LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
+#endif
+#ifdef __RAM_MODE__
+ SCB->VTOR = 0x10000000 & 0x3FFFFF80;
+#else
+ SCB->VTOR = 0x00000000 & 0x3FFFFF80;
+#endif
+}