More work on CMSIS-RTOS documentation including RTX Implementation
diff --git a/CMSIS/RTOS/RTX/INC/RTX_CM_lib.h b/CMSIS/RTOS/RTX/INC/RTX_CM_lib.h
new file mode 100644
index 0000000..d8c4137
--- /dev/null
+++ b/CMSIS/RTOS/RTX/INC/RTX_CM_lib.h
@@ -0,0 +1,571 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RTX_CM_LIB.H
+ * Purpose: RTX Kernel System Configuration
+ * Rev.: V4.81
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#if defined (__CC_ARM)
+#pragma O3
+#define __USED __attribute__((used))
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __USED __attribute__((used))
+#elif defined (__GNUC__)
+#pragma GCC optimize ("O3")
+#define __USED __attribute__((used))
+#elif defined (__ICCARM__)
+#define __USED __root
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * Definitions
+ *---------------------------------------------------------------------------*/
+
+#define _declare_box(pool,size,cnt) uint32_t pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt) uint64_t pool[(((size)+7)/8)*(cnt) + 2]
+
+#define OS_TCB_SIZE 52
+#define OS_TMR_SIZE 8
+
+#if (( defined(__CC_ARM) || \
+ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
+ !defined(__MICROLIB))
+
+typedef void *OS_ID;
+typedef uint32_t OS_TID;
+typedef uint32_t OS_MUT[4];
+typedef uint32_t OS_RESULT;
+
+#define runtask_id() rt_tsk_self()
+#define mutex_init(m) rt_mut_init(m)
+#define mutex_wait(m) os_mut_wait(m,0xFFFFU)
+#define mutex_rel(m) os_mut_release(m)
+
+extern uint8_t os_running;
+extern OS_TID rt_tsk_self (void);
+extern void rt_mut_init (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait (OS_ID mutex, uint16_t timeout);
+
+#if defined(__CC_ARM)
+#define os_mut_wait(mutex,timeout) _os_mut_wait((uint32_t)rt_mut_wait,mutex,timeout)
+#define os_mut_release(mutex) _os_mut_release((uint32_t)rt_mut_release,mutex)
+OS_RESULT _os_mut_release (uint32_t p, OS_ID mutex) __svc_indirect(0);
+OS_RESULT _os_mut_wait (uint32_t p, OS_ID mutex, uint16_t timeout) __svc_indirect(0);
+#else
+__attribute__((always_inline))
+static __inline OS_RESULT os_mut_release (OS_ID mutex) {
+ register uint32_t __r0 __asm("r0") = (uint32_t)mutex;
+ register uint32_t __r1 __asm("r1");
+ register uint32_t __r2 __asm("r2");
+ register uint32_t __r3 __asm("r3");
+ __asm volatile \
+ ( \
+ "ldr r12,=rt_mut_release\n" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r12", "lr", "cc" \
+ );
+ return (OS_RESULT)__r0;
+}
+__attribute__((always_inline))
+static __inline OS_RESULT os_mut_wait (OS_ID mutex, uint16_t timeout) {
+ register uint32_t __r0 __asm("r0") = (uint32_t)mutex;
+ register uint32_t __r1 __asm("r1") = (uint32_t)timeout;
+ register uint32_t __r2 __asm("r2");
+ register uint32_t __r3 __asm("r3");
+ __asm volatile \
+ ( \
+ "ldr r12,=rt_mut_wait\n" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r12", "lr", "cc" \
+ );
+ return (OS_RESULT)__r0;
+}
+#endif
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+#if (OS_TASKCNT == 0)
+#error "Invalid number of concurrent running threads!"
+#endif
+
+#if (OS_PRIVCNT >= OS_TASKCNT)
+#error "Too many threads with user-provided stack size!"
+#endif
+
+#if (OS_TIMERS != 0)
+#define OS_TASK_CNT (OS_TASKCNT + 1)
+#define OS_PRIV_CNT (OS_PRIVCNT + 2)
+#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE+OS_TIMERSTKSZ))
+#else
+#define OS_TASK_CNT OS_TASKCNT
+#define OS_PRIV_CNT (OS_PRIVCNT + 1)
+#define OS_STACK_SZ (4*(OS_PRIVSTKSIZE+OS_MAINSTKSIZE))
+#endif
+
+#ifndef OS_STKINIT
+#define OS_STKINIT 0
+#endif
+
+extern uint16_t const os_maxtaskrun;
+extern uint32_t const os_stackinfo;
+extern uint32_t const os_rrobin;
+extern uint32_t const os_trv;
+extern uint8_t const os_flags;
+
+uint16_t const os_maxtaskrun = OS_TASK_CNT;
+uint32_t const os_stackinfo = (OS_STKINIT<<28) | (OS_STKCHECK<<24) | (OS_PRIV_CNT<<16) | (OS_STKSIZE*4);
+uint32_t const os_rrobin = (OS_ROBIN << 16) | OS_ROBINTOUT;
+uint32_t const os_tickfreq = OS_CLOCK;
+uint16_t const os_tickus_i = OS_CLOCK/1000000;
+uint16_t const os_tickus_f = (((uint64_t)(OS_CLOCK-1000000*(OS_CLOCK/1000000)))<<16)/1000000;
+uint32_t const os_trv = OS_TRV;
+uint8_t const os_flags = OS_RUNPRIV;
+
+/* Export following defines to uVision debugger. */
+extern uint32_t const CMSIS_RTOS_API_Version;
+__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
+extern uint32_t const CMSIS_RTOS_RTX_Version;
+__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
+extern uint32_t const os_clockrate;
+__USED uint32_t const os_clockrate = OS_TICK;
+extern uint32_t const os_timernum;
+__USED uint32_t const os_timernum = 0U;
+
+/* Memory pool for TCB allocation */
+extern
+uint32_t mp_tcb[];
+_declare_box (mp_tcb, OS_TCB_SIZE, OS_TASK_CNT);
+extern
+uint16_t const mp_tcb_size;
+uint16_t const mp_tcb_size = sizeof(mp_tcb);
+
+/* Memory pool for System stack allocation (+os_idle_demon). */
+extern
+uint64_t mp_stk[];
+_declare_box8 (mp_stk, OS_STKSIZE*4, OS_TASK_CNT-OS_PRIV_CNT+1);
+extern
+uint32_t const mp_stk_size;
+uint32_t const mp_stk_size = sizeof(mp_stk);
+
+/* Memory pool for user specified stack allocation (+main, +timer) */
+extern
+uint64_t os_stack_mem[];
+uint64_t os_stack_mem[2+OS_PRIV_CNT+(OS_STACK_SZ/8)];
+extern
+uint32_t const os_stack_sz;
+uint32_t const os_stack_sz = sizeof(os_stack_mem);
+
+#ifndef OS_FIFOSZ
+#define OS_FIFOSZ 16
+#endif
+
+/* Fifo Queue buffer for ISR requests.*/
+extern
+uint32_t os_fifo[];
+uint32_t os_fifo[OS_FIFOSZ*2+1];
+extern
+uint8_t const os_fifo_size;
+uint8_t const os_fifo_size = OS_FIFOSZ;
+
+/* An array of Active task pointers. */
+extern
+void *os_active_TCB[];
+void *os_active_TCB[OS_TASK_CNT];
+
+/* User Timers Resources */
+#if (OS_TIMERS != 0)
+extern void osTimerThread (void const *argument);
+extern const osThreadDef_t os_thread_def_osTimerThread;
+osThreadDef(osTimerThread, (osPriority)(OS_TIMERPRIO-3), 1, 4*OS_TIMERSTKSZ);
+extern
+osThreadId osThreadId_osTimerThread;
+osThreadId osThreadId_osTimerThread;
+extern uint32_t os_messageQ_q_osTimerMessageQ[];
+extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;
+osMessageQDef(osTimerMessageQ, OS_TIMERCBQS, void *);
+extern
+osMessageQId osMessageQId_osTimerMessageQ;
+osMessageQId osMessageQId_osTimerMessageQ;
+#else
+extern
+const osThreadDef_t os_thread_def_osTimerThread;
+const osThreadDef_t os_thread_def_osTimerThread = { NULL, osPriorityNormal, 0U, 0U };
+extern
+osThreadId osThreadId_osTimerThread;
+osThreadId osThreadId_osTimerThread;
+extern uint32_t os_messageQ_q_osTimerMessageQ[];
+extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;
+osMessageQDef(osTimerMessageQ, 0U, void *);
+extern
+osMessageQId osMessageQId_osTimerMessageQ;
+osMessageQId osMessageQId_osTimerMessageQ;
+#endif
+
+/* Legacy RTX User Timers not used */
+extern
+uint32_t os_tmr;
+uint32_t os_tmr = 0U;
+extern
+uint32_t const *m_tmr;
+uint32_t const *m_tmr = NULL;
+extern
+uint16_t const mp_tmr_size;
+uint16_t const mp_tmr_size = 0U;
+
+#if (( defined(__CC_ARM) || \
+ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
+ !defined(__MICROLIB))
+/* A memory space for arm standard library. */
+static uint32_t std_libspace[OS_TASK_CNT][96/4];
+static OS_MUT std_libmutex[OS_MUTEXCNT];
+static uint32_t nr_mutex;
+extern void *__libspace_start;
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * RTX Optimizations (empty functions)
+ *---------------------------------------------------------------------------*/
+
+#if OS_ROBIN == 0
+extern
+void rt_init_robin (void);
+void rt_init_robin (void) {;}
+extern
+void rt_chk_robin (void);
+void rt_chk_robin (void) {;}
+#endif
+
+#if OS_STKCHECK == 0
+extern
+void rt_stk_check (void);
+void rt_stk_check (void) {;}
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * Standard Library multithreading interface
+ *---------------------------------------------------------------------------*/
+
+#if (( defined(__CC_ARM) || \
+ (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))) && \
+ !defined(__MICROLIB))
+
+/*--------------------------- __user_perthread_libspace ---------------------*/
+
+void *__user_perthread_libspace (void);
+void *__user_perthread_libspace (void) {
+ /* Provide a separate libspace for each task. */
+ uint32_t idx;
+
+ idx = (os_running != 0U) ? runtask_id () : 0U;
+ if (idx == 0U) {
+ /* RTX not running yet. */
+ return (&__libspace_start);
+ }
+ return ((void *)&std_libspace[idx-1]);
+}
+
+/*--------------------------- _mutex_initialize -----------------------------*/
+
+int _mutex_initialize (OS_ID *mutex);
+int _mutex_initialize (OS_ID *mutex) {
+ /* Allocate and initialize a system mutex. */
+
+ if (nr_mutex >= OS_MUTEXCNT) {
+ /* If you are here, you need to increase the number OS_MUTEXCNT. */
+ for (;;);
+ }
+ *mutex = &std_libmutex[nr_mutex++];
+ mutex_init (*mutex);
+ return (1);
+}
+
+
+/*--------------------------- _mutex_acquire --------------------------------*/
+
+__attribute__((used))
+void _mutex_acquire (OS_ID *mutex);
+void _mutex_acquire (OS_ID *mutex) {
+ /* Acquire a system mutex, lock stdlib resources. */
+ if (os_running) {
+ /* RTX running, acquire a mutex. */
+ mutex_wait (*mutex);
+ }
+}
+
+
+/*--------------------------- _mutex_release --------------------------------*/
+
+__attribute__((used))
+void _mutex_release (OS_ID *mutex);
+void _mutex_release (OS_ID *mutex) {
+ /* Release a system mutex, unlock stdlib resources. */
+ if (os_running) {
+ /* RTX running, release a mutex. */
+ mutex_rel (*mutex);
+ }
+}
+
+#endif
+
+
+/*----------------------------------------------------------------------------
+ * ARMCC6 Wrappers for ARMCC5 Binary
+ *---------------------------------------------------------------------------*/
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+typedef uint32_t __attribute__((vector_size(8))) vect64_t;
+
+#undef osSignalWait
+
+__attribute__((pcs("aapcs")))
+vect64_t osSignalWait (int32_t signals, uint32_t millisec);
+
+osEvent __osSignalWait (int32_t signals, uint32_t millisec) {
+ vect64_t v;
+ osEvent e;
+
+ v = osSignalWait(signals, millisec);
+ e.status = v[0];
+ e.value.v = v[1];
+
+ return e;
+}
+
+#undef osMessageGet
+
+__attribute__((pcs("aapcs")))
+vect64_t osMessageGet (osMessageQId queue_id, uint32_t millisec);
+
+osEvent __osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+ vect64_t v;
+ osEvent e;
+
+ v = osMessageGet(queue_id, millisec);
+ e.status = v[0];
+ e.value.v = v[1];
+
+ return e;
+}
+
+#undef osMailGet
+
+__attribute__((pcs("aapcs")))
+vect64_t osMailGet (osMailQId queue_id, uint32_t millisec);
+
+osEvent __osMailGet (osMailQId queue_id, uint32_t millisec) {
+ vect64_t v;
+ osEvent e;
+
+ v = osMailGet(queue_id, millisec);
+ e.status = v[0];
+ e.value.v = v[1];
+
+ return e;
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * RTX Startup
+ *---------------------------------------------------------------------------*/
+
+/* Main Thread definition */
+extern int main (void);
+extern
+const osThreadDef_t os_thread_def_main;
+const osThreadDef_t os_thread_def_main = {(os_pthread)main, osPriorityNormal, 1U, 4*OS_MAINSTKSIZE };
+
+
+#if defined (__CC_ARM)
+
+#ifdef __MICROLIB
+__attribute__((section(".ARM.Collect$$$$000000FF")))
+void _main_init (void);
+void _main_init (void) {
+ osKernelInitialize();
+ osThreadCreate(&os_thread_def_main, NULL);
+ osKernelStart();
+ for (;;);
+}
+#else
+__asm void _platform_post_lib_init (void) {
+
+ IMPORT os_thread_def_main
+ IMPORT osKernelInitialize
+ IMPORT osKernelStart
+ IMPORT osThreadCreate
+ IMPORT exit
+
+ ADD SP,#0x10
+ BL osKernelInitialize
+ LDR R0,=os_thread_def_main
+ MOVS R1,#0
+ BL osThreadCreate
+ BL osKernelStart
+ BL exit
+
+ ALIGN
+}
+#endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+
+#ifdef __MICROLIB
+__attribute__((noreturn, section(".ARM.Collect$$$$000000FF")))
+void _main_init (void);
+void _main_init (void) {
+#else
+__asm(" .global __ARM_use_no_argv\n");
+__attribute__((noreturn))
+void _platform_post_lib_init (void);
+void _platform_post_lib_init (void) {
+#endif
+ osKernelInitialize();
+ osThreadCreate(&os_thread_def_main, NULL);
+ osKernelStart();
+ for (;;);
+}
+
+#elif defined (__GNUC__)
+
+#ifdef __CS3__
+
+/* CS3 start_c routine.
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include "cs3.h"
+
+extern void __libc_init_array (void);
+
+__attribute ((noreturn)) void __cs3_start_c (void){
+ unsigned regions = __cs3_region_num;
+ const struct __cs3_region *rptr = __cs3_regions;
+
+ /* Initialize memory */
+ for (regions = __cs3_region_num, rptr = __cs3_regions; regions--; rptr++) {
+ long long *src = (long long *)rptr->init;
+ long long *dst = (long long *)rptr->data;
+ unsigned limit = rptr->init_size;
+ unsigned count;
+
+ if (src != dst)
+ for (count = 0; count != limit; count += sizeof (long long))
+ *dst++ = *src++;
+ else
+ dst = (long long *)((char *)dst + limit);
+ limit = rptr->zero_size;
+ for (count = 0; count != limit; count += sizeof (long long))
+ *dst++ = 0;
+ }
+
+ /* Run initializers. */
+ __libc_init_array ();
+
+ osKernelInitialize();
+ osThreadCreate(&os_thread_def_main, NULL);
+ osKernelStart();
+ for (;;);
+}
+
+#else
+
+__attribute__((naked)) void software_init_hook (void) {
+ __asm (
+ ".syntax unified\n"
+ ".thumb\n"
+ "movs r0,#0\n"
+ "movs r1,#0\n"
+ "mov r4,r0\n"
+ "mov r5,r1\n"
+ "ldr r0,= __libc_fini_array\n"
+ "bl atexit\n"
+ "bl __libc_init_array\n"
+ "mov r0,r4\n"
+ "mov r1,r5\n"
+ "bl osKernelInitialize\n"
+ "ldr r0,=os_thread_def_main\n"
+ "movs r1,#0\n"
+ "bl osThreadCreate\n"
+ "bl osKernelStart\n"
+ "bl exit\n"
+ );
+}
+
+#endif
+
+#elif defined (__ICCARM__)
+
+extern int __low_level_init(void);
+extern void __iar_data_init3(void);
+extern void exit(int arg);
+
+__noreturn __stackless void __cmain(void) {
+ int a;
+
+ if (__low_level_init() != 0) {
+ __iar_data_init3();
+ }
+ osKernelInitialize();
+ osThreadCreate(&os_thread_def_main, NULL);
+ a = osKernelStart();
+ exit(a);
+}
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/INC/cmsis_os.h b/CMSIS/RTOS/RTX/INC/cmsis_os.h
new file mode 100644
index 0000000..efb1b99
--- /dev/null
+++ b/CMSIS/RTOS/RTX/INC/cmsis_os.h
@@ -0,0 +1,686 @@
+/* ----------------------------------------------------------------------
+ * $Date: 5. February 2013
+ * $Revision: V1.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: cmsis_os.h RTX header file
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * Version 0.03
+ * osKernelStart added, optional feature: main started as thread
+ * osSemaphores have standard behavior
+ * osTimerCreate does not start the timer, added osTimerStart
+ * osThreadPass is renamed to osThreadYield
+ * Version 1.01
+ * Support for C++ interface
+ * - const attribute removed from the osXxxxDef_t typedef's
+ * - const attribute added to the osXxxxDef macros
+ * Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+ * Added: osKernelInitialize
+ * Version 1.02
+ * Control functions for short timeouts in microsecond resolution:
+ * Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
+ * Removed: osSignalGet
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 2013 ARM LIMITED
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+
+#ifndef _CMSIS_OS_H
+#define _CMSIS_OS_H
+
+#define osCMSIS 0x10002U ///< CMSIS-RTOS API version (main [31:16] .sub [15:0])
+
+#define osCMSIS_RTX ((4<<16)|81) ///< RTOS identification and version (main [31:16] .sub [15:0])
+
+#define osKernelSystemId "RTX V4.81" ///< RTOS identification string
+
+
+#define osFeature_MainThread 1 ///< main can be thread
+#define osFeature_Pool 1 ///< Memory Pools available
+#define osFeature_MailQ 1 ///< Mail Queues available
+#define osFeature_MessageQ 1 ///< Message Queues available
+#define osFeature_Signals 16 ///< 16 Signal Flags available per thread
+#define osFeature_Semaphore 65535 ///< Maximum count for \ref osSemaphoreCreate function
+#define osFeature_Wait 0 ///< osWait not available
+#define osFeature_SysTick 1 ///< osKernelSysTick functions available
+
+#if defined(__CC_ARM)
+#define os_InRegs __value_in_regs // Compiler specific: force struct in registers
+#else
+#define os_InRegs
+#endif
+
+#if defined(__CC_ARM)
+#define __NO_RETURN __declspec(noreturn)
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define __NO_RETURN __attribute__((noreturn))
+#elif defined(__GNUC__)
+#define __NO_RETURN __attribute__((noreturn))
+#elif defined(__ICCARM__)
+#define __NO_RETURN __noreturn
+#else
+#define __NO_RETURN
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+/// Priority used for thread control.
+typedef enum {
+ osPriorityIdle = -3, ///< priority: idle (lowest)
+ osPriorityLow = -2, ///< priority: low
+ osPriorityBelowNormal = -1, ///< priority: below normal
+ osPriorityNormal = 0, ///< priority: normal (default)
+ osPriorityAboveNormal = +1, ///< priority: above normal
+ osPriorityHigh = +2, ///< priority: high
+ osPriorityRealtime = +3, ///< priority: realtime (highest)
+ osPriorityError = 0x84, ///< system cannot determine priority or thread has illegal priority
+ os_priority_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
+} osPriority;
+
+/// Timeout value.
+#define osWaitForever 0xFFFFFFFFU ///< wait forever timeout value
+
+/// Status code values returned by CMSIS-RTOS functions.
+typedef enum {
+ osOK = 0, ///< function completed; no error or event occurred.
+ osEventSignal = 0x08, ///< function completed; signal event occurred.
+ osEventMessage = 0x10, ///< function completed; message event occurred.
+ osEventMail = 0x20, ///< function completed; mail event occurred.
+ osEventTimeout = 0x40, ///< function completed; timeout occurred.
+ osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
+ osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
+ osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
+ osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
+ osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
+ osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
+ osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
+ osErrorValue = 0x86, ///< value of a parameter is out of range.
+ osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
+ os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
+} osStatus;
+
+
+/// Timer type value for the timer definition.
+typedef enum {
+ osTimerOnce = 0, ///< one-shot timer
+ osTimerPeriodic = 1 ///< repeating timer
+} os_timer_type;
+
+/// Entry point of a thread.
+typedef void (*os_pthread) (void const *argument);
+
+/// Entry point of a timer call back function.
+typedef void (*os_ptimer) (void const *argument);
+
+// >>> the following data type definitions may shall adapted towards a specific RTOS
+
+/// Thread ID identifies the thread (pointer to a thread control block).
+typedef struct os_thread_cb *osThreadId;
+
+/// Timer ID identifies the timer (pointer to a timer control block).
+typedef struct os_timer_cb *osTimerId;
+
+/// Mutex ID identifies the mutex (pointer to a mutex control block).
+typedef struct os_mutex_cb *osMutexId;
+
+/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
+typedef struct os_semaphore_cb *osSemaphoreId;
+
+/// Pool ID identifies the memory pool (pointer to a memory pool control block).
+typedef struct os_pool_cb *osPoolId;
+
+/// Message ID identifies the message queue (pointer to a message queue control block).
+typedef struct os_messageQ_cb *osMessageQId;
+
+/// Mail ID identifies the mail queue (pointer to a mail queue control block).
+typedef struct os_mailQ_cb *osMailQId;
+
+
+/// Thread Definition structure contains startup information of a thread.
+typedef struct os_thread_def {
+ os_pthread pthread; ///< start address of thread function
+ osPriority tpriority; ///< initial thread priority
+ uint32_t instances; ///< maximum number of instances of that thread function
+ uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
+} osThreadDef_t;
+
+/// Timer Definition structure contains timer parameters.
+typedef struct os_timer_def {
+ os_ptimer ptimer; ///< start address of a timer function
+ void *timer; ///< pointer to internal data
+} osTimerDef_t;
+
+/// Mutex Definition structure contains setup information for a mutex.
+typedef struct os_mutex_def {
+ void *mutex; ///< pointer to internal data
+} osMutexDef_t;
+
+/// Semaphore Definition structure contains setup information for a semaphore.
+typedef struct os_semaphore_def {
+ void *semaphore; ///< pointer to internal data
+} osSemaphoreDef_t;
+
+/// Definition structure for memory block allocation.
+typedef struct os_pool_def {
+ uint32_t pool_sz; ///< number of items (elements) in the pool
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< pointer to memory for pool
+} osPoolDef_t;
+
+/// Definition structure for message queue.
+typedef struct os_messageQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ void *pool; ///< memory array for messages
+} osMessageQDef_t;
+
+/// Definition structure for mail queue.
+typedef struct os_mailQ_def {
+ uint32_t queue_sz; ///< number of elements in the queue
+ uint32_t item_sz; ///< size of an item
+ void *pool; ///< memory array for mail
+} osMailQDef_t;
+
+/// Event structure contains detailed information about an event.
+typedef struct {
+ osStatus status; ///< status code: event or error information
+ union {
+ uint32_t v; ///< message as 32-bit value
+ void *p; ///< message or mail as void pointer
+ int32_t signals; ///< signal flags
+ } value; ///< event value
+ union {
+ osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
+ osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
+ } def; ///< event definition
+} osEvent;
+
+
+// ==== Kernel Control Functions ====
+
+/// Initialize the RTOS Kernel for creating objects.
+/// \return status code that indicates the execution status of the function.
+osStatus osKernelInitialize (void);
+
+/// Start the RTOS Kernel.
+/// \return status code that indicates the execution status of the function.
+osStatus osKernelStart (void);
+
+/// Check if the RTOS kernel is already started.
+/// \return 0 RTOS is not started, 1 RTOS is started.
+int32_t osKernelRunning(void);
+
+#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
+
+/// \cond INTERNAL_VARIABLES
+extern uint32_t const os_tickfreq;
+extern uint16_t const os_tickus_i;
+extern uint16_t const os_tickus_f;
+/// \endcond
+
+/// Get the RTOS kernel system timer counter.
+/// \return RTOS kernel system timer as 32-bit value
+uint32_t osKernelSysTick (void);
+
+/// The RTOS kernel system timer frequency in Hz.
+/// \note Reflects the system timer setting and is typically defined in a configuration file.
+#define osKernelSysTickFrequency os_tickfreq
+
+/// Convert a microseconds value to a RTOS kernel system timer value.
+/// \param microsec time value in microseconds.
+/// \return time value normalized to the \ref osKernelSysTickFrequency
+/*
+#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
+*/
+#define osKernelSysTickMicroSec(microsec) ((microsec * os_tickus_i) + ((microsec * os_tickus_f) >> 16))
+
+#endif // System Timer available
+
+// ==== Thread Management ====
+
+/// Create a Thread Definition with function, priority, and stack requirements.
+/// \param name name of the thread function.
+/// \param priority initial priority of the thread function.
+/// \param instances number of possible thread instances.
+/// \param stacksz stack size (in bytes) requirements for the thread function.
+/// macro body is implementation specific in every CMSIS-RTOS.
+#if defined (osObjectsExternal) // object is external
+#define osThreadDef(name, priority, instances, stacksz) \
+extern const osThreadDef_t os_thread_def_##name
+#else // define the object
+#define osThreadDef(name, priority, instances, stacksz) \
+const osThreadDef_t os_thread_def_##name = \
+{ (name), (priority), (instances), (stacksz) }
+#endif
+
+/// Access a Thread definition.
+/// \param name name of the thread definition object.
+/// macro body is implementation specific in every CMSIS-RTOS.
+#define osThread(name) \
+&os_thread_def_##name
+
+/// Create a thread and add it to Active Threads and set it to state READY.
+/// \param[in] thread_def thread definition referenced with \ref osThread.
+/// \param[in] argument pointer that is passed to the thread function as start argument.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
+
+/// Return the thread ID of the current running thread.
+/// \return thread ID for reference by other functions or NULL in case of error.
+osThreadId osThreadGetId (void);
+
+/// Terminate execution of a thread and remove it from Active Threads.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return status code that indicates the execution status of the function.
+osStatus osThreadTerminate (osThreadId thread_id);
+
+/// Pass control to next thread that is in state \b READY.
+/// \return status code that indicates the execution status of the function.
+osStatus osThreadYield (void);
+
+/// Change priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] priority new priority value for the thread function.
+/// \return status code that indicates the execution status of the function.
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
+
+/// Get current priority of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \return current priority value of the thread function.
+osPriority osThreadGetPriority (osThreadId thread_id);
+
+
+// ==== Generic Wait Functions ====
+
+/// Wait for Timeout (Time Delay).
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value
+/// \return status code that indicates the execution status of the function.
+osStatus osDelay (uint32_t millisec);
+
+#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
+
+/// Wait for Signal, Message, Mail, or Timeout.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains signal, message, or mail information or error code.
+os_InRegs osEvent osWait (uint32_t millisec);
+
+#endif // Generic Wait available
+
+
+// ==== Timer Management Functions ====
+/// Define a Timer object.
+/// \param name name of the timer object.
+/// \param function name of the timer call back function.
+#if defined (osObjectsExternal) // object is external
+#define osTimerDef(name, function) \
+extern const osTimerDef_t os_timer_def_##name
+#else // define the object
+#define osTimerDef(name, function) \
+uint32_t os_timer_cb_##name[6]; \
+const osTimerDef_t os_timer_def_##name = \
+{ (function), (os_timer_cb_##name) }
+#endif
+
+/// Access a Timer definition.
+/// \param name name of the timer object.
+#define osTimer(name) \
+&os_timer_def_##name
+
+/// Create a timer.
+/// \param[in] timer_def timer object referenced with \ref osTimer.
+/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
+/// \param[in] argument argument to the timer call back function.
+/// \return timer ID for reference by other functions or NULL in case of error.
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
+
+/// Start or restart a timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue "Time delay" value of the timer.
+/// \return status code that indicates the execution status of the function.
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
+
+/// Stop the timer.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osTimerStop (osTimerId timer_id);
+
+/// Delete a timer that was created by \ref osTimerCreate.
+/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osTimerDelete (osTimerId timer_id);
+
+
+// ==== Signal Management ====
+
+/// Set the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that should be set.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+int32_t osSignalSet (osThreadId thread_id, int32_t signals);
+
+/// Clear the specified Signal Flags of an active thread.
+/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
+/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
+/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters or call from ISR.
+int32_t osSignalClear (osThreadId thread_id, int32_t signals);
+
+/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
+/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event flag information or error code.
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define osSignalWait __osSignalWait
+osEvent __osSignalWait (int32_t signals, uint32_t millisec);
+#else
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec);
+#endif
+
+
+// ==== Mutex Management ====
+
+/// Define a Mutex.
+/// \param name name of the mutex object.
+#if defined (osObjectsExternal) // object is external
+#define osMutexDef(name) \
+extern const osMutexDef_t os_mutex_def_##name
+#else // define the object
+#define osMutexDef(name) \
+uint32_t os_mutex_cb_##name[4] = { 0 }; \
+const osMutexDef_t os_mutex_def_##name = { (os_mutex_cb_##name) }
+#endif
+
+/// Access a Mutex definition.
+/// \param name name of the mutex object.
+#define osMutex(name) \
+&os_mutex_def_##name
+
+/// Create and Initialize a Mutex object.
+/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
+/// \return mutex ID for reference by other functions or NULL in case of error.
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
+
+/// Wait until a Mutex becomes available.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
+
+/// Release a Mutex that was obtained by \ref osMutexWait.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osMutexRelease (osMutexId mutex_id);
+
+/// Delete a Mutex that was created by \ref osMutexCreate.
+/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osMutexDelete (osMutexId mutex_id);
+
+
+// ==== Semaphore Management Functions ====
+
+#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
+
+/// Define a Semaphore object.
+/// \param name name of the semaphore object.
+#if defined (osObjectsExternal) // object is external
+#define osSemaphoreDef(name) \
+extern const osSemaphoreDef_t os_semaphore_def_##name
+#else // define the object
+#define osSemaphoreDef(name) \
+uint32_t os_semaphore_cb_##name[2] = { 0 }; \
+const osSemaphoreDef_t os_semaphore_def_##name = { (os_semaphore_cb_##name) }
+#endif
+
+/// Access a Semaphore definition.
+/// \param name name of the semaphore object.
+#define osSemaphore(name) \
+&os_semaphore_def_##name
+
+/// Create and Initialize a Semaphore object used for managing resources.
+/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
+/// \param[in] count number of available resources.
+/// \return semaphore ID for reference by other functions or NULL in case of error.
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
+
+/// Wait until a Semaphore token becomes available.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return number of available tokens, or -1 in case of incorrect parameters.
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
+
+/// Release a Semaphore token.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
+
+/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
+/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
+/// \return status code that indicates the execution status of the function.
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
+
+#endif // Semaphore available
+
+
+// ==== Memory Pool Management Functions ====
+
+#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
+
+/// \brief Define a Memory Pool.
+/// \param name name of the memory pool.
+/// \param no maximum number of blocks (objects) in the memory pool.
+/// \param type data type of a single block (object).
+#if defined (osObjectsExternal) // object is external
+#define osPoolDef(name, no, type) \
+extern const osPoolDef_t os_pool_def_##name
+#else // define the object
+#define osPoolDef(name, no, type) \
+uint32_t os_pool_m_##name[3+((sizeof(type)+3)/4)*(no)]; \
+const osPoolDef_t os_pool_def_##name = \
+{ (no), sizeof(type), (os_pool_m_##name) }
+#endif
+
+/// \brief Access a Memory Pool definition.
+/// \param name name of the memory pool
+#define osPool(name) \
+&os_pool_def_##name
+
+/// Create and Initialize a memory pool.
+/// \param[in] pool_def memory pool definition referenced with \ref osPool.
+/// \return memory pool ID for reference by other functions or NULL in case of error.
+osPoolId osPoolCreate (const osPoolDef_t *pool_def);
+
+/// Allocate a memory block from a memory pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolAlloc (osPoolId pool_id);
+
+/// Allocate a memory block from a memory pool and set memory block to zero.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \return address of the allocated memory block or NULL in case of no memory available.
+void *osPoolCAlloc (osPoolId pool_id);
+
+/// Return an allocated memory block back to a specific memory pool.
+/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
+/// \param[in] block address of the allocated memory block that is returned to the memory pool.
+/// \return status code that indicates the execution status of the function.
+osStatus osPoolFree (osPoolId pool_id, void *block);
+
+#endif // Memory Pool Management available
+
+
+// ==== Message Queue Management Functions ====
+
+#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
+
+/// \brief Create a Message Queue Definition.
+/// \param name name of the queue.
+/// \param queue_sz maximum number of messages in the queue.
+/// \param type data type of a single message element (for debugger).
+#if defined (osObjectsExternal) // object is external
+#define osMessageQDef(name, queue_sz, type) \
+extern const osMessageQDef_t os_messageQ_def_##name
+#else // define the object
+#define osMessageQDef(name, queue_sz, type) \
+uint32_t os_messageQ_q_##name[4+(queue_sz)] = { 0 }; \
+const osMessageQDef_t os_messageQ_def_##name = \
+{ (queue_sz), (os_messageQ_q_##name) }
+#endif
+
+/// \brief Access a Message Queue Definition.
+/// \param name name of the queue
+#define osMessageQ(name) \
+&os_messageQ_def_##name
+
+/// Create and Initialize a Message Queue.
+/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return message queue ID for reference by other functions or NULL in case of error.
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+/// Put a Message to a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] info message information.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return status code that indicates the execution status of the function.
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Get a Message or Wait for a Message from a Queue.
+/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out.
+/// \return event information that includes status code.
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define osMessageGet __osMessageGet
+osEvent __osMessageGet (osMessageQId queue_id, uint32_t millisec);
+#else
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
+#endif
+
+#endif // Message Queues available
+
+
+// ==== Mail Queue Management Functions ====
+
+#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
+
+/// \brief Create a Mail Queue Definition.
+/// \param name name of the queue
+/// \param queue_sz maximum number of messages in queue
+/// \param type data type of a single message element
+#if defined (osObjectsExternal) // object is external
+#define osMailQDef(name, queue_sz, type) \
+extern const osMailQDef_t os_mailQ_def_##name
+#else // define the object
+#define osMailQDef(name, queue_sz, type) \
+uint32_t os_mailQ_q_##name[4+(queue_sz)] = { 0 }; \
+uint32_t os_mailQ_m_##name[3+((sizeof(type)+3)/4)*(queue_sz)]; \
+void * os_mailQ_p_##name[2] = { (os_mailQ_q_##name), os_mailQ_m_##name }; \
+const osMailQDef_t os_mailQ_def_##name = \
+{ (queue_sz), sizeof(type), (os_mailQ_p_##name) }
+#endif
+
+/// \brief Access a Mail Queue Definition.
+/// \param name name of the queue
+#define osMailQ(name) \
+&os_mailQ_def_##name
+
+/// Create and Initialize mail queue.
+/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
+/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
+/// \return mail queue ID for reference by other functions or NULL in case of error.
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
+
+/// Allocate a memory block from a mail.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Allocate a memory block from a mail and set memory block to zero.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return pointer to memory block that can be filled with mail or NULL in case of error.
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
+
+/// Put a mail to a queue.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailPut (osMailQId queue_id, void *mail);
+
+/// Get a mail from a queue.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] millisec \ref CMSIS_RTOS_TimeOutValue or 0 in case of no time-out
+/// \return event that contains mail information or error code.
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#define osMailGet __osMailGet
+osEvent __osMailGet (osMailQId queue_id, uint32_t millisec);
+#else
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
+#endif
+
+/// Free a memory block from a mail.
+/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
+/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
+/// \return status code that indicates the execution status of the function.
+osStatus osMailFree (osMailQId queue_id, void *mail);
+
+#endif // Mail Queues available
+
+
+// ==== RTX Extensions ====
+
+/// Suspend the RTX task scheduler.
+/// \return number of ticks, for how long the system can sleep or power-down.
+uint32_t os_suspend (void);
+
+/// Resume the RTX task scheduler.
+/// \param[in] sleep_time specifies how long the system was in sleep or power-down mode.
+void os_resume (uint32_t sleep_time);
+
+/// OS idle demon (running when no other thread is ready to run).
+__NO_RETURN void os_idle_demon (void);
+
+/// OS error callback (called when a runtime error is detected).
+/// \param[in] error_code actual error code that has been detected.
+__NO_RETURN void os_error (uint32_t error_code);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _CMSIS_OS_H
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib
new file mode 100644
index 0000000..e7d4aef
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib
new file mode 100644
index 0000000..958995d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM0_B.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib
new file mode 100644
index 0000000..1710f1d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib
new file mode 100644
index 0000000..95809c0
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_B.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib
new file mode 100644
index 0000000..1d33b4b
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM3_IFX.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib
new file mode 100644
index 0000000..c1474ac
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib
new file mode 100644
index 0000000..0490df0
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_B.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib
new file mode 100644
index 0000000..e5d3401
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/ARM/RTX_CM4_IFX.lib
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a
new file mode 100644
index 0000000..a4ee01a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a
new file mode 100644
index 0000000..f321938
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM0_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a
new file mode 100644
index 0000000..4c100a4
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a
new file mode 100644
index 0000000..08e1464
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a
new file mode 100644
index 0000000..cbef3f9
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM3_IFX.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a
new file mode 100644
index 0000000..fa32787
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a
new file mode 100644
index 0000000..ded5cce
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a
new file mode 100644
index 0000000..9e41fc9
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/GCC/libRTX_CM4_IFX.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a
new file mode 100644
index 0000000..afe42df
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a
new file mode 100644
index 0000000..842dfc1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM0_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a
new file mode 100644
index 0000000..838db32
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a
new file mode 100644
index 0000000..d4c2986
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM3_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a
new file mode 100644
index 0000000..8094c63
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a
new file mode 100644
index 0000000..a7841cd
--- /dev/null
+++ b/CMSIS/RTOS/RTX/LIB/IAR/RTX_CM4_B.a
Binary files differ
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM0.c b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM0.c
new file mode 100644
index 0000000..e033640
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM0.c
@@ -0,0 +1,300 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM0.C
+ * Purpose: Hardware Abstraction Layer for Cortex-M0
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ BNE PrivilegedE
+ MOVS R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+PrivilegedE
+ MOVS R0,#0x02 ; Privileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R3,=__cpp(rt_alloc_box)
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedA
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedA
+ SVC 0
+ BX LR
+PrivilegedA
+ BX R12
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm U32 _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R3,=__cpp(rt_free_box)
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedF
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedF
+ SVC 0
+ BX LR
+PrivilegedF
+ BX R12
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ SUBS R1,R1,#2 ; Point to SVC Instruction
+ LDRB R1,[R1] ; Load SVC Number
+ CMP R1,#0
+ BNE SVC_User ; User SVC Number > 0
+
+ MOV LR,R4
+ LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
+ MOV R12,R4
+ MOV R4,LR
+ BLX R12 ; Call SVC Function
+
+ MRS R3,PSP ; Read PSP
+ STMIA R3!,{R0-R2} ; Store return values
+
+ LDR R3,=__cpp(&os_tsk)
+ LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ SVC_Exit ; no task switch
+
+ SUBS R3,#8
+ CMP R1,#0 ; Runtask deleted?
+ BEQ SVC_Next
+
+ MRS R0,PSP ; Read PSP
+ SUBS R0,R0,#32 ; Adjust Start Address
+ STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ STMIA R0!,{R4-R7} ; Save old context (R4-R7)
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} ; Save old context (R8-R11)
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_Next
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ ADDS R0,R0,#16 ; Adjust Start Address
+ LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 ; Write PSP
+ SUBS R0,R0,#32 ; Adjust Start Address
+ LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
+
+SVC_Exit
+ MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
+ MVNS R0,R0
+ BX R0 ; RETI to Thread Mode, use PSP
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LSLS R1,R1,#2
+ LDR R4,[R4,R1] ; Load SVC Function Address
+ MOV LR,R4
+
+ LDMIA R0,{R0-R3,R4} ; Read R0-R3,R12 from stack
+ MOV R12,R4
+ BLX LR ; Call SVC Function
+
+ MRS R4,PSP ; Read PSP
+ STMIA R4!,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ LDR R3,=__cpp(&os_tsk)
+ LDMIA R3!,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ Sys_Exit ; no task switch
+
+ SUBS R3,#8
+
+ MRS R0,PSP ; Read PSP
+ SUBS R0,R0,#32 ; Adjust Start Address
+ STR R0,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+ STMIA R0!,{R4-R7} ; Save old context (R4-R7)
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} ; Save old context (R8-R11)
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R0,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ ADDS R0,R0,#16 ; Adjust Start Address
+ LDMIA R0!,{R4-R7} ; Restore new Context (R8-R11)
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 ; Write PSP
+ SUBS R0,R0,#32 ; Adjust Start Address
+ LDMIA R0!,{R4-R7} ; Restore new Context (R4-R7)
+
+Sys_Exit
+ MOVS R0,#:NOT:0xFFFFFFFD ; Set EXC_RETURN value
+ MVNS R0,R0
+ BX R0 ; RETI to Thread Mode, use PSP
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM3.c b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM3.c
new file mode 100644
index 0000000..458aaa1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM3.c
@@ -0,0 +1,273 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM3.C
+ * Purpose: Hardware Abstraction Layer for Cortex-M3
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ MOVNE R0,#0x02 ; Privileged Thread mode, use PSP
+ MOVEQ R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_alloc_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm U32 _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_free_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+#ifdef IFX_XMC4XXX
+ EXPORT SVC_Handler_Veneer
+SVC_Handler_Veneer
+#endif
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ LDRB R1,[R1,#-2] ; Load SVC Number
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R12 ; Call SVC Function
+
+ MRS R12,PSP ; Read PSP
+ STM R12,{R0-R2} ; Store return values
+
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ SVC_Exit ; no task switch
+
+ CBZ R1,SVC_Next ; Runtask deleted?
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_Next
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ MSR PSP,R12 ; Write PSP
+
+SVC_Exit
+ MVN LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR
+#endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] ; Load SVC Function Address
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R4 ; Call SVC Function
+
+ MRS R12,PSP
+ STM R12,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT PendSV_Handler_Veneer
+PendSV_Handler_Veneer
+#endif
+
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+ BEQ Sys_Exit
+
+ MRS R12,PSP ; Read PSP
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ MSR PSP,R12 ; Write PSP
+
+Sys_Exit
+ MVN LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR ; Return to Thread Mode
+#endif
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SysTick_Handler_Veneer
+SysTick_Handler_Veneer
+#endif
+
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM4.c b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM4.c
new file mode 100644
index 0000000..badf097
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/HAL_CM4.c
@@ -0,0 +1,318 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM4.C
+ * Purpose: Hardware Abstraction Layer for Cortex-M4
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_HAL_CM.h"
+#include "rt_Task.h"
+#include "rt_MemBox.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+__asm void rt_set_PSP (U32 stack) {
+ MSR PSP,R0
+ BX LR
+}
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+__asm U32 rt_get_PSP (void) {
+ MRS R0,PSP
+ BX LR
+}
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+__asm void os_set_env (void) {
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+ MOV R0,SP ; PSP = MSP
+ MSR PSP,R0
+ LDR R0,=__cpp(&os_flags)
+ LDRB R0,[R0]
+ LSLS R0,#31
+ MOVNE R0,#0x02 ; Privileged Thread mode, use PSP
+ MOVEQ R0,#0x03 ; Unprivileged Thread mode, use PSP
+ MSR CONTROL,R0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+__asm void *_alloc_box (void *box_mem) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_alloc_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+__asm U32 _free_box (void *box_mem, void *box) {
+ /* Function wrapper for Unprivileged/Privileged mode. */
+ LDR R12,=__cpp(rt_free_box)
+ MRS R3,IPSR
+ LSLS R3,#24
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ ALIGN
+}
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+__asm void SVC_Handler (void) {
+ PRESERVE8
+
+ IMPORT SVC_Count
+ IMPORT SVC_Table
+ IMPORT rt_stk_check
+
+#ifdef IFX_XMC4XXX
+ EXPORT SVC_Handler_Veneer
+SVC_Handler_Veneer
+#endif
+
+ MRS R0,PSP ; Read PSP
+ LDR R1,[R0,#24] ; Read Saved PC from Stack
+ LDRB R1,[R1,#-2] ; Load SVC Number
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BLX R12 ; Call SVC Function
+ POP {R4,LR} ; Restore EXC_RETURN
+
+ MRS R12,PSP ; Read PSP
+ STM R12,{R0-R2} ; Store return values
+
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+#ifdef IFX_XMC4XXX
+ PUSHEQ {LR}
+ POPEQ {PC}
+#else
+ BXEQ LR ; RETI, no task switch
+#endif
+
+ CBNZ R1,SVC_ContextSave ; Runtask not deleted?
+
+ TST LR,#0x10 ; is it extended frame?
+ BNE SVC_ContextRestore
+ LDR R1,=0xE000EF34
+ LDR R0,[R1] ; Load FPCCR
+ BIC R0,#1 ; Clear LSPACT (Lazy state)
+ STR R0,[R1] ; Store FPCCR
+ B SVC_ContextRestore
+
+SVC_ContextSave
+ TST LR,#0x10 ; is it extended frame?
+ VSTMDBEQ R12!,{S16-S31} ; yes, stack also VFP hi-regs
+ MOVEQ R0,#0x01 ; os_tsk->stack_frame val
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] ; os_tsk.run->stack_frame = val
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+SVC_ContextRestore
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ LDRB R0,[R2,#TCB_STACKF] ; Stack Frame
+ CMP R0,#0 ; Basic/Extended Stack Frame
+ MVNEQ LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+ MVNNE LR,#:NOT:0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} ; restore VFP hi-registers
+ MSR PSP,R12 ; Write PSP
+
+SVC_Exit
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR
+#endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User
+ PUSH {R4,LR} ; Save Registers
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done ; Overflow
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] ; Load SVC Function Address
+
+ LDM R0,{R0-R3,R12} ; Read R0-R3,R12 from stack
+ BLX R4 ; Call SVC Function
+
+ MRS R12,PSP
+ STM R12,{R0-R3} ; Function return values
+SVC_Done
+ POP {R4,PC} ; RETI
+
+ ALIGN
+}
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+__asm void PendSV_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT PendSV_Handler_Veneer
+PendSV_Handler_Veneer
+#endif
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(rt_pop_req)
+
+Sys_Switch
+ POP {R4,LR} ; Restore EXC_RETURN
+
+ LDR R3,=__cpp(&os_tsk)
+ LDM R3,{R1,R2} ; os_tsk.run, os_tsk.new
+ CMP R1,R2
+#ifdef IFX_XMC4XXX
+ PUSHEQ {LR}
+ POPEQ {PC}
+#else
+ BXEQ LR ; RETI, no task switch
+#endif
+
+ MRS R12,PSP ; Read PSP
+ TST LR,#0x10 ; is it extended frame?
+ VSTMDBEQ R12!,{S16-S31} ; yes, stack also VFP hi-regs
+ MOVEQ R0,#0x01 ; os_tsk->stack_frame val
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] ; os_tsk.run->stack_frame = val
+ STMDB R12!,{R4-R11} ; Save Old context
+ STR R12,[R1,#TCB_TSTACK] ; Update os_tsk.run->tsk_stack
+
+ PUSH {R2,R3}
+ BL rt_stk_check ; Check for Stack overflow
+ POP {R2,R3}
+
+ STR R2,[R3] ; os_tsk.run = os_tsk.new
+
+ LDR R12,[R2,#TCB_TSTACK] ; os_tsk.new->tsk_stack
+ LDMIA R12!,{R4-R11} ; Restore New Context
+ LDRB R0,[R2,#TCB_STACKF] ; Stack Frame
+ CMP R0,#0 ; Basic/Extended Stack Frame
+ MVNEQ LR,#:NOT:0xFFFFFFFD ; set EXC_RETURN value
+ MVNNE LR,#:NOT:0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} ; restore VFP hi-regs
+ MSR PSP,R12 ; Write PSP
+
+Sys_Exit
+#ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+#else
+ BX LR ; Return to Thread Mode
+#endif
+
+ ALIGN
+}
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+__asm void SysTick_Handler (void) {
+ PRESERVE8
+
+#ifdef IFX_XMC4XXX
+ EXPORT SysTick_Handler_Veneer
+SysTick_Handler_Veneer
+#endif
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+__asm void OS_Tick_Handler (void) {
+ PRESERVE8
+
+ PUSH {R4,LR} ; Save EXC_RETURN
+ BL __cpp(os_tick_irqack)
+ BL __cpp(rt_systick)
+ B Sys_Switch
+
+ ALIGN
+}
+
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/RTE/RTE_Components.h b/CMSIS/RTOS/RTX/SRC/ARM/RTE/RTE_Components.h
new file mode 100644
index 0000000..bd96218
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/RTE/RTE_Components.h
@@ -0,0 +1,14 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'RTX_Lib_CM'
+ * Target: 'CM0_LE'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvoptx b/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvoptx
new file mode 100644
index 0000000..a300cc1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvoptx
@@ -0,0 +1,1497 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>CM0_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM0_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>0</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM0_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM0_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_LE_IFX</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_LE_IFX\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3X_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3X_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
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+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
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+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
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+ <periodic>1</periodic>
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+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
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+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
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+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
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+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
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+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
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+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
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+ <sRmem>1</sRmem>
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+ <sDll></sDll>
+ <sDllPa></sDllPa>
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+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
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+ <THDelay>0</THDelay>
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+ <DebugFlag>
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+ <StkLoc>0</StkLoc>
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+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_LE_IFX</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
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+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
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+ <OPTLEX>
+ <PageWidth>79</PageWidth>
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+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_LE_IFX\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
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+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
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+ <LLibSym>1</LLibSym>
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+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
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+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
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+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>-UU0101L5E -O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
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+ <viewmode>1</viewmode>
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+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
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+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\rt_CMSIS.c</PathWithFileName>
+ <FilenameWithoutPath>rt_CMSIS.c</FilenameWithoutPath>
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+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <tvExp>0</tvExp>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>..\rt_Task.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Task.c</FilenameWithoutPath>
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+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\rt_System.c</PathWithFileName>
+ <FilenameWithoutPath>rt_System.c</FilenameWithoutPath>
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+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
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+ </File>
+ <File>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>..\rt_List.c</PathWithFileName>
+ <FilenameWithoutPath>rt_List.c</FilenameWithoutPath>
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+ <File>
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+ <FilenameWithoutPath>rt_Mutex.c</FilenameWithoutPath>
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+ <FilenameWithoutPath>rt_Robin.c</FilenameWithoutPath>
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+ </File>
+ <File>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
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+ </File>
+ <File>
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+ <FilenameWithoutPath>rt_Memory.c</FilenameWithoutPath>
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+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>HAL</GroupName>
+ <tvExp>1</tvExp>
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+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
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+ <tvExp>0</tvExp>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\SVC_Table.s</PathWithFileName>
+ <FilenameWithoutPath>SVC_Table.s</FilenameWithoutPath>
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+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
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+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\HAL_CM.c</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM.c</FilenameWithoutPath>
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+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>16</FileNumber>
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+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\HAL_CM0.c</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
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+ <File>
+ <GroupNumber>2</GroupNumber>
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+ <bDave2>0</bDave2>
+ <PathWithFileName>.\HAL_CM4.c</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM4.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
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+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ <tvExp>0</tvExp>
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+ <RteFlg>1</RteFlg>
+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvprojx b/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvprojx
new file mode 100644
index 0000000..5376695
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/RTX_Lib_CM.uvprojx
@@ -0,0 +1,6332 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>CM0_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM0_LE\</OutputDirectory>
+ <OutputName>RTX_CM0</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM0_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM0_LE\RTX_CM0.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> </SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>0</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\AGDIRDI.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM0_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM0_BE\</OutputDirectory>
+ <OutputName>RTX_CM0_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM0_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM0_BE\RTX_CM0_B.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> </SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>1</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_LE\</OutputDirectory>
+ <OutputName>RTX_CM3</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_LE\RTX_CM3.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_BE\</OutputDirectory>
+ <OutputName>RTX_CM3_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_BE\RTX_CM3_B.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>1</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_LE_IFX</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_LE_IFX\</OutputDirectory>
+ <OutputName>RTX_CM3_IFX</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_LE_IFX\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_LE_IFX\RTX_CM3_IFX.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>IFX_XMC4XXX</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3X_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3X_LE\</OutputDirectory>
+ <OutputName>RTX_CM3X</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3X_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3X_LE\RTX_CM3X.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>2</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG NO_EXCLUSIVE_ACCESS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_LE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_LE\</OutputDirectory>
+ <OutputName>RTX_CM4</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_LE\RTX_CM4.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4097</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_BE</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_BE\</OutputDirectory>
+ <OutputName>RTX_CM4_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_BE\RTX_CM4_B.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4097</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>1</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_LE_IFX</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <pCCUsed>5060020::V5.06 (build 20)::ARMCC</pCCUsed>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.4.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_LE_IFX\</OutputDirectory>
+ <OutputName>RTX_CM4_IFX</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_LE_IFX\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>1</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_LE_IFX\RTX_CM4_IFX.lib ..\..\LIB\ARM</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4097</DriverSelection>
+ </Flash1>
+ <bUseTDR>0</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>0</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>0</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <nSecure>0</nSecure>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>1</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>4</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>1</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <uC99>0</uC99>
+ <useXO>0</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls>--diag_suppress 3731</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>1</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <useXO>0</useXO>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>0</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <pXoBase></pXoBase>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM0.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM3.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\HAL_CM4.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArmAds>
+ <Cads>
+ <interw>2</interw>
+ <Optim>0</Optim>
+ <oTime>2</oTime>
+ <SplitLS>2</SplitLS>
+ <OneElfS>2</OneElfS>
+ <Strict>2</Strict>
+ <EnumInt>2</EnumInt>
+ <PlainCh>2</PlainCh>
+ <Ropi>2</Ropi>
+ <Rwpi>2</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <uSurpInc>2</uSurpInc>
+ <uC99>2</uC99>
+ <useXO>2</useXO>
+ <v6Lang>0</v6Lang>
+ <v6LangP>0</v6LangP>
+ <vShortEn>0</vShortEn>
+ <vShortWch>0</vShortWch>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>IFX_XMC4XXX</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\</IncludePath>
+ </VariousControls>
+ </Cads>
+ </FileArmAds>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+ <targetInfos>
+ <targetInfo name="CM0_BE"/>
+ <targetInfo name="CM0_LE"/>
+ <targetInfo name="CM3X_LE"/>
+ <targetInfo name="CM3_BE"/>
+ <targetInfo name="CM3_LE"/>
+ <targetInfo name="CM3_LE_IFX"/>
+ <targetInfo name="CM4F_BE"/>
+ <targetInfo name="CM4F_LE"/>
+ <targetInfo name="CM4F_LE_IFX"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files/>
+ </RTE>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s b/CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s
new file mode 100644
index 0000000..98fce28
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/ARM/SVC_Table.s
@@ -0,0 +1,57 @@
+;/*----------------------------------------------------------------------------
+; * CMSIS-RTOS - RTX
+; *----------------------------------------------------------------------------
+; * Name: SVC_TABLE.S
+; * Purpose: Pre-defined SVC Table for Cortex-M
+; * Rev.: V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; * - Redistributions of source code must retain the above copyright
+; * notice, this list of conditions and the following disclaimer.
+; * - Redistributions in binary form must reproduce the above copyright
+; * notice, this list of conditions and the following disclaimer in the
+; * documentation and/or other materials provided with the distribution.
+; * - Neither the name of ARM nor the names of its contributors may be used
+; * to endorse or promote products derived from this software without
+; * specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+ AREA SVC_TABLE, CODE, READONLY
+
+ EXPORT SVC_Count
+
+SVC_Cnt EQU (SVC_End-SVC_Table)/4
+SVC_Count DCD SVC_Cnt
+
+; Import user SVC functions here.
+; IMPORT __SVC_1
+
+ EXPORT SVC_Table
+SVC_Table
+; Insert user SVC functions here. SVC 0 used by RTL Kernel.
+; DCD __SVC_1 ; user SVC function
+
+SVC_End
+
+ END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM0.s b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM0.s
new file mode 100644
index 0000000..9672b53
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM0.s
@@ -0,0 +1,370 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM0.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M0
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ .file "HAL_CM0.S"
+ .syntax unified
+
+ .equ TCB_TSTACK, 40
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ .thumb
+
+ .section ".text"
+ .align 2
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+# void rt_set_PSP (U32 stack);
+
+ .thumb_func
+ .type rt_set_PSP, %function
+ .global rt_set_PSP
+rt_set_PSP:
+ .fnstart
+ .cantunwind
+
+ MSR PSP,R0
+ BX LR
+
+ .fnend
+ .size rt_set_PSP, .-rt_set_PSP
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+# U32 rt_get_PSP (void);
+
+ .thumb_func
+ .type rt_get_PSP, %function
+ .global rt_get_PSP
+rt_get_PSP:
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP
+ BX LR
+
+ .fnend
+ .size rt_get_PSP, .-rt_get_PSP
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+# void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ .thumb_func
+ .type os_set_env, %function
+ .global os_set_env
+os_set_env:
+ .fnstart
+ .cantunwind
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ BNE PrivilegedE
+ MOVS R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+PrivilegedE:
+ MOVS R0,#0x02 /* Privileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+ .fnend
+ .size os_set_env, .-os_set_env
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+# void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _alloc_box, %function
+ .global _alloc_box
+_alloc_box:
+ .fnstart
+ .cantunwind
+
+ LDR R3,=rt_alloc_box
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedA
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedA
+ SVC 0
+ BX LR
+PrivilegedA:
+ BX R12
+
+ .fnend
+ .size _alloc_box, .-_alloc_box
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+# U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _free_box, %function
+ .global _free_box
+_free_box:
+ .fnstart
+ .cantunwind
+
+ LDR R3,=rt_free_box
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedF
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedF
+ SVC 0
+ BX LR
+PrivilegedF:
+ BX R12
+
+ .fnend
+ .size _free_box, .-_free_box
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+# void SVC_Handler (void);
+
+ .thumb_func
+ .type SVC_Handler, %function
+ .global SVC_Handler
+SVC_Handler:
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ SUBS R1,R1,#2 /* Point to SVC Instruction */
+ LDRB R1,[R1] /* Load SVC Number */
+ CMP R1,#0
+ BNE SVC_User /* User SVC Number > 0 */
+
+ MOV LR,R4
+ LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */
+ MOV R12,R4
+ MOV R4,LR
+ BLX R12 /* Call SVC Function */
+
+ MRS R3,PSP /* Read PSP */
+ STMIA R3!,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ SVC_Exit /* no task switch */
+
+ SUBS R3,#8
+ CMP R1,#0 /* Runtask deleted? */
+ BEQ SVC_Next
+
+ MRS R0,PSP /* Read PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+ STMIA R0!,{R4-R7} /* Save old context (R4-R7) */
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} /* Save old context (R8-R11) */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_Next:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ ADDS R0,R0,#16 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 /* Write PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */
+
+SVC_Exit:
+ MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */
+ MVNS R0,R0
+ BX R0 /* RETI to Thread Mode, use PSP */
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LSLS R1,R1,#2
+ LDR R4,[R4,R1] /* Load SVC Function Address */
+ MOV LR,R4
+
+ LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */
+ MOV R12,R4
+ BLX LR /* Call SVC Function */
+
+ MRS R4,PSP /* Read PSP */
+ STMIA R4!,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+ .fnend
+ .size SVC_Handler, .-SVC_Handler
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+# void PendSV_Handler (void);
+
+ .thumb_func
+ .type PendSV_Handler, %function
+ .global PendSV_Handler
+ .global Sys_Switch
+PendSV_Handler:
+ .fnstart
+ .cantunwind
+
+ BL rt_pop_req
+
+Sys_Switch:
+ LDR R3,=os_tsk
+ LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ Sys_Exit /* no task switch */
+
+ SUBS R3,#8
+
+ MRS R0,PSP /* Read PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+ STMIA R0!,{R4-R7} /* Save old context (R4-R7) */
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} /* Save old context (R8-R11) */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ ADDS R0,R0,#16 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 /* Write PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */
+
+Sys_Exit:
+ MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */
+ MVNS R0,R0
+ BX R0 /* RETI to Thread Mode, use PSP */
+
+ .fnend
+ .size PendSV_Handler, .-PendSV_Handler
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+# void SysTick_Handler (void);
+
+ .thumb_func
+ .type SysTick_Handler, %function
+ .global SysTick_Handler
+SysTick_Handler:
+ .fnstart
+ .cantunwind
+
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size SysTick_Handler, .-SysTick_Handler
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+# void OS_Tick_Handler (void);
+
+ .thumb_func
+ .type OS_Tick_Handler, %function
+ .global OS_Tick_Handler
+OS_Tick_Handler:
+ .fnstart
+ .cantunwind
+
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size OS_Tick_Handler, .-OS_Tick_Handler
+
+
+ .end
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM3.s b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM3.s
new file mode 100644
index 0000000..5cfede3
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM3.s
@@ -0,0 +1,345 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM3.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M3
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ .file "HAL_CM3.S"
+ .syntax unified
+
+ .equ TCB_TSTACK, 40
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ .thumb
+
+ .section ".text"
+ .align 2
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+# void rt_set_PSP (U32 stack);
+
+ .thumb_func
+ .type rt_set_PSP, %function
+ .global rt_set_PSP
+rt_set_PSP:
+ .fnstart
+ .cantunwind
+
+ MSR PSP,R0
+ BX LR
+
+ .fnend
+ .size rt_set_PSP, .-rt_set_PSP
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+# U32 rt_get_PSP (void);
+
+ .thumb_func
+ .type rt_get_PSP, %function
+ .global rt_get_PSP
+rt_get_PSP:
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP
+ BX LR
+
+ .fnend
+ .size rt_get_PSP, .-rt_get_PSP
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+# void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ .thumb_func
+ .type os_set_env, %function
+ .global os_set_env
+os_set_env:
+ .fnstart
+ .cantunwind
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ ITE NE
+ MOVNE R0,#0x02 /* Privileged Thread mode, use PSP */
+ MOVEQ R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+ .fnend
+ .size os_set_env, .-os_set_env
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+# void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _alloc_box, %function
+ .global _alloc_box
+_alloc_box:
+ .fnstart
+ .cantunwind
+
+ LDR R12,=rt_alloc_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ .fnend
+ .size _alloc_box, .-_alloc_box
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+# U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _free_box, %function
+ .global _free_box
+_free_box:
+ .fnstart
+ .cantunwind
+
+ LDR R12,=rt_free_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ .fnend
+ .size _free_box, .-_free_box
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+# void SVC_Handler (void);
+
+ .thumb_func
+ .type SVC_Handler, %function
+ .global SVC_Handler
+SVC_Handler:
+ .ifdef IFX_XMC4XXX
+ .global SVC_Handler_Veneer
+SVC_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ LDRB R1,[R1,#-2] /* Load SVC Number */
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R12 /* Call SVC Function */
+
+ MRS R12,PSP /* Read PSP */
+ STM R12,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ SVC_Exit /* no task switch */
+
+ CBZ R1,SVC_Next /* Runtask deleted? */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_Next:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ MSR PSP,R12 /* Write PSP */
+
+SVC_Exit:
+ MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ .ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+ .else
+ BX LR
+ .endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] /* Load SVC Function Address */
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R4 /* Call SVC Function */
+
+ MRS R12,PSP
+ STM R12,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+ .fnend
+ .size SVC_Handler, .-SVC_Handler
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+# void PendSV_Handler (void);
+
+ .thumb_func
+ .type PendSV_Handler, %function
+ .global PendSV_Handler
+ .global Sys_Switch
+PendSV_Handler:
+ .ifdef IFX_XMC4XXX
+ .global PendSV_Handler_Veneer
+PendSV_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ BL rt_pop_req
+
+Sys_Switch:
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ Sys_Exit
+
+ MRS R12,PSP /* Read PSP */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ MSR PSP,R12 /* Write PSP */
+
+Sys_Exit:
+ MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ .ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+ .else
+ BX LR /* Return to Thread Mode */
+ .endif
+
+ .fnend
+ .size PendSV_Handler, .-PendSV_Handler
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+# void SysTick_Handler (void);
+
+ .thumb_func
+ .type SysTick_Handler, %function
+ .global SysTick_Handler
+SysTick_Handler:
+ .ifdef IFX_XMC4XXX
+ .global SysTick_Handler_Veneer
+SysTick_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size SysTick_Handler, .-SysTick_Handler
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+# void OS_Tick_Handler (void);
+
+ .thumb_func
+ .type OS_Tick_Handler, %function
+ .global OS_Tick_Handler
+OS_Tick_Handler:
+ .fnstart
+ .cantunwind
+
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size OS_Tick_Handler, .-OS_Tick_Handler
+
+
+ .end
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM4.s b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM4.s
new file mode 100644
index 0000000..c3e60a6
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/HAL_CM4.s
@@ -0,0 +1,399 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM4.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M4
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ .file "HAL_CM4.S"
+ .syntax unified
+
+ .equ TCB_STACKF, 37
+ .equ TCB_TSTACK, 40
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ .thumb
+
+ .section ".text"
+ .align 2
+
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+# void rt_set_PSP (U32 stack);
+
+ .thumb_func
+ .type rt_set_PSP, %function
+ .global rt_set_PSP
+rt_set_PSP:
+ .fnstart
+ .cantunwind
+
+ MSR PSP,R0
+ BX LR
+
+ .fnend
+ .size rt_set_PSP, .-rt_set_PSP
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+# U32 rt_get_PSP (void);
+
+ .thumb_func
+ .type rt_get_PSP, %function
+ .global rt_get_PSP
+rt_get_PSP:
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP
+ BX LR
+
+ .fnend
+ .size rt_get_PSP, .-rt_get_PSP
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+# void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ .thumb_func
+ .type os_set_env, %function
+ .global os_set_env
+os_set_env:
+ .fnstart
+ .cantunwind
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ ITE NE
+ MOVNE R0,#0x02 /* Privileged Thread mode, use PSP */
+ MOVEQ R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+ .fnend
+ .size os_set_env, .-os_set_env
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+# void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _alloc_box, %function
+ .global _alloc_box
+_alloc_box:
+ .fnstart
+ .cantunwind
+
+ LDR R12,=rt_alloc_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ .fnend
+ .size _alloc_box, .-_alloc_box
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+# U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ .thumb_func
+ .type _free_box, %function
+ .global _free_box
+_free_box:
+ .fnstart
+ .cantunwind
+
+ LDR R12,=rt_free_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+ .fnend
+ .size _free_box, .-_free_box
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+# void SVC_Handler (void);
+
+ .thumb_func
+ .type SVC_Handler, %function
+ .global SVC_Handler
+SVC_Handler:
+ .ifdef IFX_XMC4XXX
+ .global SVC_Handler_Veneer
+SVC_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ LDRB R1,[R1,#-2] /* Load SVC Number */
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BLX R12 /* Call SVC Function */
+ POP {R4,LR} /* Restore EXC_RETURN */
+
+ MRS R12,PSP /* Read PSP */
+ STM R12,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ .ifdef IFX_XMC4XXX
+ ITT EQ
+ PUSHEQ {LR}
+ POPEQ {PC}
+ .else
+ IT EQ
+ BXEQ LR /* RETI, no task switch */
+ .endif
+
+ CBNZ R1,SVC_ContextSave /* Runtask not deleted? */
+
+ TST LR,#0x10 /* is it extended frame? */
+ BNE SVC_ContextRestore
+ LDR R1,=0xE000EF34
+ LDR R0,[R1] /* Load FPCCR */
+ BIC R0,#1 /* Clear LSPACT (Lazy state) */
+ STR R0,[R1] /* Store FPCCR */
+ B SVC_ContextRestore
+
+SVC_ContextSave:
+ TST LR,#0x10 /* is it extended frame? */
+ ITTE EQ
+ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
+ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_ContextRestore:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
+ CMP R0,#0 /* Basic/Extended Stack Frame */
+ ITEE EQ
+ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ MVNNE LR,#~0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
+ MSR PSP,R12 /* Write PSP */
+
+SVC_Exit:
+ .ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+ .else
+ BX LR
+ .endif
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] /* Load SVC Function Address */
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R4 /* Call SVC Function */
+
+ MRS R12,PSP
+ STM R12,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+ .fnend
+ .size SVC_Handler, .-SVC_Handler
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+# void PendSV_Handler (void);
+
+ .thumb_func
+ .type PendSV_Handler, %function
+ .global PendSV_Handler
+ .global Sys_Switch
+PendSV_Handler:
+ .ifdef IFX_XMC4XXX
+ .global PendSV_Handler_Veneer
+PendSV_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL rt_pop_req
+
+Sys_Switch:
+ POP {R4,LR} /* Restore EXC_RETURN */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ .ifdef IFX_XMC4XXX
+ ITT EQ
+ PUSHEQ {LR}
+ POPEQ {PC}
+ .else
+ IT EQ
+ BXEQ LR /* RETI, no task switch */
+ .endif
+
+ MRS R12,PSP /* Read PSP */
+ TST LR,#0x10 /* is it extended frame? */
+ ITTE EQ
+ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
+ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
+ CMP R0,#0 /* Basic/Extended Stack Frame */
+ ITEE EQ
+ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ MVNNE LR,#~0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
+ MSR PSP,R12 /* Write PSP */
+
+Sys_Exit:
+ .ifdef IFX_XMC4XXX
+ PUSH {LR}
+ POP {PC}
+ .else
+ BX LR /* Return to Thread Mode */
+ .endif
+
+ .fnend
+ .size PendSV_Handler, .-PendSV_Handler
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+# void SysTick_Handler (void);
+
+ .thumb_func
+ .type SysTick_Handler, %function
+ .global SysTick_Handler
+SysTick_Handler:
+ .ifdef IFX_XMC4XXX
+ .global SysTick_Handler_Veneer
+SysTick_Handler_Veneer:
+ .endif
+ .fnstart
+ .cantunwind
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size SysTick_Handler, .-SysTick_Handler
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+# void OS_Tick_Handler (void);
+
+ .thumb_func
+ .type OS_Tick_Handler, %function
+ .global OS_Tick_Handler
+OS_Tick_Handler:
+ .fnstart
+ .cantunwind
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+ .fnend
+ .size OS_Tick_Handler, .-OS_Tick_Handler
+
+
+ .end
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/RTE/RTE_Components.h b/CMSIS/RTOS/RTX/SRC/GCC/RTE/RTE_Components.h
new file mode 100644
index 0000000..bd96218
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/RTE/RTE_Components.h
@@ -0,0 +1,14 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ * *** Do not modify ! ***
+ *
+ * Project: 'RTX_Lib_CM'
+ * Target: 'CM0_LE'
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvoptx b/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvoptx
new file mode 100644
index 0000000..71e680e
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvoptx
@@ -0,0 +1,1362 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ <nMigrate>0</nMigrate>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>CM0_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM0_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM0_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM0_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM3_LE_IFX</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM3_LE_IFX\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL040000 -FS00 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_LE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_BE\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Target>
+ <TargetName>CM4F_LE_IFX</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>0</RunSim>
+ <RunTarget>1</RunTarget>
+ <RunAbUc>0</RunAbUc>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\CM4F_LE_IFX\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>0</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>7</CpuCode>
+ <DebugOpt>
+ <uSim>0</uSim>
+ <uTrg>1</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>1</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRSysVw>1</sRSysVw>
+ <tRSysVw>1</tRSysVw>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon>BIN\UL2CM3.DLL</pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>UL2CM3</Key>
+ <Name>UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0NEW_DEVICE -FL080000 -FS00 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM)</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>0</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ <bLintAuto>0</bLintAuto>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_CMSIS.c</PathWithFileName>
+ <FilenameWithoutPath>rt_CMSIS.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Task.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Task.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_System.c</PathWithFileName>
+ <FilenameWithoutPath>rt_System.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Event.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Event.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_List.c</PathWithFileName>
+ <FilenameWithoutPath>rt_List.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>6</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Mailbox.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Mailbox.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Semaphore.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Semaphore.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
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+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Time.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Time.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>9</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Timer.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Timer.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>10</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Mutex.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Mutex.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>11</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Robin.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Robin.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>12</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_MemBox.c</PathWithFileName>
+ <FilenameWithoutPath>rt_MemBox.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>13</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../rt_Memory.c</PathWithFileName>
+ <FilenameWithoutPath>rt_Memory.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>HAL</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>14</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\SVC_Table.s</PathWithFileName>
+ <FilenameWithoutPath>SVC_Table.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>15</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../HAL_CM.c</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>16</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\HAL_CM0.s</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM0.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>17</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\HAL_CM3.s</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM3.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>18</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\HAL_CM4.s</PathWithFileName>
+ <FilenameWithoutPath>HAL_CM4.s</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ <tvExp>0</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>1</RteFlg>
+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvprojx b/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvprojx
new file mode 100644
index 0000000..8519984
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/RTX_Lib_CM.uvprojx
@@ -0,0 +1,4147 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+ <SchemaVersion>2.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>CM0_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM0_LE\</OutputDirectory>
+ <OutputName>RTX_CM0</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM0_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM0_LE\libRTX_CM0.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> </SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>1</Capability>
+ <DriverSelection>4096</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M0"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
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+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-ffunction-sections</MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
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+ <enaGarb>1</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
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+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
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+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
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+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
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+ <FileName>rt_List.c</FileName>
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+ <FilePath>../rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
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+ <FilePath>../rt_Mailbox.c</FilePath>
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+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
+ <File>
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+ <FilePath>../rt_Time.c</FilePath>
+ </File>
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+ <File>
+ <FileName>rt_Mutex.c</FileName>
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+ <File>
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+ <FileName>rt_Memory.c</FileName>
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+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
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+ <ModuleSelection>0</ModuleSelection>
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+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
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+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
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+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
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+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM0_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM0</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM0$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM0$Device\ARM\ARMCM0\Include\ARMCM0.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM0$Device\ARM\SVD\ARMCM0.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM0_BE\</OutputDirectory>
+ <OutputName>RTX_CM0_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM0_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
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+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM0_BE\libRTX_CM0_B.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
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+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
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+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
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+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> </TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
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+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
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+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
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+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
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+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
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+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
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+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
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+ <asDbgD>1</asDbgD>
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+ <BigEnd>1</BigEnd>
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+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
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+ <hadIRAM2>0</hadIRAM2>
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+ </XRAM>
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+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
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+ <MiscControls>-ffunction-sections</MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M0 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
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+ <enaGarb>1</enaGarb>
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+ <TextAddressRange></TextAddressRange>
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+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
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+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FilePath>../rt_Memory.c</FilePath>
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+ </Files>
+ </Group>
+ <Group>
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+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
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+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
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+ </File>
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+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_LE\</OutputDirectory>
+ <OutputName>RTX_CM3</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_LE\libRTX_CM3.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-ffunction-sections</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>1</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Carm>
+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
+ <reentr>2</reentr>
+ <interw>2</interw>
+ <bigend>2</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_BE\</OutputDirectory>
+ <OutputName>RTX_CM3_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_BE\libRTX_CM3_B.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>1</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-ffunction-sections</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>1</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Carm>
+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
+ <reentr>2</reentr>
+ <interw>2</interw>
+ <bigend>2</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM3_LE_IFX</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM3</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M3") CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL040000 -FP0($$Device:ARMCM3$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM3_LE_IFX\</OutputDirectory>
+ <OutputName>RTX_CM3_IFX</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM3_LE_IFX\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM3_LE_IFX\libRTX_CM3_IFX.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
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+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
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+ <Size>0x40000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
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+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-ffunction-sections</MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CORTEX_M3 __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>1</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc></Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
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+ <ModuleSelection>0</ModuleSelection>
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+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Carm>
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+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
+ <CommonProperty>
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+ <ModuleSelection>0</ModuleSelection>
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+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
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+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
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+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>IFX_XMC4XXX</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
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+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
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+ <MiscControls></MiscControls>
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+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_LE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_LE\</OutputDirectory>
+ <OutputName>RTX_CM4</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_LE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_LE\libRTX_CM4.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
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+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
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+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
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+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
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+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
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+ <GCPUTYP>"Cortex-M4"</GCPUTYP>
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+ <hadIROM2>0</hadIROM2>
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+ <Size>0x80000</Size>
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+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
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+ <StartAddress>0x0</StartAddress>
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+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
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+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
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+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
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+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>
+ <Define>__CORTEX_M4F __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
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+ </Aarm>
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+ <IncludeDir></IncludeDir>
+ <Misc>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
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+ <StopOnExitCode>11</StopOnExitCode>
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+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
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+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
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+ <FileType>1</FileType>
+ <FilePath>../rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
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+ </File>
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+ </File>
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+ </File>
+ <File>
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+ <FilePath>../rt_Mailbox.c</FilePath>
+ </File>
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+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
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+ </File>
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+ <FilePath>../rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
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+ <FilePath>../rt_Mutex.c</FilePath>
+ </File>
+ <File>
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+ <FilePath>../rt_Robin.c</FilePath>
+ </File>
+ <File>
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+ <FilePath>../rt_MemBox.c</FilePath>
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+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
+ <CommonProperty>
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+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
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+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
+ <CommonProperty>
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+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
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+ <FileArm>
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+ <interw>2</interw>
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+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_BE</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_BE\</OutputDirectory>
+ <OutputName>RTX_CM4_B</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_BE\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_BE\libRTX_CM4_B.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
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+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
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+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
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+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
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+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
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+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
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+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
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+ <TargetArm>
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+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
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+ <BigEnd>1</BigEnd>
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+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
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+ <StartAddress>0x0</StartAddress>
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+ </XRAM>
+ <IRAM2>
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+ <IROM2>
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+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
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+ <Strict>0</Strict>
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+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
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+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>
+ <Define>__CORTEX_M4F __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>1</enaGarb>
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+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
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+ <StopOnExitCode>11</StopOnExitCode>
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+ </File>
+ <File>
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+ <File>
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+ <FileType>1</FileType>
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+ <File>
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+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
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+ <File>
+ <FileName>rt_Mailbox.c</FileName>
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+ <File>
+ <FileName>rt_Timer.c</FileName>
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+ <File>
+ <FileName>rt_Mutex.c</FileName>
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+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
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+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
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+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
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+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
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+ <interw>2</interw>
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+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ <Target>
+ <TargetName>CM4F_LE_IFX</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>ARMCM4_FP</Device>
+ <Vendor>ARM</Vendor>
+ <PackID>ARM.CMSIS.4.3.0</PackID>
+ <PackURL>http://www.keil.com/pack/</PackURL>
+ <Cpu>IROM(0x00000000,0x80000) IRAM(0x20000000,0x20000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0NEW_DEVICE -FS00 -FL080000 -FP0($$Device:ARMCM4_FP$Device\ARM\Flash\NEW_DEVICE.FLM))</FlashDriverDll>
+ <DeviceId>0</DeviceId>
+ <RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
+ <bCustSvd>0</bCustSvd>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\CM4F_LE_IFX\</OutputDirectory>
+ <OutputName>RTX_CM4_IFX</OutputName>
+ <CreateExecutable>0</CreateExecutable>
+ <CreateLib>1</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\CM4F_LE_IFX\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopB1X>0</nStopB1X>
+ <nStopB2X>0</nStopB2X>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>1</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name>cmd.exe /C copy CM4F_LE_IFX\libRTX_CM4_IFX.a ..\..\LIB\GCC\</UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopA1X>0</nStopA1X>
+ <nStopA2X>0</nStopA2X>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments> -MPU</SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments> -MPU</TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>0</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Simulator>
+ <Target>
+ <UseTarget>1</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ <RestoreSysVw>1</RestoreSysVw>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver>BIN\UL2CM3.DLL</Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <bUseTDR>1</bUseTDR>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ <pFcarmOut></pFcarmOut>
+ <pFcarmGrp></pFcarmGrp>
+ <pFcArmRoot></pFcArmRoot>
+ <FcArmLst>0</FcArmLst>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M4"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x20000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>5</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections</MiscControls>
+ <Define>__CORTEX_M4F __FPU_PRESENT=1 __CMSIS_RTOS DBG_MSG</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>
+ <Define>__CORTEX_M4F __CMSIS_RTOS</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>1</enaGarb>
+ <noStart>1</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-mfpu=fpv4-sp-d16 -mfloat-abi=hard</Misc>
+ <ScatterFile></ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Kernel</GroupName>
+ <Files>
+ <File>
+ <FileName>rt_CMSIS.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_CMSIS.c</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Carm>
+ <arpcs>2</arpcs>
+ <stkchk>2</stkchk>
+ <reentr>2</reentr>
+ <interw>2</interw>
+ <bigend>2</bigend>
+ <Strict>0</Strict>
+ <Optim>0</Optim>
+ <wLevel>0</wLevel>
+ <uThumb>2</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>rt_Task.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Task.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_System.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_System.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Event.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Event.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_List.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_List.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mailbox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mailbox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Semaphore.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Semaphore.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Time.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Time.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Timer.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Timer.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Mutex.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Mutex.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Robin.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Robin.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_MemBox.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_MemBox.c</FilePath>
+ </File>
+ <File>
+ <FileName>rt_Memory.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../rt_Memory.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>HAL</GroupName>
+ <Files>
+ <File>
+ <FileName>SVC_Table.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\SVC_Table.s</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../HAL_CM.c</FilePath>
+ </File>
+ <File>
+ <FileName>HAL_CM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM0.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM3.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>0</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ <File>
+ <FileName>HAL_CM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\HAL_CM4.s</FilePath>
+ <FileOption>
+ <CommonProperty>
+ <UseCPPCompiler>2</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>2</IncludeInBuild>
+ <AlwaysBuild>2</AlwaysBuild>
+ <GenerateAssemblyFile>2</GenerateAssemblyFile>
+ <AssembleAssemblyFile>2</AssembleAssemblyFile>
+ <PublicsOnly>2</PublicsOnly>
+ <StopOnExitCode>11</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ <ComprImg>1</ComprImg>
+ </CommonProperty>
+ <FileArm>
+ <Aarm>
+ <bBE>2</bBE>
+ <interw>2</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>IFX_XMC4XXX</Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ </FileArm>
+ </FileOption>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>::CMSIS</GroupName>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+ <RTE>
+ <apis/>
+ <components>
+ <component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
+ <package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
+ <targetInfos>
+ <targetInfo name="CM0_BE"/>
+ <targetInfo name="CM0_LE"/>
+ <targetInfo name="CM3_BE"/>
+ <targetInfo name="CM3_LE"/>
+ <targetInfo name="CM3_LE_IFX"/>
+ <targetInfo name="CM4F_BE"/>
+ <targetInfo name="CM4F_LE"/>
+ <targetInfo name="CM4F_LE_IFX"/>
+ </targetInfos>
+ </component>
+ </components>
+ <files/>
+ </RTE>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S b/CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S
new file mode 100644
index 0000000..5c64a76
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/GCC/SVC_Table.S
@@ -0,0 +1,56 @@
+;/*----------------------------------------------------------------------------
+; * CMSIS-RTOS - RTX
+; *----------------------------------------------------------------------------
+; * Name: SVC_TABLE.S
+; * Purpose: Pre-defined SVC Table for Cortex-M
+; * Rev.: V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; * - Redistributions of source code must retain the above copyright
+; * notice, this list of conditions and the following disclaimer.
+; * - Redistributions in binary form must reproduce the above copyright
+; * notice, this list of conditions and the following disclaimer in the
+; * documentation and/or other materials provided with the distribution.
+; * - Neither the name of ARM nor the names of its contributors may be used
+; * to endorse or promote products derived from this software without
+; * specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+ .file "SVC_Table.S"
+
+
+ .section ".svc_table"
+
+ .global SVC_Table
+SVC_Table:
+/* Insert user SVC functions here. SVC 0 used by RTL Kernel. */
+# .long __SVC_1 /* user SVC function */
+SVC_End:
+
+ .global SVC_Count
+SVC_Count:
+ .long (SVC_End-SVC_Table)/4
+
+
+ .end
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/HAL_CM.c b/CMSIS/RTOS/RTX/SRC/HAL_CM.c
new file mode 100644
index 0000000..cd994e9
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/HAL_CM.c
@@ -0,0 +1,180 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM.C
+ * Purpose: Hardware Abstraction Layer for Cortex-M
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+#ifdef DBG_MSG
+BIT dbg_msg;
+#endif
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_init_stack ---------------------------------*/
+
+void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
+ /* Prepare TCB and saved context for a first time start of a task. */
+ U32 *stk,i,size;
+
+ /* Prepare a complete interrupt frame for first task start */
+ size = p_TCB->priv_stack >> 2;
+ if (size == 0U) {
+ size = (U16)os_stackinfo >> 2;
+ }
+
+ /* Write to the top of stack. */
+ stk = &p_TCB->stack[size];
+
+ /* Auto correct to 8-byte ARM stack alignment. */
+ if ((U32)stk & 0x04U) {
+ stk--;
+ }
+
+ stk -= 16;
+
+ /* Default xPSR and initial PC */
+ stk[15] = INITIAL_xPSR;
+ stk[14] = (U32)task_body;
+
+ /* Clear R4-R11,R0-R3,R12,LR registers. */
+ for (i = 0U; i < 14U; i++) {
+ stk[i] = 0U;
+ }
+
+ /* Assign a void pointer to R0. */
+ stk[8] = (U32)p_TCB->msg;
+
+ /* Initial Task stack pointer. */
+ p_TCB->tsk_stack = (U32)stk;
+
+ /* Task entry point. */
+ p_TCB->ptask = task_body;
+
+ /* Initialize stack with magic pattern. */
+ if (os_stackinfo & 0x10000000U) {
+ if (size > (16U+1U)) {
+ for (i = ((size - 16U)/2U) - 1U; i; i--) {
+ stk -= 2U;
+ stk[1] = MAGIC_PATTERN;
+ stk[0] = MAGIC_PATTERN;
+ }
+ if (--stk > p_TCB->stack) {
+ *stk = MAGIC_PATTERN;
+ }
+ }
+ }
+
+ /* Set a magic word for checking of stack overflow. */
+ p_TCB->stack[0] = MAGIC_WORD;
+}
+
+
+/*--------------------------- rt_ret_val ----------------------------------*/
+
+static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
+ /* Get pointer to task return value registers (R0..R3) in Stack */
+#if defined(__TARGET_FPU_VFP)
+ if (p_TCB->stack_frame) {
+ /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
+ return (U32 *)(p_TCB->tsk_stack + (8U*4U) + (16U*4U));
+ } else {
+ /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
+ return (U32 *)(p_TCB->tsk_stack + (8U*4U));
+ }
+#else
+ /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
+ return (U32 *)(p_TCB->tsk_stack + (8U*4U));
+#endif
+}
+
+void rt_ret_val (P_TCB p_TCB, U32 v0) {
+ U32 *ret;
+
+ ret = rt_ret_regs(p_TCB);
+ ret[0] = v0;
+}
+
+void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
+ U32 *ret;
+
+ ret = rt_ret_regs(p_TCB);
+ ret[0] = v0;
+ ret[1] = v1;
+}
+
+
+/*--------------------------- dbg_init --------------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_init (void) {
+ if (((DEMCR & DEMCR_TRCENA) != 0U) &&
+ ((ITM_CONTROL & ITM_ITMENA) != 0U) &&
+ ((ITM_ENABLE & (1UL << 31)) != 0U)) {
+ dbg_msg = __TRUE;
+ }
+}
+#endif
+
+/*--------------------------- dbg_task_notify -------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_task_notify (P_TCB p_tcb, BOOL create) {
+ while (ITM_PORT31_U32 == 0U);
+ ITM_PORT31_U32 = (U32)p_tcb->ptask;
+ while (ITM_PORT31_U32 == 0U);
+ ITM_PORT31_U16 = (U16)((create << 8) | p_tcb->task_id);
+}
+#endif
+
+/*--------------------------- dbg_task_switch -------------------------------*/
+
+#ifdef DBG_MSG
+void dbg_task_switch (U32 task_id) {
+ while (ITM_PORT31_U32 == 0U);
+ ITM_PORT31_U8 = (U8)task_id;
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM0.s b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM0.s
new file mode 100644
index 0000000..b83397c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM0.s
@@ -0,0 +1,312 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM0.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M0
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ NAME HAL_CM0.S
+
+ #define TCB_TSTACK 40
+
+ EXTERN os_flags
+ EXTERN os_tsk
+ EXTERN rt_alloc_box
+ EXTERN rt_free_box
+ EXTERN rt_stk_check
+ EXTERN rt_pop_req
+ EXTERN rt_systick
+ EXTERN os_tick_irqack
+ EXTERN SVC_Table
+ EXTERN SVC_Count
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+; void rt_set_PSP (U32 stack);
+
+ PUBLIC rt_set_PSP
+rt_set_PSP:
+
+ MSR PSP,R0
+ BX LR
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+; U32 rt_get_PSP (void);
+
+ PUBLIC rt_get_PSP
+rt_get_PSP:
+
+ MRS R0,PSP
+ BX LR
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+; void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ PUBLIC os_set_env
+os_set_env:
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ BNE PrivilegedE
+ MOVS R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+PrivilegedE:
+ MOVS R0,#0x02 /* Privileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+; void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _alloc_box
+_alloc_box:
+
+ LDR R3,=rt_alloc_box
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedA
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedA
+ SVC 0
+ BX LR
+PrivilegedA:
+ BX R12
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+; U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _free_box
+_free_box:
+
+ LDR R3,=rt_free_box
+ MOV R12,R3
+ MRS R3,IPSR
+ LSLS R3,#24
+ BNE PrivilegedF
+ MRS R3,CONTROL
+ LSLS R3,#31
+ BEQ PrivilegedF
+ SVC 0
+ BX LR
+PrivilegedF:
+ BX R12
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+; void SVC_Handler (void);
+
+ PUBLIC SVC_Handler
+SVC_Handler:
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ SUBS R1,R1,#2 /* Point to SVC Instruction */
+ LDRB R1,[R1] /* Load SVC Number */
+ CMP R1,#0
+ BNE SVC_User /* User SVC Number > 0 */
+
+ MOV LR,R4
+ LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */
+ MOV R12,R4
+ MOV R4,LR
+ BLX R12 /* Call SVC Function */
+
+ MRS R3,PSP /* Read PSP */
+ STMIA R3!,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ SVC_Exit /* no task switch */
+
+ SUBS R3,#8
+ CMP R1,#0 /* Runtask deleted? */
+ BEQ SVC_Next
+
+ MRS R0,PSP /* Read PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+ STMIA R0!,{R4-R7} /* Save old context (R4-R7) */
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} /* Save old context (R8-R11) */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_Next:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ ADDS R0,R0,#16 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 /* Write PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */
+
+SVC_Exit:
+ MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */
+ MVNS R0,R0
+ BX R0 /* RETI to Thread Mode, use PSP */
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LSLS R1,R1,#2
+ LDR R4,[R4,R1] /* Load SVC Function Address */
+ MOV LR,R4
+
+ LDMIA R0,{R0-R3,R4} /* Read R0-R3,R12 from stack */
+ MOV R12,R4
+ BLX LR /* Call SVC Function */
+
+ MRS R4,PSP /* Read PSP */
+ STMIA R4!,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+; void PendSV_Handler (void);
+
+ PUBLIC PendSV_Handler
+PendSV_Handler:
+
+ BL rt_pop_req
+
+Sys_Switch:
+ LDR R3,=os_tsk
+ LDMIA R3!,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ Sys_Exit /* no task switch */
+
+ SUBS R3,#8
+
+ MRS R0,PSP /* Read PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ STR R0,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+ STMIA R0!,{R4-R7} /* Save old context (R4-R7) */
+ MOV R4,R8
+ MOV R5,R9
+ MOV R6,R10
+ MOV R7,R11
+ STMIA R0!,{R4-R7} /* Save old context (R8-R11) */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R0,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ ADDS R0,R0,#16 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R8-R11) */
+ MOV R8,R4
+ MOV R9,R5
+ MOV R10,R6
+ MOV R11,R7
+ MSR PSP,R0 /* Write PSP */
+ SUBS R0,R0,#32 /* Adjust Start Address */
+ LDMIA R0!,{R4-R7} /* Restore new Context (R4-R7) */
+
+Sys_Exit:
+ MOVS R0,#~0xFFFFFFFD /* Set EXC_RETURN value */
+ MVNS R0,R0
+ BX R0 /* RETI to Thread Mode, use PSP */
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+; void SysTick_Handler (void);
+
+ PUBLIC SysTick_Handler
+SysTick_Handler:
+
+ BL rt_systick
+ B Sys_Switch
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+; void OS_Tick_Handler (void);
+
+ PUBLIC OS_Tick_Handler
+OS_Tick_Handler:
+
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+
+ END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM3.s b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM3.s
new file mode 100644
index 0000000..b67a21d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM3.s
@@ -0,0 +1,265 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM3.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M3
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ NAME HAL_CM3.S
+
+ #define TCB_TSTACK 40
+
+ EXTERN os_flags
+ EXTERN os_tsk
+ EXTERN rt_alloc_box
+ EXTERN rt_free_box
+ EXTERN rt_stk_check
+ EXTERN rt_pop_req
+ EXTERN rt_systick
+ EXTERN os_tick_irqack
+ EXTERN SVC_Table
+ EXTERN SVC_Count
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+; void rt_set_PSP (U32 stack);
+
+ PUBLIC rt_set_PSP
+rt_set_PSP:
+
+ MSR PSP,R0
+ BX LR
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+; U32 rt_get_PSP (void);
+
+ PUBLIC rt_get_PSP
+rt_get_PSP:
+
+ MRS R0,PSP
+ BX LR
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+; void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ PUBLIC os_set_env
+os_set_env:
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ ITE NE
+ MOVNE R0,#0x02 /* Privileged Thread mode, use PSP */
+ MOVEQ R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+; void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _alloc_box
+_alloc_box:
+
+ LDR R12,=rt_alloc_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+; U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _free_box
+_free_box:
+
+ LDR R12,=rt_free_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+; void SVC_Handler (void);
+
+ PUBLIC SVC_Handler
+SVC_Handler:
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ LDRB R1,[R1,#-2] /* Load SVC Number */
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R12 /* Call SVC Function */
+
+ MRS R12,PSP /* Read PSP */
+ STM R12,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ SVC_Exit /* no task switch */
+
+ CBZ R1,SVC_Next /* Runtask deleted? */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_Next:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ MSR PSP,R12 /* Write PSP */
+
+SVC_Exit:
+ MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ BX LR
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] /* Load SVC Function Address */
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R4 /* Call SVC Function */
+
+ MRS R12,PSP
+ STM R12,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+; void PendSV_Handler (void);
+
+ PUBLIC PendSV_Handler
+PendSV_Handler:
+
+ BL rt_pop_req
+
+Sys_Switch:
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ BEQ Sys_Exit
+
+ MRS R12,PSP /* Read PSP */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ MSR PSP,R12 /* Write PSP */
+
+Sys_Exit:
+ MVN LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ BX LR /* Return to Thread Mode */
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+; void SysTick_Handler (void);
+
+ PUBLIC SysTick_Handler
+SysTick_Handler:
+
+ BL rt_systick
+ B Sys_Switch
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+; void OS_Tick_Handler (void);
+
+ PUBLIC OS_Tick_Handler
+OS_Tick_Handler:
+
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+
+ END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM4.s b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM4.s
new file mode 100644
index 0000000..9c8288f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/HAL_CM4.s
@@ -0,0 +1,307 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: HAL_CM4.S
+ * Purpose: Hardware Abstraction Layer for Cortex-M4
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+ NAME HAL_CM4.S
+
+ #define TCB_STACKF 37
+ #define TCB_TSTACK 40
+
+ EXTERN os_flags
+ EXTERN os_tsk
+ EXTERN rt_alloc_box
+ EXTERN rt_free_box
+ EXTERN rt_stk_check
+ EXTERN rt_pop_req
+ EXTERN rt_systick
+ EXTERN os_tick_irqack
+ EXTERN SVC_Table
+ EXTERN SVC_Count
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+ SECTION .text:CODE:NOROOT(2)
+ THUMB
+
+/*--------------------------- rt_set_PSP ------------------------------------*/
+
+; void rt_set_PSP (U32 stack);
+
+ PUBLIC rt_set_PSP
+rt_set_PSP:
+
+ MSR PSP,R0
+ BX LR
+
+
+/*--------------------------- rt_get_PSP ------------------------------------*/
+
+; U32 rt_get_PSP (void);
+
+ PUBLIC rt_get_PSP
+rt_get_PSP:
+
+ MRS R0,PSP
+ BX LR
+
+
+/*--------------------------- os_set_env ------------------------------------*/
+
+; void os_set_env (void);
+ /* Switch to Unprivileged/Privileged Thread mode, use PSP. */
+
+ PUBLIC os_set_env
+os_set_env:
+
+ MOV R0,SP /* PSP = MSP */
+ MSR PSP,R0
+ LDR R0,=os_flags
+ LDRB R0,[R0]
+ LSLS R0,#31
+ ITE NE
+ MOVNE R0,#0x02 /* Privileged Thread mode, use PSP */
+ MOVEQ R0,#0x03 /* Unprivileged Thread mode, use PSP */
+ MSR CONTROL,R0
+ BX LR
+
+
+/*--------------------------- _alloc_box ------------------------------------*/
+
+; void *_alloc_box (void *box_mem);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _alloc_box
+_alloc_box:
+
+ LDR R12,=rt_alloc_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+
+/*--------------------------- _free_box -------------------------------------*/
+
+; U32 _free_box (void *box_mem, void *box);
+ /* Function wrapper for Unprivileged/Privileged mode. */
+
+ PUBLIC _free_box
+_free_box:
+
+ LDR R12,=rt_free_box
+ MRS R3,IPSR
+ LSLS R3,#24
+ IT NE
+ BXNE R12
+ MRS R3,CONTROL
+ LSLS R3,#31
+ IT EQ
+ BXEQ R12
+ SVC 0
+ BX LR
+
+
+/*-------------------------- SVC_Handler ------------------------------------*/
+
+; void SVC_Handler (void);
+
+ PUBLIC SVC_Handler
+SVC_Handler:
+
+ MRS R0,PSP /* Read PSP */
+ LDR R1,[R0,#24] /* Read Saved PC from Stack */
+ LDRB R1,[R1,#-2] /* Load SVC Number */
+ CBNZ R1,SVC_User
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BLX R12 /* Call SVC Function */
+ POP {R4,LR} /* Restore EXC_RETURN */
+
+ MRS R12,PSP /* Read PSP */
+ STM R12,{R0-R2} /* Store return values */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ IT EQ
+ BXEQ LR /* RETI, no task switch */
+
+ CBNZ R1,SVC_ContextSave /* Runtask not deleted? */
+
+ TST LR,#0x10 /* is it extended frame? */
+ BNE SVC_ContextRestore
+ LDR R1,=0xE000EF34
+ LDR R0,[R1] /* Load FPCCR */
+ BIC R0,R0,#1 /* Clear LSPACT (Lazy state) */
+ STR R0,[R1] /* Store FPCCR */
+ B SVC_ContextRestore
+
+SVC_ContextSave:
+ TST LR,#0x10 /* is it extended frame? */
+ ITTE EQ
+ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
+ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+SVC_ContextRestore:
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
+ CMP R0,#0 /* Basic/Extended Stack Frame */
+ ITEE EQ
+ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ MVNNE LR,#~0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
+ MSR PSP,R12 /* Write PSP */
+
+SVC_Exit:
+ BX LR
+
+ /*------------------- User SVC ------------------------------*/
+
+SVC_User:
+ PUSH {R4,LR} /* Save Registers */
+ LDR R2,=SVC_Count
+ LDR R2,[R2]
+ CMP R1,R2
+ BHI SVC_Done /* Overflow */
+
+ LDR R4,=SVC_Table-4
+ LDR R4,[R4,R1,LSL #2] /* Load SVC Function Address */
+
+ LDM R0,{R0-R3,R12} /* Read R0-R3,R12 from stack */
+ BLX R4 /* Call SVC Function */
+
+ MRS R12,PSP
+ STM R12,{R0-R3} /* Function return values */
+SVC_Done:
+ POP {R4,PC} /* RETI */
+
+
+/*-------------------------- PendSV_Handler ---------------------------------*/
+
+; void PendSV_Handler (void);
+
+ PUBLIC PendSV_Handler
+PendSV_Handler:
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL rt_pop_req
+
+Sys_Switch:
+ POP {R4,LR} /* Restore EXC_RETURN */
+
+ LDR R3,=os_tsk
+ LDM R3,{R1,R2} /* os_tsk.run, os_tsk.new */
+ CMP R1,R2
+ IT EQ
+ BXEQ LR /* RETI, no task switch */
+
+ MRS R12,PSP /* Read PSP */
+ TST LR,#0x10 /* is it extended frame? */
+ ITTE EQ
+ VSTMDBEQ R12!,{S16-S31} /* yes, stack also VFP hi-regs */
+ MOVEQ R0,#0x01 /* os_tsk->stack_frame val */
+ MOVNE R0,#0x00
+ STRB R0,[R1,#TCB_STACKF] /* os_tsk.run->stack_frame = val */
+ STMDB R12!,{R4-R11} /* Save Old context */
+ STR R12,[R1,#TCB_TSTACK] /* Update os_tsk.run->tsk_stack */
+
+ PUSH {R2,R3}
+ BL rt_stk_check /* Check for Stack overflow */
+ POP {R2,R3}
+
+ STR R2,[R3] /* os_tsk.run = os_tsk.new */
+
+ LDR R12,[R2,#TCB_TSTACK] /* os_tsk.new->tsk_stack */
+ LDMIA R12!,{R4-R11} /* Restore New Context */
+ LDRB R0,[R2,#TCB_STACKF] /* Stack Frame */
+ CMP R0,#0 /* Basic/Extended Stack Frame */
+ ITEE EQ
+ MVNEQ LR,#~0xFFFFFFFD /* set EXC_RETURN value */
+ MVNNE LR,#~0xFFFFFFED
+ VLDMIANE R12!,{S16-S31} /* restore VFP hi-registers */
+ MSR PSP,R12 /* Write PSP */
+
+Sys_Exit:
+ BX LR /* Return to Thread Mode */
+
+
+/*-------------------------- SysTick_Handler --------------------------------*/
+
+; void SysTick_Handler (void);
+
+ PUBLIC SysTick_Handler
+SysTick_Handler:
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL rt_systick
+ B Sys_Switch
+
+
+/*-------------------------- OS_Tick_Handler --------------------------------*/
+
+; void OS_Tick_Handler (void);
+
+ PUBLIC OS_Tick_Handler
+OS_Tick_Handler:
+
+ PUSH {R4,LR} /* Save EXC_RETURN */
+ BL os_tick_irqack
+ BL rt_systick
+ B Sys_Switch
+
+
+ END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.ewp b/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.ewp
new file mode 100644
index 0000000..e002f64
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.ewp
@@ -0,0 +1,7039 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>2</fileVersion>
+ <configuration>
+ <name>CM0_LE</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>0</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>ExePath</name>
+ <state>CM0_LE</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>CM0_LE</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>CM0_LE</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>20</version>
+ <state>34</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>To be used with the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.40.5.54273</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
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+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
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+ <name>GeneralMisraVer</name>
+ <state>0</state>
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+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
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+ <name>GFPUCoreSlave</name>
+ <version>20</version>
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+ </option>
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+ <name>GBECoreSlave</name>
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+ <name>OGUseCmsis</name>
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+ <name>OGUseCmsisDspLib</name>
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+ </settings>
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+ <state>0</state>
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+ <name>IccCppDialect</name>
+ <state>1</state>
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+ <name>IccExceptions</name>
+ <state>1</state>
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+ <name>IccRTTI</name>
+ <state>1</state>
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+ <state>0</state>
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+ <name>IccCmsis</name>
+ <state>1</state>
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+ <name>IccFloatSemantics</name>
+ <state>0</state>
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+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
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+ <name>AWarnOne</name>
+ <state></state>
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+ <name>AWarnRange1</name>
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+ <name>AWarnRange2</name>
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+ <name>ADebug</name>
+ <state>1</state>
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+ <option>
+ <name>AltRegisterNames</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state>__CMSIS_RTOS</state>
+ </option>
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+ <name>AList</name>
+ <state>0</state>
+ </option>
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+ <name>AListHeader</name>
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+ <name>MacExps</name>
+ <state>1</state>
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+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
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+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
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+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
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+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
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+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
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+ <option>
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+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
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+ <name>CCPosIndRwpi</name>
+ <state>0</state>
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+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
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+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
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+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
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+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
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+ <option>
+ <name>IccCppInlineSemantics</name>
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+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>CM3_LE</name>
+ <settings>
+ <name>ICCARM</name>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>__CORTEX_M3</state>
+ <state>__CMSIS_RTOS</state>
+ <state>DBG_MSG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
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+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCFile</name>
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+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
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+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
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+ <option>
+ <name>CCListAssSource</name>
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+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
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+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
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+ <name>CCDiagRemark</name>
+ <state></state>
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+ <name>CCDiagWarning</name>
+ <state></state>
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+ <name>CCDiagError</name>
+ <state></state>
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+ <name>CCObjPrefix</name>
+ <state>1</state>
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+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
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+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
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+ </option>
+ <option>
+ <name>IFpuProcessor</name>
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+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
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+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
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+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
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+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
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+ <name>IInterwork2</name>
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+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
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+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
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+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
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+ <version>0</version>
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+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
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+ <name>IccCDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
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+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
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+ <name>IccExceptions</name>
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+ <name>IccRTTI</name>
+ <state>1</state>
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+ <name>IccStaticDestr</name>
+ <state>1</state>
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+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
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+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>CM3_BE</name>
+ <settings>
+ <name>ICCARM</name>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>__CORTEX_M3</state>
+ <state>__CMSIS_RTOS</state>
+ <state>DBG_MSG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
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+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
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+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCFile</name>
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+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
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+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
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+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
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+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
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+ <name>CCDiagRemark</name>
+ <state></state>
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+ <name>CCDiagWarning</name>
+ <state></state>
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+ <name>CCDiagError</name>
+ <state></state>
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+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
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+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
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+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
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+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
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+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
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+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
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+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
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+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
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+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
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+ <option>
+ <name>CCMultibyteSupport</name>
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+ <name>CCDiagWarnAreErr</name>
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+ <option>
+ <name>CCCompilerRuntimeInfo</name>
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+ <option>
+ <name>IFpuProcessor</name>
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+ <option>
+ <name>OutputFile</name>
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+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
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+ <option>
+ <name>PreInclude</name>
+ <state></state>
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+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
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+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
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+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
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+ <name>CCCodeSection</name>
+ <state>.text</state>
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+ <name>IInterwork2</name>
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+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
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+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
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+ <name>CCOptStrategy</name>
+ <version>0</version>
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+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
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+ <version>0</version>
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+ <name>CCPosIndRwpi</name>
+ <state>0</state>
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+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
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+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
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+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
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+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
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+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
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+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
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+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>CM4F_LE</name>
+ <settings>
+ <name>ICCARM</name>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
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+ <option>
+ <name>CCDefines</name>
+ <state>__CORTEX_M4F</state>
+ <state>__CMSIS_RTOS</state>
+ <state>DBG_MSG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
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+ <name>CCPreprocComments</name>
+ <state>0</state>
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+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCFile</name>
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+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
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+ <option>
+ <name>CCListCMessages</name>
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+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
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+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
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+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
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+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
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+ <name>CCDiagRemark</name>
+ <state></state>
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+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
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+ <name>CCDiagError</name>
+ <state></state>
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+ <name>CCObjPrefix</name>
+ <state>1</state>
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+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
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+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
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+ <state>1</state>
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+ <name>IProcessor</name>
+ <state>1</state>
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+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
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+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
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+ <name>CCLangConformance</name>
+ <state>0</state>
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+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
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+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
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+ <name>CCDiagWarnAreErr</name>
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+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
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+ <name>IFpuProcessor</name>
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+ <name>OutputFile</name>
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+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
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+ <option>
+ <name>PreInclude</name>
+ <state></state>
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+ <name>CompilerMisraOverride</name>
+ <state>0</state>
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+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
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+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
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+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
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+ <name>IInterwork2</name>
+ <state>0</state>
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+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
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+ <option>
+ <name>CCOptLevel</name>
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+ <name>CCOptStrategy</name>
+ <version>0</version>
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+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
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+ <version>0</version>
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+ <name>CCPosIndRwpi</name>
+ <state>0</state>
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+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ </configuration>
+ <configuration>
+ <name>CM4F_BE</name>
+ <settings>
+ <name>ICCARM</name>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>CCOptimizationNoSizeConstraints</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDefines</name>
+ <state>__CORTEX_M4F</state>
+ <state>__CMSIS_RTOS</state>
+ <state>DBG_MSG</state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>3</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ </configuration>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Event.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_List.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Mailbox.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_MemBox.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Memory.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Mutex.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Robin.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Semaphore.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_System.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Task.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Time.c</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\rt_Timer.c</name>
+ </file>
+ </group>
+</project>
+
+
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.eww b/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.eww
new file mode 100644
index 0000000..da55aab
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/RTX_Lib_CM.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\RTX_Lib_CM.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s b/CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s
new file mode 100644
index 0000000..82bcd17
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/IAR/SVC_Table.s
@@ -0,0 +1,58 @@
+;/*----------------------------------------------------------------------------
+; * CMSIS-RTOS - RTX
+; *----------------------------------------------------------------------------
+; * Name: SVC_TABLE.S
+; * Purpose: Pre-defined SVC Table for Cortex-M
+; * Rev.: V4.70
+; *----------------------------------------------------------------------------
+; *
+; * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+; * All rights reserved.
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; * - Redistributions of source code must retain the above copyright
+; * notice, this list of conditions and the following disclaimer.
+; * - Redistributions in binary form must reproduce the above copyright
+; * notice, this list of conditions and the following disclaimer in the
+; * documentation and/or other materials provided with the distribution.
+; * - Neither the name of ARM nor the names of its contributors may be used
+; * to endorse or promote products derived from this software without
+; * specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; * POSSIBILITY OF SUCH DAMAGE.
+; *---------------------------------------------------------------------------*/
+
+
+ NAME SVC_TABLE
+ SECTION .text:CONST (2)
+
+ PUBLIC SVC_Count
+
+SVC_Cnt EQU (SVC_End-SVC_Table)/4
+SVC_Count DCD SVC_Cnt
+
+; Import user SVC functions here.
+; IMPORT __SVC_1
+
+ PUBLIC SVC_Table
+SVC_Table
+; Insert user SVC functions here. SVC 0 used by RTL Kernel.
+; DCD __SVC_1 ; user SVC function
+
+SVC_End
+
+ END
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/RTX_Config.h b/CMSIS/RTOS/RTX/SRC/RTX_Config.h
new file mode 100644
index 0000000..151ca38
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/RTX_Config.h
@@ -0,0 +1,80 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RTX_CONFIG.H
+ * Purpose: Exported functions of RTX_Config.c
+ * Rev.: V4.81
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include <stdint.h>
+
+/* Error Codes */
+#define OS_ERR_STK_OVF 1U
+#define OS_ERR_FIFO_OVF 2U
+#define OS_ERR_MBX_OVF 3U
+#define OS_ERR_TIMER_OVF 4U
+
+/* Definitions */
+#define BOX_ALIGN_8 0x80000000U
+#define _declare_box(pool,size,cnt) U32 pool[(((size)+3)/4)*(cnt) + 3]
+#define _declare_box8(pool,size,cnt) U64 pool[(((size)+7)/8)*(cnt) + 2]
+#define _init_box8(pool,size,bsize) _init_box (pool,size,(bsize) | BOX_ALIGN_8)
+
+/* Variables */
+extern U32 mp_tcb[];
+extern U64 mp_stk[];
+extern U32 os_fifo[];
+extern void *os_active_TCB[];
+
+/* Constants */
+extern U16 const os_maxtaskrun;
+extern U32 const os_trv;
+extern U8 const os_flags;
+extern U32 const os_stackinfo;
+extern U32 const os_rrobin;
+extern U32 const os_clockrate;
+extern U32 const os_timernum;
+extern U16 const mp_tcb_size;
+extern U32 const mp_stk_size;
+extern U32 const *m_tmr;
+extern U16 const mp_tmr_size;
+extern U8 const os_fifo_size;
+
+/* Functions */
+extern void os_idle_demon (void);
+extern S32 os_tick_init (void);
+extern U32 os_tick_val (void);
+extern U32 os_tick_ovf (void);
+extern void os_tick_irqack (void);
+extern void os_tmr_call (U16 info);
+extern void os_error (uint32_t err_code);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_CMSIS.c b/CMSIS/RTOS/RTX/SRC/rt_CMSIS.c
new file mode 100644
index 0000000..173913c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_CMSIS.c
@@ -0,0 +1,2186 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: rt_CMSIS.c
+ * Purpose: CMSIS RTOS API
+ * Rev.: V4.80
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#define __CMSIS_GENERIC
+
+#if defined (__CORTEX_M4) || defined (__CORTEX_M4F)
+ #include "core_cm4.h"
+#elif defined (__CORTEX_M3)
+ #include "core_cm3.h"
+#elif defined (__CORTEX_M0)
+ #include "core_cm0.h"
+#else
+ #error "Missing __CORTEX_Mx definition"
+#endif
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Time.h"
+#include "rt_Mutex.h"
+#include "rt_Semaphore.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_Memory.h"
+#include "rt_HAL_CM.h"
+
+#define os_thread_cb OS_TCB
+
+#include "cmsis_os.h"
+
+#if (osFeature_Signals != 16)
+#error Invalid "osFeature_Signals" value!
+#endif
+#if (osFeature_Semaphore > 65535)
+#error Invalid "osFeature_Semaphore" value!
+#endif
+#if (osFeature_Wait != 0)
+#error osWait not supported!
+#endif
+
+
+// ==== Enumeration, structures, defines ====
+
+// Service Calls defines
+
+#if defined (__CC_ARM) /* ARM Compiler */
+
+#define __NO_RETURN __declspec(noreturn)
+
+#define osEvent_type osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value ret
+#define osEvent_ret_msg ret
+#define osEvent_ret_mail ret
+
+#define osCallback_type osCallback
+#define osCallback_ret ret
+
+#define SVC_0_1(f,t,...) \
+__svc_indirect(0) t _##f (t(*)()); \
+ t f (void); \
+__attribute__((always_inline)) \
+static __inline t __##f (void) { \
+ return _##f(f); \
+}
+
+#define SVC_1_0(f,t,t1,...) \
+__svc_indirect(0) t _##f (t(*)(t1),t1); \
+ t f (t1 a1); \
+__attribute__((always_inline)) \
+static __inline t __##f (t1 a1) { \
+ _##f(f,a1); \
+}
+
+#define SVC_1_1(f,t,t1,...) \
+__svc_indirect(0) t _##f (t(*)(t1),t1); \
+ t f (t1 a1); \
+__attribute__((always_inline)) \
+static __inline t __##f (t1 a1) { \
+ return _##f(f,a1); \
+}
+
+#define SVC_2_1(f,t,t1,t2,...) \
+__svc_indirect(0) t _##f (t(*)(t1,t2),t1,t2); \
+ t f (t1 a1, t2 a2); \
+__attribute__((always_inline)) \
+static __inline t __##f (t1 a1, t2 a2) { \
+ return _##f(f,a1,a2); \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...) \
+__svc_indirect(0) t _##f (t(*)(t1,t2,t3),t1,t2,t3); \
+ t f (t1 a1, t2 a2, t3 a3); \
+__attribute__((always_inline)) \
+static __inline t __##f (t1 a1, t2 a2, t3 a3) { \
+ return _##f(f,a1,a2,a3); \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...) \
+__svc_indirect(0) t _##f (t(*)(t1,t2,t3,t4),t1,t2,t3,t4); \
+ t f (t1 a1, t2 a2, t3 a3, t4 a4); \
+__attribute__((always_inline)) \
+static __inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
+ return _##f(f,a1,a2,a3,a4); \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__GNUC__) /* GNU Compiler */
+
+#define __NO_RETURN __attribute__((noreturn))
+
+typedef uint32_t __attribute__((vector_size(8))) ret64;
+typedef uint32_t __attribute__((vector_size(16))) ret128;
+
+#define RET_pointer __r0
+#define RET_int32_t __r0
+#define RET_uint32_t __r0
+#define RET_osStatus __r0
+#define RET_osPriority __r0
+#define RET_osEvent {(osStatus)__r0, {(uint32_t)__r1}, {(void *)__r2}}
+#define RET_osCallback {(void *)__r0, (void *)__r1}
+
+#define osEvent_type __attribute__((pcs("aapcs"))) ret128
+#define osEvent_ret_status (ret128){ret.status}
+#define osEvent_ret_value (ret128){ret.status, ret.value.v}
+#define osEvent_ret_msg (ret128){ret.status, ret.value.v, (uint32_t)ret.def.message_id}
+#define osEvent_ret_mail (ret128){ret.status, ret.value.v, (uint32_t)ret.def.mail_id}
+
+#define osCallback_type __attribute__((pcs("aapcs"))) ret64
+#define osCallback_ret (ret64) {(uint32_t)ret.fp, (uint32_t)ret.arg}
+
+#define SVC_ArgN(n) \
+ register int __r##n __asm("r"#n);
+
+#define SVC_ArgR(n,t,a) \
+ register t __r##n __asm("r"#n) = a;
+
+#define SVC_Arg0() \
+ SVC_ArgN(0) \
+ SVC_ArgN(1) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Arg1(t1) \
+ SVC_ArgR(0,t1,a1) \
+ SVC_ArgN(1) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Arg2(t1,t2) \
+ SVC_ArgR(0,t1,a1) \
+ SVC_ArgR(1,t2,a2) \
+ SVC_ArgN(2) \
+ SVC_ArgN(3)
+
+#define SVC_Arg3(t1,t2,t3) \
+ SVC_ArgR(0,t1,a1) \
+ SVC_ArgR(1,t2,a2) \
+ SVC_ArgR(2,t3,a3) \
+ SVC_ArgN(3)
+
+#define SVC_Arg4(t1,t2,t3,t4) \
+ SVC_ArgR(0,t1,a1) \
+ SVC_ArgR(1,t2,a2) \
+ SVC_ArgR(2,t3,a3) \
+ SVC_ArgR(3,t4,a4)
+
+#if (defined (__CORTEX_M0))
+#define SVC_Call(f) \
+ __asm volatile \
+ ( \
+ "ldr r7,="#f"\n\t" \
+ "mov r12,r7\n\t" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r7", "r12", "lr", "cc" \
+ );
+#else
+#define SVC_Call(f) \
+ __asm volatile \
+ ( \
+ "ldr r12,="#f"\n\t" \
+ "svc 0" \
+ : "=r" (__r0), "=r" (__r1), "=r" (__r2), "=r" (__r3) \
+ : "r" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) \
+ : "r12", "lr", "cc" \
+ );
+#endif
+
+#define SVC_0_1(f,t,rv) \
+__attribute__((always_inline)) \
+static inline t __##f (void) { \
+ SVC_Arg0(); \
+ SVC_Call(f); \
+ return (t) rv; \
+}
+
+#define SVC_1_0(f,t,t1) \
+__attribute__((always_inline)) \
+static inline t __##f (t1 a1) { \
+ SVC_Arg1(t1); \
+ SVC_Call(f); \
+}
+
+#define SVC_1_1(f,t,t1,rv) \
+__attribute__((always_inline)) \
+static inline t __##f (t1 a1) { \
+ SVC_Arg1(t1); \
+ SVC_Call(f); \
+ return (t) rv; \
+}
+
+#define SVC_2_1(f,t,t1,t2,rv) \
+__attribute__((always_inline)) \
+static inline t __##f (t1 a1, t2 a2) { \
+ SVC_Arg2(t1,t2); \
+ SVC_Call(f); \
+ return (t) rv; \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,rv) \
+__attribute__((always_inline)) \
+static inline t __##f (t1 a1, t2 a2, t3 a3) { \
+ SVC_Arg3(t1,t2,t3); \
+ SVC_Call(f); \
+ return (t) rv; \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,rv) \
+__attribute__((always_inline)) \
+static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
+ SVC_Arg4(t1,t2,t3,t4); \
+ SVC_Call(f); \
+ return (t) rv; \
+}
+
+#define SVC_1_2 SVC_1_1
+#define SVC_1_3 SVC_1_1
+#define SVC_2_3 SVC_2_1
+
+#elif defined (__ICCARM__) /* IAR Compiler */
+
+#define __NO_RETURN __noreturn
+
+#define RET_osEvent "=r"(ret.status), "=r"(ret.value), "=r"(ret.def)
+#define RET_osCallback "=r"(ret.fp), "=r"(ret.arg)
+
+#define osEvent_type osEvent
+#define osEvent_ret_status ret
+#define osEvent_ret_value ret
+#define osEvent_ret_msg ret
+#define osEvent_ret_mail ret
+
+#define osCallback_type uint64_t
+#define osCallback_ret ((uint64_t)ret.fp | ((uint64_t)ret.arg)<<32)
+
+#define SVC_Setup(f) \
+ __asm( \
+ "mov r12,%0\n" \
+ :: "r"(&f): "r12" \
+ );
+
+#define SVC_Ret3() \
+ __asm( \
+ "ldr r0,[sp,#0]\n" \
+ "ldr r1,[sp,#4]\n" \
+ "ldr r2,[sp,#8]\n" \
+ );
+
+#define SVC_0_1(f,t,...) \
+t f (void); \
+_Pragma("swi_number=0") __swi t _##f (void); \
+static inline t __##f (void) { \
+ SVC_Setup(f); \
+ return _##f(); \
+}
+
+#define SVC_1_0(f,t,t1,...) \
+t f (t1 a1); \
+_Pragma("swi_number=0") __swi t _##f (t1 a1); \
+static inline t __##f (t1 a1) { \
+ SVC_Setup(f); \
+ _##f(a1); \
+}
+
+#define SVC_1_1(f,t,t1,...) \
+t f (t1 a1); \
+_Pragma("swi_number=0") __swi t _##f (t1 a1); \
+static inline t __##f (t1 a1) { \
+ SVC_Setup(f); \
+ return _##f(a1); \
+}
+
+#define SVC_2_1(f,t,t1,t2,...) \
+t f (t1 a1, t2 a2); \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2); \
+static inline t __##f (t1 a1, t2 a2) { \
+ SVC_Setup(f); \
+ return _##f(a1,a2); \
+}
+
+#define SVC_3_1(f,t,t1,t2,t3,...) \
+t f (t1 a1, t2 a2, t3 a3); \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3); \
+static inline t __##f (t1 a1, t2 a2, t3 a3) { \
+ SVC_Setup(f); \
+ return _##f(a1,a2,a3); \
+}
+
+#define SVC_4_1(f,t,t1,t2,t3,t4,...) \
+t f (t1 a1, t2 a2, t3 a3, t4 a4); \
+_Pragma("swi_number=0") __swi t _##f (t1 a1, t2 a2, t3 a3, t4 a4); \
+static inline t __##f (t1 a1, t2 a2, t3 a3, t4 a4) { \
+ SVC_Setup(f); \
+ return _##f(a1,a2,a3,a4); \
+}
+
+#define SVC_1_2(f,t,t1,rr) \
+uint64_t f (t1 a1); \
+_Pragma("swi_number=0") __swi uint64_t _##f (t1 a1); \
+static inline t __##f (t1 a1) { \
+ t ret; \
+ SVC_Setup(f); \
+ _##f(a1); \
+ __asm("" : rr : :); \
+ return ret; \
+}
+
+#define SVC_1_3(f,t,t1,rr) \
+t f (t1 a1); \
+void f##_ (t1 a1) { \
+ f(a1); \
+ SVC_Ret3(); \
+} \
+_Pragma("swi_number=0") __swi void _##f (t1 a1); \
+static inline t __##f (t1 a1) { \
+ t ret; \
+ SVC_Setup(f##_); \
+ _##f(a1); \
+ __asm("" : rr : :); \
+ return ret; \
+}
+
+#define SVC_2_3(f,t,t1,t2,rr) \
+t f (t1 a1, t2 a2); \
+void f##_ (t1 a1, t2 a2) { \
+ f(a1,a2); \
+ SVC_Ret3(); \
+} \
+_Pragma("swi_number=0") __swi void _##f (t1 a1, t2 a2); \
+static inline t __##f (t1 a1, t2 a2) { \
+ t ret; \
+ SVC_Setup(f##_); \
+ _##f(a1,a2); \
+ __asm("" : rr : :); \
+ return ret; \
+}
+
+#endif
+
+
+// Callback structure
+typedef struct {
+ void *fp; // Function pointer
+ void *arg; // Function argument
+} osCallback;
+
+
+// OS Section definitions
+#ifdef OS_SECTIONS_LINK_INFO
+extern const uint32_t os_section_id$$Base;
+extern const uint32_t os_section_id$$Limit;
+#endif
+
+// OS Stack Memory for Threads definitions
+extern uint64_t os_stack_mem[];
+extern const uint32_t os_stack_sz;
+
+// OS Timers external resources
+extern const osThreadDef_t os_thread_def_osTimerThread;
+extern osThreadId osThreadId_osTimerThread;
+extern const osMessageQDef_t os_messageQ_def_osTimerMessageQ;
+extern osMessageQId osMessageQId_osTimerMessageQ;
+
+
+// ==== Helper Functions ====
+
+/// Convert timeout in millisec to system ticks
+static uint16_t rt_ms2tick (uint32_t millisec) {
+ uint32_t tick;
+
+ if (millisec == 0U) { return 0x0U; } // No timeout
+ if (millisec == osWaitForever) { return 0xFFFFU; } // Indefinite timeout
+ if (millisec > 4000000U) { return 0xFFFEU; } // Max ticks supported
+
+ tick = ((1000U * millisec) + os_clockrate - 1U) / os_clockrate;
+ if (tick > 0xFFFEU) { return 0xFFFEU; }
+
+ return (uint16_t)tick;
+}
+
+/// Convert Thread ID to TCB pointer
+static P_TCB rt_tid2ptcb (osThreadId thread_id) {
+ P_TCB ptcb;
+
+ if (thread_id == NULL) { return NULL; }
+
+ if ((uint32_t)thread_id & 3U) { return NULL; }
+
+#ifdef OS_SECTIONS_LINK_INFO
+ if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {
+ if (thread_id < (osThreadId)os_section_id$$Base) { return NULL; }
+ if (thread_id >= (osThreadId)os_section_id$$Limit) { return NULL; }
+ }
+#endif
+
+ ptcb = thread_id;
+
+ if (ptcb->cb_type != TCB) { return NULL; }
+
+ return ptcb;
+}
+
+/// Convert ID pointer to Object pointer
+static void *rt_id2obj (void *id) {
+
+ if ((uint32_t)id & 3U) { return NULL; }
+
+#ifdef OS_SECTIONS_LINK_INFO
+ if ((os_section_id$$Base != 0U) && (os_section_id$$Limit != 0U)) {
+ if (id < (void *)os_section_id$$Base) { return NULL; }
+ if (id >= (void *)os_section_id$$Limit) { return NULL; }
+ }
+#endif
+
+ return id;
+}
+
+
+// ==== Kernel Control ====
+
+uint8_t os_initialized; // Kernel Initialized flag
+uint8_t os_running; // Kernel Running flag
+
+// Kernel Control Service Calls declarations
+SVC_0_1(svcKernelInitialize, osStatus, RET_osStatus)
+SVC_0_1(svcKernelStart, osStatus, RET_osStatus)
+SVC_0_1(svcKernelRunning, int32_t, RET_int32_t)
+SVC_0_1(svcKernelSysTick, uint32_t, RET_uint32_t)
+
+static void sysThreadError (osStatus status);
+osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument);
+osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
+
+// Kernel Control Service Calls
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus svcKernelInitialize (void) {
+ uint32_t ret;
+
+ if (os_initialized == 0U) {
+
+ // Init Thread Stack Memory (must be 8-byte aligned)
+ if (((uint32_t)os_stack_mem & 7U) != 0U) { return osErrorNoMemory; }
+ ret = rt_init_mem(os_stack_mem, os_stack_sz);
+ if (ret != 0U) { return osErrorNoMemory; }
+
+ rt_sys_init(); // RTX System Initialization
+ }
+
+ os_tsk.run->prio = 255U; // Highest priority
+
+ if (os_initialized == 0U) {
+ // Create OS Timers resources (Message Queue & Thread)
+ osMessageQId_osTimerMessageQ = svcMessageCreate (&os_messageQ_def_osTimerMessageQ, NULL);
+ osThreadId_osTimerThread = svcThreadCreate(&os_thread_def_osTimerThread, NULL);
+ }
+
+ sysThreadError(osOK);
+
+ os_initialized = 1U;
+ os_running = 0U;
+
+ return osOK;
+}
+
+/// Start the RTOS Kernel
+osStatus svcKernelStart (void) {
+
+ if (os_running) { return osOK; }
+
+ rt_tsk_prio(0U, os_tsk.run->prio_base); // Restore priority
+ if (os_tsk.run->task_id == 0xFFU) { // Idle Thread
+ __set_PSP(os_tsk.run->tsk_stack + (8U*4U)); // Setup PSP
+ }
+ if (os_tsk.new == NULL) { // Force context switch
+ os_tsk.new = os_tsk.run;
+ os_tsk.run = NULL;
+ }
+
+ rt_sys_start();
+
+ os_running = 1U;
+
+ return osOK;
+}
+
+/// Check if the RTOS kernel is already started
+int32_t svcKernelRunning (void) {
+ return (int32_t)os_running;
+}
+
+/// Get the RTOS kernel system timer counter
+uint32_t svcKernelSysTick (void) {
+ uint32_t tick, tick0;
+
+ tick = os_tick_val();
+ if (os_tick_ovf()) {
+ tick0 = os_tick_val();
+ if (tick0 < tick) { tick = tick0; }
+ tick += (os_trv + 1U) * (os_time + 1U);
+ } else {
+ tick += (os_trv + 1U) * os_time;
+ }
+
+ return tick;
+}
+
+// Kernel Control Public API
+
+/// Initialize the RTOS Kernel for creating objects
+osStatus osKernelInitialize (void) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ if ((__get_CONTROL() & 1U) == 0U) { // Privileged mode
+ return svcKernelInitialize();
+ } else {
+ return __svcKernelInitialize();
+ }
+}
+
+/// Start the RTOS Kernel
+osStatus osKernelStart (void) {
+ uint32_t stack[8];
+
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ switch (__get_CONTROL() & 0x03U) {
+ case 0x00U: // Privileged Thread mode & MSP
+ __set_PSP((uint32_t)(stack + 8)); // Initial PSP
+ if (os_flags & 1U) {
+ __set_CONTROL(0x02U); // Set Privileged Thread mode & PSP
+ } else {
+ __set_CONTROL(0x03U); // Set Unprivileged Thread mode & PSP
+ }
+ __DSB();
+ __ISB();
+ break;
+ case 0x01U: // Unprivileged Thread mode & MSP
+ return osErrorOS;
+ case 0x02U: // Privileged Thread mode & PSP
+ if ((os_flags & 1U) == 0U) { // Unprivileged Thread mode requested
+ __set_CONTROL(0x03U); // Set Unprivileged Thread mode & PSP
+ __DSB();
+ __ISB();
+ }
+ break;
+ case 0x03U: // Unprivileged Thread mode & PSP
+ if (os_flags & 1U) { return osErrorOS; } // Privileged Thread mode requested
+ break;
+ }
+ return __svcKernelStart();
+}
+
+/// Check if the RTOS kernel is already started
+int32_t osKernelRunning (void) {
+ if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) {
+ // in ISR or Privileged
+ return (int32_t)os_running;
+ } else {
+ return __svcKernelRunning();
+ }
+}
+
+/// Get the RTOS kernel system timer counter
+uint32_t osKernelSysTick (void) {
+ if (__get_IPSR() != 0U) { return 0U; } // Not allowed in ISR
+ return __svcKernelSysTick();
+}
+
+
+// ==== Thread Management ====
+
+/// Set Thread Error (for Create functions which return IDs)
+static void sysThreadError (osStatus status) {
+ // To Do
+}
+
+__NO_RETURN void osThreadExit (void);
+
+// Thread Service Calls declarations
+SVC_2_1(svcThreadCreate, osThreadId, const osThreadDef_t *, void *, RET_pointer)
+SVC_0_1(svcThreadGetId, osThreadId, RET_pointer)
+SVC_1_1(svcThreadTerminate, osStatus, osThreadId, RET_osStatus)
+SVC_0_1(svcThreadYield, osStatus, RET_osStatus)
+SVC_2_1(svcThreadSetPriority, osStatus, osThreadId, osPriority, RET_osStatus)
+SVC_1_1(svcThreadGetPriority, osPriority, osThreadId, RET_osPriority)
+
+// Thread Service Calls
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId svcThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+ P_TCB ptcb;
+ OS_TID tsk;
+ void *stk;
+
+ if ((thread_def == NULL) ||
+ (thread_def->pthread == NULL) ||
+ (thread_def->tpriority < osPriorityIdle) ||
+ (thread_def->tpriority > osPriorityRealtime)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if (thread_def->stacksize != 0U) { // Custom stack size
+ stk = rt_alloc_mem( // Allocate stack
+ os_stack_mem,
+ thread_def->stacksize
+ );
+ if (stk == NULL) {
+ sysThreadError(osErrorNoMemory); // Out of memory
+ return NULL;
+ }
+ } else { // Default stack size
+ stk = NULL;
+ }
+
+ tsk = rt_tsk_create( // Create task
+ (FUNCP)thread_def->pthread, // Task function pointer
+ (uint32_t)
+ (thread_def->tpriority-osPriorityIdle+1) | // Task priority
+ (thread_def->stacksize << 8), // Task stack size in bytes
+ stk, // Pointer to task's stack
+ argument // Argument to the task
+ );
+
+ if (tsk == 0U) { // Invalid task ID
+ if (stk != NULL) {
+ rt_free_mem(os_stack_mem, stk); // Free allocated stack
+ }
+ sysThreadError(osErrorNoMemory); // Create task failed (Out of memory)
+ return NULL;
+ }
+
+ ptcb = (P_TCB)os_active_TCB[tsk - 1U]; // TCB pointer
+
+ *((uint32_t *)ptcb->tsk_stack + 13) = (uint32_t)osThreadExit;
+
+ return ptcb;
+}
+
+/// Return the thread ID of the current running thread
+osThreadId svcThreadGetId (void) {
+ OS_TID tsk;
+
+ tsk = rt_tsk_self();
+ if (tsk == 0U) { return NULL; }
+ return (P_TCB)os_active_TCB[tsk - 1U];
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus svcThreadTerminate (osThreadId thread_id) {
+ OS_RESULT res;
+ P_TCB ptcb;
+ void *stk;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return osErrorParameter;
+ }
+
+ stk = ptcb->priv_stack ? ptcb->stack : NULL; // Private stack
+
+ res = rt_tsk_delete(ptcb->task_id); // Delete task
+
+ if (res == OS_R_NOK) {
+ return osErrorResource; // Delete task failed
+ }
+
+ if (stk != NULL) {
+ rt_free_mem(os_stack_mem, stk); // Free private stack
+ }
+
+ return osOK;
+}
+
+/// Pass control to next thread that is in state READY
+osStatus svcThreadYield (void) {
+ rt_tsk_pass(); // Pass control to next task
+ return osOK;
+}
+
+/// Change priority of an active thread
+osStatus svcThreadSetPriority (osThreadId thread_id, osPriority priority) {
+ OS_RESULT res;
+ P_TCB ptcb;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return osErrorParameter;
+ }
+
+ if ((priority < osPriorityIdle) || (priority > osPriorityRealtime)) {
+ return osErrorValue;
+ }
+
+ res = rt_tsk_prio( // Change task priority
+ ptcb->task_id, // Task ID
+ (uint8_t)(priority - osPriorityIdle + 1) // New task priority
+ );
+
+ if (res == OS_R_NOK) {
+ return osErrorResource; // Change task priority failed
+ }
+
+ return osOK;
+}
+
+/// Get current priority of an active thread
+osPriority svcThreadGetPriority (osThreadId thread_id) {
+ P_TCB ptcb;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return osPriorityError;
+ }
+
+ return (osPriority)(ptcb->prio - 1 + osPriorityIdle);
+}
+
+
+// Thread Public API
+
+/// Create a thread and add it to Active Threads and set it to state READY
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcThreadCreate(thread_def, argument);
+ } else {
+ return __svcThreadCreate(thread_def, argument);
+ }
+}
+
+/// Return the thread ID of the current running thread
+osThreadId osThreadGetId (void) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ return __svcThreadGetId();
+}
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus osThreadTerminate (osThreadId thread_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcThreadTerminate(thread_id);
+}
+
+/// Pass control to next thread that is in state READY
+osStatus osThreadYield (void) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcThreadYield();
+}
+
+/// Change priority of an active thread
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcThreadSetPriority(thread_id, priority);
+}
+
+/// Get current priority of an active thread
+osPriority osThreadGetPriority (osThreadId thread_id) {
+ if (__get_IPSR() != 0U) {
+ return osPriorityError; // Not allowed in ISR
+ }
+ return __svcThreadGetPriority(thread_id);
+}
+
+/// INTERNAL - Not Public
+/// Auto Terminate Thread on exit (used implicitly when thread exists)
+__NO_RETURN void osThreadExit (void) {
+ __svcThreadTerminate(__svcThreadGetId());
+ for (;;); // Should never come here
+}
+
+
+// ==== Generic Wait Functions ====
+
+// Generic Wait Service Calls declarations
+SVC_1_1(svcDelay, osStatus, uint32_t, RET_osStatus)
+#if osFeature_Wait != 0
+SVC_1_3(svcWait, os_InRegs osEvent, uint32_t, RET_osEvent)
+#endif
+
+// Generic Wait Service Calls
+
+/// Wait for Timeout (Time Delay)
+osStatus svcDelay (uint32_t millisec) {
+ if (millisec == 0U) { return osOK; }
+ rt_dly_wait(rt_ms2tick(millisec));
+ return osEventTimeout;
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+#if osFeature_Wait != 0
+os_InRegs osEvent_type svcWait (uint32_t millisec) {
+ osEvent ret;
+
+ if (millisec == 0U) {
+ ret.status = osOK;
+ return osEvent_ret_status;
+ }
+
+ /* To Do: osEventSignal, osEventMessage, osEventMail */
+ rt_dly_wait(rt_ms2tick(millisec));
+ ret.status = osEventTimeout;
+
+ return osEvent_ret_status;
+}
+#endif
+
+
+// Generic Wait API
+
+/// Wait for Timeout (Time Delay)
+osStatus osDelay (uint32_t millisec) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcDelay(millisec);
+}
+
+/// Wait for Signal, Message, Mail, or Timeout
+os_InRegs osEvent osWait (uint32_t millisec) {
+ osEvent ret;
+
+#if osFeature_Wait == 0
+ ret.status = osErrorOS;
+ return ret;
+#else
+ if (__get_IPSR() != 0U) { // Not allowed in ISR
+ ret.status = osErrorISR;
+ return ret;
+ }
+ return __svcWait(millisec);
+#endif
+}
+
+
+// ==== Timer Management ====
+
+// Timer definitions
+#define osTimerInvalid 0U
+#define osTimerStopped 1U
+#define osTimerRunning 2U
+
+// Timer structures
+
+typedef struct os_timer_cb_ { // Timer Control Block
+ struct os_timer_cb_ *next; // Pointer to next active Timer
+ uint8_t state; // Timer State
+ uint8_t type; // Timer Type (Periodic/One-shot)
+ uint16_t reserved; // Reserved
+ uint32_t tcnt; // Timer Delay Count
+ uint32_t icnt; // Timer Initial Count
+ void *arg; // Timer Function Argument
+ const osTimerDef_t *timer; // Pointer to Timer definition
+} os_timer_cb;
+
+// Timer variables
+os_timer_cb *os_timer_head; // Pointer to first active Timer
+
+
+// Timer Helper Functions
+
+// Insert Timer into the list sorted by time
+static void rt_timer_insert (os_timer_cb *pt, uint32_t tcnt) {
+ os_timer_cb *p, *prev;
+
+ prev = NULL;
+ p = os_timer_head;
+ while (p != NULL) {
+ if (tcnt < p->tcnt) { break; }
+ tcnt -= p->tcnt;
+ prev = p;
+ p = p->next;
+ }
+ pt->next = p;
+ pt->tcnt = tcnt;
+ if (p != NULL) {
+ p->tcnt -= pt->tcnt;
+ }
+ if (prev != NULL) {
+ prev->next = pt;
+ } else {
+ os_timer_head = pt;
+ }
+}
+
+// Remove Timer from the list
+static int32_t rt_timer_remove (os_timer_cb *pt) {
+ os_timer_cb *p, *prev;
+
+ prev = NULL;
+ p = os_timer_head;
+ while (p != NULL) {
+ if (p == pt) { break; }
+ prev = p;
+ p = p->next;
+ }
+ if (p == NULL) { return -1; }
+ if (prev != NULL) {
+ prev->next = pt->next;
+ } else {
+ os_timer_head = pt->next;
+ }
+ if (pt->next != NULL) {
+ pt->next->tcnt += pt->tcnt;
+ }
+
+ return 0;
+}
+
+
+// Timer Service Calls declarations
+SVC_3_1(svcTimerCreate, osTimerId, const osTimerDef_t *, os_timer_type, void *, RET_pointer)
+SVC_2_1(svcTimerStart, osStatus, osTimerId, uint32_t, RET_osStatus)
+SVC_1_1(svcTimerStop, osStatus, osTimerId, RET_osStatus)
+SVC_1_1(svcTimerDelete, osStatus, osTimerId, RET_osStatus)
+SVC_1_2(svcTimerCall, os_InRegs osCallback, osTimerId, RET_osCallback)
+
+// Timer Management Service Calls
+
+/// Create timer
+osTimerId svcTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+ os_timer_cb *pt;
+
+ if ((timer_def == NULL) || (timer_def->ptimer == NULL)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ pt = timer_def->timer;
+ if (pt == NULL) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if ((type != osTimerOnce) && (type != osTimerPeriodic)) {
+ sysThreadError(osErrorValue);
+ return NULL;
+ }
+
+ if (osThreadId_osTimerThread == NULL) {
+ sysThreadError(osErrorResource);
+ return NULL;
+ }
+
+ if (pt->state != osTimerInvalid){
+ sysThreadError(osErrorResource);
+ return NULL;
+ }
+
+ pt->next = NULL;
+ pt->state = osTimerStopped;
+ pt->type = (uint8_t)type;
+ pt->arg = argument;
+ pt->timer = timer_def;
+
+ return (osTimerId)pt;
+}
+
+/// Start or restart timer
+osStatus svcTimerStart (osTimerId timer_id, uint32_t millisec) {
+ os_timer_cb *pt;
+ uint32_t tcnt;
+
+ pt = rt_id2obj(timer_id);
+ if (pt == NULL) {
+ return osErrorParameter;
+ }
+
+ if (millisec == 0U) { return osErrorValue; }
+
+ tcnt = (uint32_t)(((1000U * (uint64_t)millisec) + os_clockrate - 1U) / os_clockrate);
+
+ switch (pt->state) {
+ case osTimerRunning:
+ if (rt_timer_remove(pt) != 0) {
+ return osErrorResource;
+ }
+ break;
+ case osTimerStopped:
+ pt->state = osTimerRunning;
+ pt->icnt = tcnt;
+ break;
+ default:
+ return osErrorResource;
+ }
+
+ rt_timer_insert(pt, tcnt);
+
+ return osOK;
+}
+
+/// Stop timer
+osStatus svcTimerStop (osTimerId timer_id) {
+ os_timer_cb *pt;
+
+ pt = rt_id2obj(timer_id);
+ if (pt == NULL) {
+ return osErrorParameter;
+ }
+
+ if (pt->state != osTimerRunning) { return osErrorResource; }
+
+ pt->state = osTimerStopped;
+
+ if (rt_timer_remove(pt) != 0) {
+ return osErrorResource;
+ }
+
+ return osOK;
+}
+
+/// Delete timer
+osStatus svcTimerDelete (osTimerId timer_id) {
+ os_timer_cb *pt;
+
+ pt = rt_id2obj(timer_id);
+ if (pt == NULL) {
+ return osErrorParameter;
+ }
+
+ switch (pt->state) {
+ case osTimerRunning:
+ rt_timer_remove(pt);
+ break;
+ case osTimerStopped:
+ break;
+ default:
+ return osErrorResource;
+ }
+
+ pt->state = osTimerInvalid;
+
+ return osOK;
+}
+
+/// Get timer callback parameters
+os_InRegs osCallback_type svcTimerCall (osTimerId timer_id) {
+ os_timer_cb *pt;
+ osCallback ret;
+
+ pt = rt_id2obj(timer_id);
+ if (pt == NULL) {
+ ret.fp = NULL;
+ ret.arg = NULL;
+ return osCallback_ret;
+ }
+
+ ret.fp = (void *)pt->timer->ptimer;
+ ret.arg = pt->arg;
+
+ return osCallback_ret;
+}
+
+osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
+
+/// Timer Tick (called each SysTick)
+void sysTimerTick (void) {
+ os_timer_cb *pt, *p;
+ osStatus status;
+
+ p = os_timer_head;
+ if (p == NULL) { return; }
+
+ p->tcnt--;
+ while ((p != NULL) && (p->tcnt == 0U)) {
+ pt = p;
+ p = p->next;
+ os_timer_head = p;
+ status = isrMessagePut(osMessageQId_osTimerMessageQ, (uint32_t)pt, 0U);
+ if (status != osOK) {
+ os_error(OS_ERR_TIMER_OVF);
+ }
+ if (pt->type == (uint8_t)osTimerPeriodic) {
+ rt_timer_insert(pt, pt->icnt);
+ } else {
+ pt->state = osTimerStopped;
+ }
+ }
+}
+
+/// Get user timers wake-up time
+uint32_t sysUserTimerWakeupTime (void) {
+
+ if (os_timer_head) {
+ return os_timer_head->tcnt;
+ }
+ return 0xFFFFFFFFU;
+}
+
+/// Update user timers on resume
+void sysUserTimerUpdate (uint32_t sleep_time) {
+
+ while ((os_timer_head != NULL) && (sleep_time != 0U)) {
+ if (sleep_time >= os_timer_head->tcnt) {
+ sleep_time -= os_timer_head->tcnt;
+ os_timer_head->tcnt = 1U;
+ sysTimerTick();
+ } else {
+ os_timer_head->tcnt -= sleep_time;
+ break;
+ }
+ }
+}
+
+
+// Timer Management Public API
+
+/// Create timer
+osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcTimerCreate(timer_def, type, argument);
+ } else {
+ return __svcTimerCreate(timer_def, type, argument);
+ }
+}
+
+/// Start or restart timer
+osStatus osTimerStart (osTimerId timer_id, uint32_t millisec) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcTimerStart(timer_id, millisec);
+}
+
+/// Stop timer
+osStatus osTimerStop (osTimerId timer_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcTimerStop(timer_id);
+}
+
+/// Delete timer
+osStatus osTimerDelete (osTimerId timer_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcTimerDelete(timer_id);
+}
+
+/// INTERNAL - Not Public
+/// Get timer callback parameters (used by OS Timer Thread)
+os_InRegs osCallback osTimerCall (osTimerId timer_id) {
+ return __svcTimerCall(timer_id);
+}
+
+
+// Timer Thread
+__NO_RETURN void osTimerThread (void const *argument) {
+ osCallback cb;
+ osEvent evt;
+
+ for (;;) {
+ evt = osMessageGet(osMessageQId_osTimerMessageQ, osWaitForever);
+ if (evt.status == osEventMessage) {
+ cb = osTimerCall(evt.value.p);
+ if (cb.fp != NULL) {
+ (*(os_ptimer)cb.fp)(cb.arg);
+ }
+ }
+ }
+}
+
+
+// ==== Signal Management ====
+
+// Signal Service Calls declarations
+SVC_2_1(svcSignalSet, int32_t, osThreadId, int32_t, RET_int32_t)
+SVC_2_1(svcSignalClear, int32_t, osThreadId, int32_t, RET_int32_t)
+SVC_2_3(svcSignalWait, os_InRegs osEvent, int32_t, uint32_t, RET_osEvent)
+
+// Signal Service Calls
+
+/// Set the specified Signal Flags of an active thread
+int32_t svcSignalSet (osThreadId thread_id, int32_t signals) {
+ P_TCB ptcb;
+ int32_t sig;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return (int32_t)0x80000000U;
+ }
+
+ if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
+ return (int32_t)0x80000000U;
+ }
+
+ sig = (int32_t)ptcb->events; // Previous signal flags
+
+ rt_evt_set((uint16_t)signals, ptcb->task_id); // Set event flags
+
+ return sig;
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t svcSignalClear (osThreadId thread_id, int32_t signals) {
+ P_TCB ptcb;
+ int32_t sig;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return (int32_t)0x80000000U;
+ }
+
+ if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
+ return (int32_t)0x80000000U;
+ }
+
+ sig = (int32_t)ptcb->events; // Previous signal flags
+
+ rt_evt_clr((uint16_t)signals, ptcb->task_id); // Clear event flags
+
+ return sig;
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent_type svcSignalWait (int32_t signals, uint32_t millisec) {
+ OS_RESULT res;
+ osEvent ret;
+
+ if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
+ ret.status = osErrorValue;
+ return osEvent_ret_status;
+ }
+
+ if (signals != 0) { // Wait for all specified signals
+ res = rt_evt_wait((uint16_t)signals, rt_ms2tick(millisec), __TRUE);
+ } else { // Wait for any signal
+ res = rt_evt_wait(0xFFFFU, rt_ms2tick(millisec), __FALSE);
+ }
+
+ if (res == OS_R_EVT) {
+ ret.status = osEventSignal;
+ ret.value.signals = (signals != 0) ? signals : (int32_t)os_tsk.run->waits;
+ } else {
+ ret.status = (millisec != 0U) ? osEventTimeout : osOK;
+ ret.value.signals = 0;
+ }
+
+ return osEvent_ret_value;
+}
+
+
+// Signal ISR Calls
+
+/// Set the specified Signal Flags of an active thread
+int32_t isrSignalSet (osThreadId thread_id, int32_t signals) {
+ P_TCB ptcb;
+ int32_t sig;
+
+ ptcb = rt_tid2ptcb(thread_id); // Get TCB pointer
+ if (ptcb == NULL) {
+ return (int32_t)0x80000000U;
+ }
+
+ if ((uint32_t)signals & (0xFFFFFFFFU << osFeature_Signals)) {
+ return (int32_t)0x80000000U;
+ }
+
+ sig = (int32_t)ptcb->events; // Previous signal flags
+
+ isr_evt_set((uint16_t)signals, ptcb->task_id);// Set event flags
+
+ return sig;
+}
+
+
+// Signal Public API
+
+/// Set the specified Signal Flags of an active thread
+int32_t osSignalSet (osThreadId thread_id, int32_t signals) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return isrSignalSet(thread_id, signals);
+ } else { // in Thread
+ return __svcSignalSet(thread_id, signals);
+ }
+}
+
+/// Clear the specified Signal Flags of an active thread
+int32_t osSignalClear (osThreadId thread_id, int32_t signals) {
+ if (__get_IPSR() != 0U) {
+ return (int32_t)0x80000000U; // Not allowed in ISR
+ }
+ return __svcSignalClear(thread_id, signals);
+}
+
+/// Wait for one or more Signal Flags to become signaled for the current RUNNING thread
+os_InRegs osEvent osSignalWait (int32_t signals, uint32_t millisec) {
+ osEvent ret;
+
+ if (__get_IPSR() != 0U) { // Not allowed in ISR
+ ret.status = osErrorISR;
+ return ret;
+ }
+ return __svcSignalWait(signals, millisec);
+}
+
+
+// ==== Mutex Management ====
+
+// Mutex Service Calls declarations
+SVC_1_1(svcMutexCreate, osMutexId, const osMutexDef_t *, RET_pointer)
+SVC_2_1(svcMutexWait, osStatus, osMutexId, uint32_t, RET_osStatus)
+SVC_1_1(svcMutexRelease, osStatus, osMutexId, RET_osStatus)
+SVC_1_1(svcMutexDelete, osStatus, osMutexId, RET_osStatus)
+
+// Mutex Service Calls
+
+/// Create and Initialize a Mutex object
+osMutexId svcMutexCreate (const osMutexDef_t *mutex_def) {
+ OS_ID mut;
+
+ if (mutex_def == NULL) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ mut = mutex_def->mutex;
+ if (mut == NULL) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if (((P_MUCB)mut)->cb_type != 0U) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ rt_mut_init(mut); // Initialize Mutex
+
+ return mut;
+}
+
+/// Wait until a Mutex becomes available
+osStatus svcMutexWait (osMutexId mutex_id, uint32_t millisec) {
+ OS_ID mut;
+ OS_RESULT res;
+
+ mut = rt_id2obj(mutex_id);
+ if (mut == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_MUCB)mut)->cb_type != MUCB) {
+ return osErrorParameter;
+ }
+
+ res = rt_mut_wait(mut, rt_ms2tick(millisec)); // Wait for Mutex
+
+ if (res == OS_R_TMO) {
+ return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);
+ }
+
+ return osOK;
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus svcMutexRelease (osMutexId mutex_id) {
+ OS_ID mut;
+ OS_RESULT res;
+
+ mut = rt_id2obj(mutex_id);
+ if (mut == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_MUCB)mut)->cb_type != MUCB) {
+ return osErrorParameter;
+ }
+
+ res = rt_mut_release(mut); // Release Mutex
+
+ if (res == OS_R_NOK) {
+ return osErrorResource; // Thread not owner or Zero Counter
+ }
+
+ return osOK;
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus svcMutexDelete (osMutexId mutex_id) {
+ OS_ID mut;
+
+ mut = rt_id2obj(mutex_id);
+ if (mut == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_MUCB)mut)->cb_type != MUCB) {
+ return osErrorParameter;
+ }
+
+ rt_mut_delete(mut); // Release Mutex
+
+ return osOK;
+}
+
+
+// Mutex Public API
+
+/// Create and Initialize a Mutex object
+osMutexId osMutexCreate (const osMutexDef_t *mutex_def) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcMutexCreate(mutex_def);
+ } else {
+ return __svcMutexCreate(mutex_def);
+ }
+}
+
+/// Wait until a Mutex becomes available
+osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcMutexWait(mutex_id, millisec);
+}
+
+/// Release a Mutex that was obtained with osMutexWait
+osStatus osMutexRelease (osMutexId mutex_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcMutexRelease(mutex_id);
+}
+
+/// Delete a Mutex that was created by osMutexCreate
+osStatus osMutexDelete (osMutexId mutex_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcMutexDelete(mutex_id);
+}
+
+
+// ==== Semaphore Management ====
+
+// Semaphore Service Calls declarations
+SVC_2_1(svcSemaphoreCreate, osSemaphoreId, const osSemaphoreDef_t *, int32_t, RET_pointer)
+SVC_2_1(svcSemaphoreWait, int32_t, osSemaphoreId, uint32_t, RET_int32_t)
+SVC_1_1(svcSemaphoreRelease, osStatus, osSemaphoreId, RET_osStatus)
+SVC_1_1(svcSemaphoreDelete, osStatus, osSemaphoreId, RET_osStatus)
+
+// Semaphore Service Calls
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId svcSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+ OS_ID sem;
+
+ if (semaphore_def == NULL) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ sem = semaphore_def->semaphore;
+ if (sem == NULL) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if (((P_SCB)sem)->cb_type != 0U) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if (count > osFeature_Semaphore) {
+ sysThreadError(osErrorValue);
+ return NULL;
+ }
+
+ rt_sem_init(sem, (uint16_t)count); // Initialize Semaphore
+
+ return sem;
+}
+
+/// Wait until a Semaphore becomes available
+int32_t svcSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+ OS_ID sem;
+ OS_RESULT res;
+
+ sem = rt_id2obj(semaphore_id);
+ if (sem == NULL) {
+ return -1;
+ }
+
+ if (((P_SCB)sem)->cb_type != SCB) {
+ return -1;
+ }
+
+ res = rt_sem_wait(sem, rt_ms2tick(millisec)); // Wait for Semaphore
+
+ if (res == OS_R_TMO) { return 0; } // Timeout
+
+ return (int32_t)(((P_SCB)sem)->tokens + 1U);
+}
+
+/// Release a Semaphore
+osStatus svcSemaphoreRelease (osSemaphoreId semaphore_id) {
+ OS_ID sem;
+
+ sem = rt_id2obj(semaphore_id);
+ if (sem == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_SCB)sem)->cb_type != SCB) {
+ return osErrorParameter;
+ }
+
+ if ((int32_t)((P_SCB)sem)->tokens == osFeature_Semaphore) {
+ return osErrorResource;
+ }
+
+ rt_sem_send(sem); // Release Semaphore
+
+ return osOK;
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus svcSemaphoreDelete (osSemaphoreId semaphore_id) {
+ OS_ID sem;
+
+ sem = rt_id2obj(semaphore_id);
+ if (sem == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_SCB)sem)->cb_type != SCB) {
+ return osErrorParameter;
+ }
+
+ rt_sem_delete(sem); // Delete Semaphore
+
+ return osOK;
+}
+
+
+// Semaphore ISR Calls
+
+/// Release a Semaphore
+osStatus isrSemaphoreRelease (osSemaphoreId semaphore_id) {
+ OS_ID sem;
+
+ sem = rt_id2obj(semaphore_id);
+ if (sem == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_SCB)sem)->cb_type != SCB) {
+ return osErrorParameter;
+ }
+
+ if ((int32_t)((P_SCB)sem)->tokens == osFeature_Semaphore) {
+ return osErrorResource;
+ }
+
+ isr_sem_send(sem); // Release Semaphore
+
+ return osOK;
+}
+
+
+// Semaphore Public API
+
+/// Create and Initialize a Semaphore object
+osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcSemaphoreCreate(semaphore_def, count);
+ } else {
+ return __svcSemaphoreCreate(semaphore_def, count);
+ }
+}
+
+/// Wait until a Semaphore becomes available
+int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec) {
+ if (__get_IPSR() != 0U) {
+ return -1; // Not allowed in ISR
+ }
+ return __svcSemaphoreWait(semaphore_id, millisec);
+}
+
+/// Release a Semaphore
+osStatus osSemaphoreRelease (osSemaphoreId semaphore_id) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return isrSemaphoreRelease(semaphore_id);
+ } else { // in Thread
+ return __svcSemaphoreRelease(semaphore_id);
+ }
+}
+
+/// Delete a Semaphore that was created by osSemaphoreCreate
+osStatus osSemaphoreDelete (osSemaphoreId semaphore_id) {
+ if (__get_IPSR() != 0U) {
+ return osErrorISR; // Not allowed in ISR
+ }
+ return __svcSemaphoreDelete(semaphore_id);
+}
+
+
+// ==== Memory Management Functions ====
+
+// Memory Management Helper Functions
+
+// Clear Memory Box (Zero init)
+static void rt_clr_box (void *box_mem, void *box) {
+ uint32_t *p, n;
+
+ if ((box_mem != NULL) && (box != NULL)) {
+ p = box;
+ for (n = ((P_BM)box_mem)->blk_size; n; n -= 4U) {
+ *p++ = 0U;
+ }
+ }
+}
+
+// Memory Management Service Calls declarations
+SVC_1_1(svcPoolCreate, osPoolId, const osPoolDef_t *, RET_pointer)
+SVC_1_1(sysPoolAlloc, void *, osPoolId, RET_pointer)
+SVC_2_1(sysPoolFree, osStatus, osPoolId, void *, RET_osStatus)
+
+// Memory Management Service & ISR Calls
+
+/// Create and Initialize memory pool
+osPoolId svcPoolCreate (const osPoolDef_t *pool_def) {
+ uint32_t blk_sz;
+
+ if ((pool_def == NULL) ||
+ (pool_def->pool_sz == 0U) ||
+ (pool_def->item_sz == 0U) ||
+ (pool_def->pool == NULL)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ blk_sz = (pool_def->item_sz + 3U) & (uint32_t)~3U;
+
+ _init_box(pool_def->pool, sizeof(struct OS_BM) + (pool_def->pool_sz * blk_sz), blk_sz);
+
+ return pool_def->pool;
+}
+
+/// Allocate a memory block from a memory pool
+void *sysPoolAlloc (osPoolId pool_id) {
+ void *mem;
+
+ if (pool_id == NULL) {
+ return NULL;
+ }
+
+ mem = rt_alloc_box(pool_id);
+
+ return mem;
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus sysPoolFree (osPoolId pool_id, void *block) {
+ uint32_t res;
+
+ if (pool_id == NULL) {
+ return osErrorParameter;
+ }
+
+ res = rt_free_box(pool_id, block);
+ if (res != 0) {
+ return osErrorValue;
+ }
+
+ return osOK;
+}
+
+
+// Memory Management Public API
+
+/// Create and Initialize memory pool
+osPoolId osPoolCreate (const osPoolDef_t *pool_def) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcPoolCreate(pool_def);
+ } else {
+ return __svcPoolCreate(pool_def);
+ }
+}
+
+/// Allocate a memory block from a memory pool
+void *osPoolAlloc (osPoolId pool_id) {
+ if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) { // in ISR or Privileged
+ return sysPoolAlloc(pool_id);
+ } else { // in Thread
+ return __sysPoolAlloc(pool_id);
+ }
+}
+
+/// Allocate a memory block from a memory pool and set memory block to zero
+void *osPoolCAlloc (osPoolId pool_id) {
+ void *mem;
+
+ if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) { // in ISR or Privileged
+ mem = sysPoolAlloc(pool_id);
+ } else { // in Thread
+ mem = __sysPoolAlloc(pool_id);
+ }
+
+ rt_clr_box(pool_id, mem);
+
+ return mem;
+}
+
+/// Return an allocated memory block back to a specific memory pool
+osStatus osPoolFree (osPoolId pool_id, void *block) {
+ if ((__get_IPSR() != 0U) || ((__get_CONTROL() & 1U) == 0U)) { // in ISR or Privileged
+ return sysPoolFree(pool_id, block);
+ } else { // in Thread
+ return __sysPoolFree(pool_id, block);
+ }
+}
+
+
+// ==== Message Queue Management Functions ====
+
+// Message Queue Management Service Calls declarations
+SVC_2_1(svcMessageCreate, osMessageQId, const osMessageQDef_t *, osThreadId, RET_pointer)
+SVC_3_1(svcMessagePut, osStatus, osMessageQId, uint32_t, uint32_t, RET_osStatus)
+SVC_2_3(svcMessageGet, os_InRegs osEvent, osMessageQId, uint32_t, RET_osEvent)
+
+// Message Queue Service Calls
+
+/// Create and Initialize Message Queue
+osMessageQId svcMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+
+ if ((queue_def == NULL) ||
+ (queue_def->queue_sz == 0U) ||
+ (queue_def->pool == NULL)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ if (((P_MCB)queue_def->pool)->cb_type != 0U) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ rt_mbx_init(queue_def->pool, (uint16_t)(4U*(queue_def->queue_sz + 4U)));
+
+ return queue_def->pool;
+}
+
+/// Put a Message to a Queue
+osStatus svcMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+ OS_RESULT res;
+
+ if (queue_id == NULL) {
+ return osErrorParameter;
+ }
+
+ if (((P_MCB)queue_id)->cb_type != MCB) {
+ return osErrorParameter;
+ }
+
+ res = rt_mbx_send(queue_id, (void *)info, rt_ms2tick(millisec));
+
+ if (res == OS_R_TMO) {
+ return ((millisec != 0U) ? osErrorTimeoutResource : osErrorResource);
+ }
+
+ return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent_type svcMessageGet (osMessageQId queue_id, uint32_t millisec) {
+ OS_RESULT res;
+ osEvent ret;
+
+ if (queue_id == NULL) {
+ ret.status = osErrorParameter;
+ return osEvent_ret_status;
+ }
+
+ if (((P_MCB)queue_id)->cb_type != MCB) {
+ ret.status = osErrorParameter;
+ return osEvent_ret_status;
+ }
+
+ res = rt_mbx_wait(queue_id, &ret.value.p, rt_ms2tick(millisec));
+
+ if (res == OS_R_TMO) {
+ ret.status = (millisec != 0U) ? osEventTimeout : osOK;
+ return osEvent_ret_value;
+ }
+
+ ret.status = osEventMessage;
+
+ return osEvent_ret_value;
+}
+
+
+// Message Queue ISR Calls
+
+/// Put a Message to a Queue
+osStatus isrMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+
+ if ((queue_id == NULL) || (millisec != 0U)) {
+ return osErrorParameter;
+ }
+
+ if (((P_MCB)queue_id)->cb_type != MCB) {
+ return osErrorParameter;
+ }
+
+ if (rt_mbx_check(queue_id) == 0U) { // Check if Queue is full
+ return osErrorResource;
+ }
+
+ isr_mbx_send(queue_id, (void *)info);
+
+ return osOK;
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent isrMessageGet (osMessageQId queue_id, uint32_t millisec) {
+ OS_RESULT res;
+ osEvent ret;
+
+ if ((queue_id == NULL) || (millisec != 0U)) {
+ ret.status = osErrorParameter;
+ return ret;
+ }
+
+ if (((P_MCB)queue_id)->cb_type != MCB) {
+ ret.status = osErrorParameter;
+ return ret;
+ }
+
+ res = isr_mbx_receive(queue_id, &ret.value.p);
+
+ if (res != OS_R_MBX) {
+ ret.status = osOK;
+ return ret;
+ }
+
+ ret.status = osEventMessage;
+
+ return ret;
+}
+
+
+// Message Queue Management Public API
+
+/// Create and Initialize Message Queue
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcMessageCreate(queue_def, thread_id);
+ } else {
+ return __svcMessageCreate(queue_def, thread_id);
+ }
+}
+
+/// Put a Message to a Queue
+osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return isrMessagePut(queue_id, info, millisec);
+ } else { // in Thread
+ return __svcMessagePut(queue_id, info, millisec);
+ }
+}
+
+/// Get a Message or Wait for a Message from a Queue
+os_InRegs osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return isrMessageGet(queue_id, millisec);
+ } else { // in Thread
+ return __svcMessageGet(queue_id, millisec);
+ }
+}
+
+
+// ==== Mail Queue Management Functions ====
+
+// Mail Queue Management Service Calls declarations
+SVC_2_1(svcMailCreate, osMailQId, const osMailQDef_t *, osThreadId, RET_pointer)
+SVC_3_1(sysMailAlloc, void *, osMailQId, uint32_t, uint32_t, RET_pointer)
+SVC_3_1(sysMailFree, osStatus, osMailQId, void *, uint32_t, RET_osStatus)
+
+// Mail Queue Management Service & ISR Calls
+
+/// Create and Initialize mail queue
+osMailQId svcMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+ uint32_t blk_sz;
+ P_MCB pmcb;
+ void *pool;
+
+ if ((queue_def == NULL) ||
+ (queue_def->queue_sz == 0U) ||
+ (queue_def->item_sz == 0U) ||
+ (queue_def->pool == NULL)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ pmcb = *(((void **)queue_def->pool) + 0);
+ pool = *(((void **)queue_def->pool) + 1);
+
+ if ((pool == NULL) || (pmcb == NULL) || (pmcb->cb_type != 0U)) {
+ sysThreadError(osErrorParameter);
+ return NULL;
+ }
+
+ blk_sz = (queue_def->item_sz + 3U) & (uint32_t)~3U;
+
+ _init_box(pool, sizeof(struct OS_BM) + (queue_def->queue_sz * blk_sz), blk_sz);
+
+ rt_mbx_init(pmcb, (uint16_t)(4U*(queue_def->queue_sz + 4U)));
+
+ return queue_def->pool;
+}
+
+/// Allocate a memory block from a mail
+void *sysMailAlloc (osMailQId queue_id, uint32_t millisec, uint32_t isr) {
+ P_MCB pmcb;
+ void *pool;
+ void *mem;
+
+ if (queue_id == NULL) {
+ return NULL;
+ }
+
+ pmcb = *(((void **)queue_id) + 0);
+ pool = *(((void **)queue_id) + 1);
+
+ if ((pool == NULL) || (pmcb == NULL)) {
+ return NULL;
+ }
+
+ if ((isr != 0U) && (millisec != 0U)) {
+ return NULL;
+ }
+
+ mem = rt_alloc_box(pool);
+
+ if ((mem == NULL) && (millisec != 0U)) {
+ // Put Task to sleep when Memory not available
+ if (pmcb->p_lnk != NULL) {
+ rt_put_prio((P_XCB)pmcb, os_tsk.run);
+ } else {
+ pmcb->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)pmcb;
+ // Task is waiting to allocate a message
+ pmcb->state = 3U;
+ }
+ rt_block(rt_ms2tick(millisec), WAIT_MBX);
+ }
+
+ return mem;
+}
+
+/// Free a memory block from a mail
+osStatus sysMailFree (osMailQId queue_id, void *mail, uint32_t isr) {
+ P_MCB pmcb;
+ P_TCB ptcb;
+ void *pool;
+ void *mem;
+ uint32_t res;
+
+ if (queue_id == NULL) {
+ return osErrorParameter;
+ }
+
+ pmcb = *(((void **)queue_id) + 0);
+ pool = *(((void **)queue_id) + 1);
+
+ if ((pmcb == NULL) || (pool == NULL)) {
+ return osErrorParameter;
+ }
+
+ res = rt_free_box(pool, mail);
+
+ if (res != 0U) {
+ return osErrorValue;
+ }
+
+ if ((pmcb->p_lnk != NULL) && (pmcb->state == 3U)) {
+ // Task is waiting to allocate a message
+ if (isr != 0U) {
+ rt_psq_enq (pmcb, (U32)pool);
+ rt_psh_req ();
+ } else {
+ mem = rt_alloc_box(pool);
+ if (mem != NULL) {
+ ptcb = rt_get_first((P_XCB)pmcb);
+ rt_ret_val(ptcb, (U32)mem);
+ rt_rmv_dly(ptcb);
+ rt_dispatch(ptcb);
+ }
+ }
+ }
+
+ return osOK;
+}
+
+
+// Mail Queue Management Public API
+
+/// Create and Initialize mail queue
+osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id) {
+ if (__get_IPSR() != 0U) {
+ return NULL; // Not allowed in ISR
+ }
+ if (((__get_CONTROL() & 1U) == 0U) && (os_running == 0U)) {
+ // Privileged and not running
+ return svcMailCreate(queue_def, thread_id);
+ } else {
+ return __svcMailCreate(queue_def, thread_id);
+ }
+}
+
+/// Allocate a memory block from a mail
+void *osMailAlloc (osMailQId queue_id, uint32_t millisec) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return sysMailAlloc(queue_id, millisec, 1U);
+ } else { // in Thread
+ return __sysMailAlloc(queue_id, millisec, 0U);
+ }
+}
+
+/// Allocate a memory block from a mail and set memory block to zero
+void *osMailCAlloc (osMailQId queue_id, uint32_t millisec) {
+ void *pool;
+ void *mem;
+
+ if (__get_IPSR() != 0U) { // in ISR
+ mem = sysMailAlloc(queue_id, millisec, 1U);
+ } else { // in Thread
+ mem = __sysMailAlloc(queue_id, millisec, 0U);
+ }
+
+ pool = *(((void **)queue_id) + 1);
+
+ rt_clr_box(pool, mem);
+
+ return mem;
+}
+
+/// Free a memory block from a mail
+osStatus osMailFree (osMailQId queue_id, void *mail) {
+ if (__get_IPSR() != 0U) { // in ISR
+ return sysMailFree(queue_id, mail, 1U);
+ } else { // in Thread
+ return __sysMailFree(queue_id, mail, 0U);
+ }
+}
+
+/// Put a mail to a queue
+osStatus osMailPut (osMailQId queue_id, void *mail) {
+ if (queue_id == NULL) {
+ return osErrorParameter;
+ }
+ if (mail == NULL) {
+ return osErrorValue;
+ }
+ return osMessagePut(*((void **)queue_id), (uint32_t)mail, 0U);
+}
+
+/// Get a mail from a queue
+os_InRegs osEvent osMailGet (osMailQId queue_id, uint32_t millisec) {
+ osEvent ret;
+
+ if (queue_id == NULL) {
+ ret.status = osErrorParameter;
+ return ret;
+ }
+
+ ret = osMessageGet(*((void **)queue_id), millisec);
+ if (ret.status == osEventMessage) ret.status = osEventMail;
+
+ return ret;
+}
+
+
+// ==== RTX Extensions ====
+
+// Service Calls declarations
+SVC_0_1(rt_suspend, uint32_t, RET_uint32_t)
+SVC_1_0(rt_resume, void, uint32_t)
+
+
+// Public API
+
+/// Suspends the OS task scheduler
+uint32_t os_suspend (void) {
+ return __rt_suspend();
+}
+
+/// Resumes the OS task scheduler
+void os_resume (uint32_t sleep_time) {
+ __rt_resume(sleep_time);
+}
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Event.c b/CMSIS/RTOS/RTX/SRC/rt_Event.c
new file mode 100644
index 0000000..ba92293
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Event.c
@@ -0,0 +1,190 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_EVENT.C
+ * Purpose: Implements waits and wake-ups for event flags
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_evt_wait -----------------------------------*/
+
+OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait) {
+ /* Wait for one or more event flags with optional time-out. */
+ /* "wait_flags" identifies the flags to wait for. */
+ /* "timeout" is the time-out limit in system ticks (0xffff if no time-out) */
+ /* "and_wait" specifies the AND-ing of "wait_flags" as condition to be met */
+ /* to complete the wait. (OR-ing if set to 0). */
+ U32 block_state;
+
+ if (and_wait) {
+ /* Check for AND-connected events */
+ if ((os_tsk.run->events & wait_flags) == wait_flags) {
+ os_tsk.run->events &= ~wait_flags;
+ return (OS_R_EVT);
+ }
+ block_state = WAIT_AND;
+ }
+ else {
+ /* Check for OR-connected events */
+ if (os_tsk.run->events & wait_flags) {
+ os_tsk.run->waits = os_tsk.run->events & wait_flags;
+ os_tsk.run->events &= ~wait_flags;
+ return (OS_R_EVT);
+ }
+ block_state = WAIT_OR;
+ }
+ /* Task has to wait */
+ os_tsk.run->waits = wait_flags;
+ rt_block (timeout, (U8)block_state);
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_evt_set ------------------------------------*/
+
+void rt_evt_set (U16 event_flags, OS_TID task_id) {
+ /* Set one or more event flags of a selectable task. */
+ P_TCB p_tcb;
+
+ p_tcb = os_active_TCB[task_id-1U];
+ if (p_tcb == NULL) {
+ return;
+ }
+ p_tcb->events |= event_flags;
+ event_flags = p_tcb->waits;
+ /* If the task is not waiting for an event, it should not be put */
+ /* to ready state. */
+ if (p_tcb->state == WAIT_AND) {
+ /* Check for AND-connected events */
+ if ((p_tcb->events & event_flags) == event_flags) {
+ goto wkup;
+ }
+ }
+ if (p_tcb->state == WAIT_OR) {
+ /* Check for OR-connected events */
+ if (p_tcb->events & event_flags) {
+ p_tcb->waits &= p_tcb->events;
+wkup: p_tcb->events &= ~event_flags;
+ rt_rmv_dly (p_tcb);
+ p_tcb->state = READY;
+#ifdef __CMSIS_RTOS
+ rt_ret_val2(p_tcb, 0x08U/*osEventSignal*/, p_tcb->waits);
+#else
+ rt_ret_val (p_tcb, OS_R_EVT);
+#endif
+ rt_dispatch (p_tcb);
+ }
+ }
+}
+
+
+/*--------------------------- rt_evt_clr ------------------------------------*/
+
+void rt_evt_clr (U16 clear_flags, OS_TID task_id) {
+ /* Clear one or more event flags (identified by "clear_flags") of a */
+ /* selectable task (identified by "task"). */
+ P_TCB task = os_active_TCB[task_id-1U];
+
+ if (task == NULL) {
+ return;
+ }
+ task->events &= ~clear_flags;
+}
+
+
+/*--------------------------- isr_evt_set -----------------------------------*/
+
+void isr_evt_set (U16 event_flags, OS_TID task_id) {
+ /* Same function as "os_evt_set", but to be called by ISRs. */
+ P_TCB p_tcb = os_active_TCB[task_id-1U];
+
+ if (p_tcb == NULL) {
+ return;
+ }
+ rt_psq_enq (p_tcb, event_flags);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- rt_evt_get ------------------------------------*/
+
+U16 rt_evt_get (void) {
+ /* Get events of a running task after waiting for OR connected events. */
+ return (os_tsk.run->waits);
+}
+
+
+/*--------------------------- rt_evt_psh ------------------------------------*/
+
+void rt_evt_psh (P_TCB p_CB, U16 set_flags) {
+ /* Check if task has to be waken up */
+ U16 event_flags;
+
+ p_CB->events |= set_flags;
+ event_flags = p_CB->waits;
+ if (p_CB->state == WAIT_AND) {
+ /* Check for AND-connected events */
+ if ((p_CB->events & event_flags) == event_flags) {
+ goto rdy;
+ }
+ }
+ if (p_CB->state == WAIT_OR) {
+ /* Check for OR-connected events */
+ if (p_CB->events & event_flags) {
+ p_CB->waits &= p_CB->events;
+rdy: p_CB->events &= ~event_flags;
+ rt_rmv_dly (p_CB);
+ p_CB->state = READY;
+#ifdef __CMSIS_RTOS
+ rt_ret_val2(p_CB, 0x08U/*osEventSignal*/, p_CB->waits);
+#else
+ rt_ret_val (p_CB, OS_R_EVT);
+#endif
+ rt_put_prio (&os_rdy, p_CB);
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Event.h b/CMSIS/RTOS/RTX/SRC/rt_Event.h
new file mode 100644
index 0000000..ebe9765
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Event.h
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_EVENT.H
+ * Purpose: Implements waits and wake-ups for event flags
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern OS_RESULT rt_evt_wait (U16 wait_flags, U16 timeout, BOOL and_wait);
+extern void rt_evt_set (U16 event_flags, OS_TID task_id);
+extern void rt_evt_clr (U16 clear_flags, OS_TID task_id);
+extern void isr_evt_set (U16 event_flags, OS_TID task_id);
+extern U16 rt_evt_get (void);
+extern void rt_evt_psh (P_TCB p_CB, U16 set_flags);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h b/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h
new file mode 100644
index 0000000..dd97edf
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_HAL_CM.h
@@ -0,0 +1,289 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_HAL_CM.H
+ * Purpose: Hardware Abstraction Layer for Cortex-M definitions
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+#define INITIAL_xPSR 0x01000000U
+#define DEMCR_TRCENA 0x01000000U
+#define ITM_ITMENA 0x00000001U
+#define MAGIC_WORD 0xE25A2EA5U
+#define MAGIC_PATTERN 0xCCCCCCCCU
+
+#if defined (__CC_ARM) /* ARM Compiler */
+
+#if ((defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M)) && !defined(NO_EXCLUSIVE_ACCESS))
+ #define __USE_EXCLUSIVE_ACCESS
+#else
+ #undef __USE_EXCLUSIVE_ACCESS
+#endif
+
+#ifndef __CMSIS_GENERIC
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0)
+#endif
+
+#elif defined (__GNUC__) /* GNU Compiler */
+
+#undef __USE_EXCLUSIVE_ACCESS
+
+#if defined (__CORTEX_M0)
+#define __TARGET_ARCH_6S_M
+#endif
+
+#if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#define __TARGET_FPU_VFP
+#endif
+
+#define __inline inline
+#define __weak __attribute__((weak))
+
+#ifndef __CMSIS_GENERIC
+
+__attribute__((always_inline)) static inline void __enable_irq(void)
+{
+ __asm volatile ("cpsie i");
+}
+
+__attribute__((always_inline)) static inline U32 __disable_irq(void)
+{
+ U32 result;
+
+ __asm volatile ("mrs %0, primask" : "=r" (result));
+ __asm volatile ("cpsid i");
+ return(result & 1);
+}
+
+__attribute__((always_inline)) static inline void __DMB(void)
+{
+ __asm volatile ("dmb 0xF":::"memory");
+}
+
+#endif
+
+__attribute__(( always_inline)) static inline U8 __clz(U32 value)
+{
+ U8 result;
+
+ __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+ return(result);
+}
+
+#elif defined (__ICCARM__) /* IAR Compiler */
+
+#undef __USE_EXCLUSIVE_ACCESS
+
+#if (__CORE__ == __ARM6M__)
+#define __TARGET_ARCH_6S_M 1
+#endif
+
+#if defined __ARMVFP__
+#define __TARGET_FPU_VFP 1
+#endif
+
+#define __inline inline
+
+#ifndef __CMSIS_GENERIC
+
+static inline void __enable_irq(void)
+{
+ __asm volatile ("cpsie i");
+}
+
+static inline U32 __disable_irq(void)
+{
+ U32 result;
+
+ __asm volatile ("mrs %0, primask" : "=r" (result));
+ __asm volatile ("cpsid i");
+ return(result & 1);
+}
+
+#endif
+
+static inline U8 __clz(U32 value)
+{
+ U8 result;
+
+ __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
+ return(result);
+}
+
+#endif
+
+/* NVIC registers */
+#define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010U))
+#define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014U))
+#define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018U))
+#define NVIC_ISER ((volatile U32 *)0xE000E100U)
+#define NVIC_ICER ((volatile U32 *)0xE000E180U)
+#if defined(__TARGET_ARCH_6S_M)
+#define NVIC_IP ((volatile U32 *)0xE000E400U)
+#else
+#define NVIC_IP ((volatile U8 *)0xE000E400U)
+#endif
+#define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04U))
+#define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0CU))
+#define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1CU))
+#define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20U))
+
+#define OS_PEND_IRQ() NVIC_INT_CTRL = (1UL<<28)
+#define OS_PENDING ((NVIC_INT_CTRL >> 26) & 5U)
+#define OS_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_PENDING) << 25
+#define OS_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | (U8)(p<<2)) << 26
+#define OS_LOCK() NVIC_ST_CTRL = 0x0005U
+#define OS_UNLOCK() NVIC_ST_CTRL = 0x0007U
+
+#define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1U)
+#define OS_X_UNPEND(fl) NVIC_INT_CTRL = (U32)(fl = (U8)OS_X_PENDING) << 27
+#define OS_X_PEND(fl,p) NVIC_INT_CTRL = (U32)(fl | p) << 28
+#if defined(__TARGET_ARCH_6S_M)
+#define OS_X_INIT(n) NVIC_IP[n>>2] |= (U32)0xFFU << ((n & 0x03U) << 3); \
+ NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
+#else
+#define OS_X_INIT(n) NVIC_IP[n] = 0xFFU; \
+ NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
+#endif
+#define OS_X_LOCK(n) NVIC_ICER[n>>5] = (U32)1U << (n & 0x1FU)
+#define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = (U32)1U << (n & 0x1FU)
+
+/* Core Debug registers */
+#define DEMCR (*((volatile U32 *)0xE000EDFCU))
+
+/* ITM registers */
+#define ITM_CONTROL (*((volatile U32 *)0xE0000E80U))
+#define ITM_ENABLE (*((volatile U32 *)0xE0000E00U))
+#define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078U))
+#define ITM_PORT31_U32 (*((volatile U32 *)0xE000007CU))
+#define ITM_PORT31_U16 (*((volatile U16 *)0xE000007CU))
+#define ITM_PORT31_U8 (*((volatile U8 *)0xE000007CU))
+
+/* Variables */
+extern BIT dbg_msg;
+
+/* Functions */
+#ifdef __USE_EXCLUSIVE_ACCESS
+ #define rt_inc(p) while(__strex((__ldrex(p)+1U),p))
+ #define rt_dec(p) while(__strex((__ldrex(p)-1U),p))
+#else
+ #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
+ #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
+#endif
+
+__inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
+ U32 cnt,c2;
+#ifdef __USE_EXCLUSIVE_ACCESS
+ do {
+ if ((cnt = __ldrex(count)) == size) {
+ __clrex();
+ return (cnt); }
+ } while (__strex(cnt+1U, count));
+ do {
+ c2 = (cnt = __ldrex(first)) + 1U;
+ if (c2 == size) { c2 = 0U; }
+ } while (__strex(c2, first));
+#else
+ __disable_irq();
+ if ((cnt = *count) < size) {
+ *count = (U8)(cnt+1U);
+ c2 = (cnt = *first) + 1U;
+ if (c2 == size) { c2 = 0U; }
+ *first = (U8)c2;
+ }
+ __enable_irq ();
+#endif
+ return (cnt);
+}
+
+__inline static void rt_systick_init (void) {
+ NVIC_ST_RELOAD = os_trv;
+ NVIC_ST_CURRENT = 0U;
+ NVIC_ST_CTRL = 0x0007U;
+ NVIC_SYS_PRI3 |= 0xFF000000U;
+}
+
+__inline static U32 rt_systick_val (void) {
+ return (os_trv - NVIC_ST_CURRENT);
+}
+
+__inline static U32 rt_systick_ovf (void) {
+ return ((NVIC_INT_CTRL >> 26) & 1U);
+}
+
+__inline static void rt_svc_init (void) {
+#if !defined(__TARGET_ARCH_6S_M)
+ U32 sh,prigroup;
+#endif
+ NVIC_SYS_PRI3 |= 0x00FF0000U;
+#if defined(__TARGET_ARCH_6S_M)
+ NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000U;
+#else
+ sh = 8U - __clz(~((NVIC_SYS_PRI3 << 8) & 0xFF000000U));
+ prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07U);
+ if (prigroup >= sh) {
+ sh = prigroup + 1U;
+ }
+ NVIC_SYS_PRI2 = ((0xFEFFFFFFU << sh) & 0xFF000000U) | (NVIC_SYS_PRI2 & 0x00FFFFFFU);
+#endif
+}
+
+extern void rt_set_PSP (U32 stack);
+extern U32 rt_get_PSP (void);
+extern void os_set_env (void);
+extern void *_alloc_box (void *box_mem);
+extern U32 _free_box (void *box_mem, void *box);
+
+extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
+extern void rt_ret_val (P_TCB p_TCB, U32 v0);
+extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
+
+extern void dbg_init (void);
+extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
+extern void dbg_task_switch (U32 task_id);
+
+#ifdef DBG_MSG
+#define DBG_INIT() dbg_init()
+#define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new!=os_tsk.run)) \
+ dbg_task_switch(task_id)
+#else
+#define DBG_INIT()
+#define DBG_TASK_NOTIFY(p_tcb,create)
+#define DBG_TASK_SWITCH(task_id)
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_List.c b/CMSIS/RTOS/RTX/SRC/rt_List.c
new file mode 100644
index 0000000..40bb09a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_List.c
@@ -0,0 +1,318 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_LIST.C
+ * Purpose: Functions for the management of different lists
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* List head of chained ready tasks */
+struct OS_XCB os_rdy;
+/* List head of chained delay tasks */
+struct OS_XCB os_dly;
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_put_prio -----------------------------------*/
+
+void rt_put_prio (P_XCB p_CB, P_TCB p_task) {
+ /* Put task identified with "p_task" into list ordered by priority. */
+ /* "p_CB" points to head of list; list has always an element at end with */
+ /* a priority less than "p_task->prio". */
+ P_TCB p_CB2;
+ U32 prio;
+ BOOL sem_mbx = __FALSE;
+
+ if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
+ sem_mbx = __TRUE;
+ }
+ prio = p_task->prio;
+ p_CB2 = p_CB->p_lnk;
+ /* Search for an entry in the list */
+ while ((p_CB2 != NULL) && (prio <= p_CB2->prio)) {
+ p_CB = (P_XCB)p_CB2;
+ p_CB2 = p_CB2->p_lnk;
+ }
+ /* Entry found, insert the task into the list */
+ p_task->p_lnk = p_CB2;
+ p_CB->p_lnk = p_task;
+ if (sem_mbx) {
+ if (p_CB2 != NULL) {
+ p_CB2->p_rlnk = p_task;
+ }
+ p_task->p_rlnk = (P_TCB)p_CB;
+ }
+ else {
+ p_task->p_rlnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_get_first ----------------------------------*/
+
+P_TCB rt_get_first (P_XCB p_CB) {
+ /* Get task at head of list: it is the task with highest priority. */
+ /* "p_CB" points to head of list. */
+ P_TCB p_first;
+
+ p_first = p_CB->p_lnk;
+ p_CB->p_lnk = p_first->p_lnk;
+ if ((p_CB->cb_type == SCB) || (p_CB->cb_type == MCB) || (p_CB->cb_type == MUCB)) {
+ if (p_first->p_lnk != NULL) {
+ p_first->p_lnk->p_rlnk = (P_TCB)p_CB;
+ p_first->p_lnk = NULL;
+ }
+ p_first->p_rlnk = NULL;
+ }
+ else {
+ p_first->p_lnk = NULL;
+ }
+ return (p_first);
+}
+
+
+/*--------------------------- rt_put_rdy_first ------------------------------*/
+
+void rt_put_rdy_first (P_TCB p_task) {
+ /* Put task identified with "p_task" at the head of the ready list. The */
+ /* task must have at least a priority equal to highest priority in list. */
+ p_task->p_lnk = os_rdy.p_lnk;
+ p_task->p_rlnk = NULL;
+ os_rdy.p_lnk = p_task;
+}
+
+
+/*--------------------------- rt_get_same_rdy_prio --------------------------*/
+
+P_TCB rt_get_same_rdy_prio (void) {
+ /* Remove a task of same priority from ready list if any exists. Other- */
+ /* wise return NULL. */
+ P_TCB p_first;
+
+ p_first = os_rdy.p_lnk;
+ if (p_first->prio == os_tsk.run->prio) {
+ os_rdy.p_lnk = os_rdy.p_lnk->p_lnk;
+ return (p_first);
+ }
+ return (NULL);
+}
+
+
+/*--------------------------- rt_resort_prio --------------------------------*/
+
+void rt_resort_prio (P_TCB p_task) {
+ /* Re-sort ordered lists after the priority of 'p_task' has changed. */
+ P_TCB p_CB;
+
+ if (p_task->p_rlnk == NULL) {
+ if (p_task->state == READY) {
+ /* Task is chained into READY list. */
+ p_CB = (P_TCB)&os_rdy;
+ goto res;
+ }
+ }
+ else {
+ p_CB = p_task->p_rlnk;
+ while (p_CB->cb_type == TCB) {
+ /* Find a header of this task chain list. */
+ p_CB = p_CB->p_rlnk;
+ }
+res:rt_rmv_list (p_task);
+ rt_put_prio ((P_XCB)p_CB, p_task);
+ }
+}
+
+
+/*--------------------------- rt_put_dly ------------------------------------*/
+
+void rt_put_dly (P_TCB p_task, U16 delay) {
+ /* Put a task identified with "p_task" into chained delay wait list using */
+ /* a delay value of "delay". */
+ P_TCB p;
+ U32 delta,idelay = delay;
+
+ p = (P_TCB)&os_dly;
+ if (p->p_dlnk == NULL) {
+ /* Delay list empty */
+ delta = 0U;
+ goto last;
+ }
+ delta = os_dly.delta_time;
+ while (delta < idelay) {
+ if (p->p_dlnk == NULL) {
+ /* End of list found */
+last: p_task->p_dlnk = NULL;
+ p->p_dlnk = p_task;
+ p_task->p_blnk = p;
+ p->delta_time = (U16)(idelay - delta);
+ p_task->delta_time = 0U;
+ return;
+ }
+ p = p->p_dlnk;
+ delta += p->delta_time;
+ }
+ /* Right place found */
+ p_task->p_dlnk = p->p_dlnk;
+ p->p_dlnk = p_task;
+ p_task->p_blnk = p;
+ if (p_task->p_dlnk != NULL) {
+ p_task->p_dlnk->p_blnk = p_task;
+ }
+ p_task->delta_time = (U16)(delta - idelay);
+ p->delta_time -= p_task->delta_time;
+}
+
+
+/*--------------------------- rt_dec_dly ------------------------------------*/
+
+void rt_dec_dly (void) {
+ /* Decrement delta time of list head: remove tasks having a value of zero.*/
+ P_TCB p_rdy;
+
+ if (os_dly.p_dlnk == NULL) {
+ return;
+ }
+ os_dly.delta_time--;
+ while ((os_dly.delta_time == 0U) && (os_dly.p_dlnk != NULL)) {
+ p_rdy = os_dly.p_dlnk;
+ if (p_rdy->p_rlnk != NULL) {
+ /* Task is really enqueued, remove task from semaphore/mailbox */
+ /* timeout waiting list. */
+ p_rdy->p_rlnk->p_lnk = p_rdy->p_lnk;
+ if (p_rdy->p_lnk != NULL) {
+ p_rdy->p_lnk->p_rlnk = p_rdy->p_rlnk;
+ p_rdy->p_lnk = NULL;
+ }
+ p_rdy->p_rlnk = NULL;
+ }
+ rt_put_prio (&os_rdy, p_rdy);
+ os_dly.delta_time = p_rdy->delta_time;
+ if (p_rdy->state == WAIT_ITV) {
+ /* Calculate the next time for interval wait. */
+ p_rdy->delta_time = p_rdy->interval_time + (U16)os_time;
+ }
+ p_rdy->state = READY;
+ os_dly.p_dlnk = p_rdy->p_dlnk;
+ if (p_rdy->p_dlnk != NULL) {
+ p_rdy->p_dlnk->p_blnk = (P_TCB)&os_dly;
+ p_rdy->p_dlnk = NULL;
+ }
+ p_rdy->p_blnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_rmv_list -----------------------------------*/
+
+void rt_rmv_list (P_TCB p_task) {
+ /* Remove task identified with "p_task" from ready, semaphore or mailbox */
+ /* waiting list if enqueued. */
+ P_TCB p_b;
+
+ if (p_task->p_rlnk != NULL) {
+ /* A task is enqueued in semaphore / mailbox waiting list. */
+ p_task->p_rlnk->p_lnk = p_task->p_lnk;
+ if (p_task->p_lnk != NULL) {
+ p_task->p_lnk->p_rlnk = p_task->p_rlnk;
+ }
+ return;
+ }
+
+ p_b = (P_TCB)&os_rdy;
+ while (p_b != NULL) {
+ /* Search the ready list for task "p_task" */
+ if (p_b->p_lnk == p_task) {
+ p_b->p_lnk = p_task->p_lnk;
+ return;
+ }
+ p_b = p_b->p_lnk;
+ }
+}
+
+
+/*--------------------------- rt_rmv_dly ------------------------------------*/
+
+void rt_rmv_dly (P_TCB p_task) {
+ /* Remove task identified with "p_task" from delay list if enqueued. */
+ P_TCB p_b;
+
+ p_b = p_task->p_blnk;
+ if (p_b != NULL) {
+ /* Task is really enqueued */
+ p_b->p_dlnk = p_task->p_dlnk;
+ if (p_task->p_dlnk != NULL) {
+ /* 'p_task' is in the middle of list */
+ p_b->delta_time += p_task->delta_time;
+ p_task->p_dlnk->p_blnk = p_b;
+ p_task->p_dlnk = NULL;
+ }
+ else {
+ /* 'p_task' is at the end of list */
+ p_b->delta_time = 0U;
+ }
+ p_task->p_blnk = NULL;
+ }
+}
+
+
+/*--------------------------- rt_psq_enq ------------------------------------*/
+
+void rt_psq_enq (OS_ID entry, U32 arg) {
+ /* Insert post service request "entry" into ps-queue. */
+ U32 idx;
+
+ idx = rt_inc_qi (os_psq->size, &os_psq->count, &os_psq->first);
+ if (idx < os_psq->size) {
+ os_psq->q[idx].id = entry;
+ os_psq->q[idx].arg = arg;
+ }
+ else {
+ os_error (OS_ERR_FIFO_OVF);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_List.h b/CMSIS/RTOS/RTX/SRC/rt_List.h
new file mode 100644
index 0000000..e60bb4d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_List.h
@@ -0,0 +1,65 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_LIST.H
+ * Purpose: Functions for the management of different lists
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+
+/* Values for 'cb_type' */
+#define TCB 0U
+#define MCB 1U
+#define SCB 2U
+#define MUCB 3U
+#define HCB 4U
+
+/* Variables */
+extern struct OS_XCB os_rdy;
+extern struct OS_XCB os_dly;
+
+/* Functions */
+extern void rt_put_prio (P_XCB p_CB, P_TCB p_task);
+extern P_TCB rt_get_first (P_XCB p_CB);
+extern void rt_put_rdy_first (P_TCB p_task);
+extern P_TCB rt_get_same_rdy_prio (void);
+extern void rt_resort_prio (P_TCB p_task);
+extern void rt_put_dly (P_TCB p_task, U16 delay);
+extern void rt_dec_dly (void);
+extern void rt_rmv_list (P_TCB p_task);
+extern void rt_rmv_dly (P_TCB p_task);
+extern void rt_psq_enq (OS_ID entry, U32 arg);
+
+/* This is a fast macro generating in-line code */
+#define rt_rdy_prio(void) (os_rdy.p_lnk->prio)
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Mailbox.c b/CMSIS/RTOS/RTX/SRC/rt_Mailbox.c
new file mode 100644
index 0000000..6f906dc
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Mailbox.c
@@ -0,0 +1,293 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MAILBOX.C
+ * Purpose: Implements waits and wake-ups for mailbox messages
+ * Rev.: V4.81
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_MemBox.h"
+#include "rt_Task.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mbx_init -----------------------------------*/
+
+void rt_mbx_init (OS_ID mailbox, U16 mbx_size) {
+ /* Initialize a mailbox */
+ P_MCB p_MCB = mailbox;
+
+ p_MCB->cb_type = MCB;
+ p_MCB->state = 0U;
+ p_MCB->isr_st = 0U;
+ p_MCB->p_lnk = NULL;
+ p_MCB->first = 0U;
+ p_MCB->last = 0U;
+ p_MCB->count = 0U;
+ p_MCB->size = (U16)((mbx_size - (sizeof(struct OS_MCB) - (sizeof(void *))))
+ / sizeof(void *));
+}
+
+
+/*--------------------------- rt_mbx_send -----------------------------------*/
+
+OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout) {
+ /* Send message to a mailbox */
+ P_MCB p_MCB = mailbox;
+ P_TCB p_TCB;
+
+ if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 1U)) {
+ /* A task is waiting for message */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
+#else
+ *p_TCB->msg = p_msg;
+ rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ }
+ else {
+ /* Store message in mailbox queue */
+ if (p_MCB->count == p_MCB->size) {
+ /* No free message entry, wait for one. If message queue is full, */
+ /* then no task is waiting for message. The 'p_MCB->p_lnk' list */
+ /* pointer can now be reused for send message waits task list. */
+ if (timeout == 0U) {
+ return (OS_R_TMO);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ /* Task is waiting to send a message */
+ p_MCB->state = 2U;
+ }
+ os_tsk.run->msg = p_msg;
+ rt_block (timeout, WAIT_MBX);
+ return (OS_R_TMO);
+ }
+ /* Yes, there is a free entry in a mailbox. */
+ p_MCB->msg[p_MCB->first] = p_msg;
+ rt_inc (&p_MCB->count);
+ if (++p_MCB->first == p_MCB->size) {
+ p_MCB->first = 0U;
+ }
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_wait -----------------------------------*/
+
+OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout) {
+ /* Receive a message; possibly wait for it */
+ P_MCB p_MCB = mailbox;
+ P_TCB p_TCB;
+
+ /* If a message is available in the fifo buffer */
+ /* remove it from the fifo buffer and return. */
+ if (p_MCB->count) {
+ *message = p_MCB->msg[p_MCB->last];
+ if (++p_MCB->last == p_MCB->size) {
+ p_MCB->last = 0U;
+ }
+ if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {
+ /* A task is waiting to send message */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val(p_TCB, 0U/*osOK*/);
+#else
+ rt_ret_val(p_TCB, OS_R_OK);
+#endif
+ p_MCB->msg[p_MCB->first] = p_TCB->msg;
+ if (++p_MCB->first == p_MCB->size) {
+ p_MCB->first = 0U;
+ }
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ }
+ else {
+ rt_dec (&p_MCB->count);
+ }
+ return (OS_R_OK);
+ }
+ /* No message available: wait for one */
+ if (timeout == 0U) {
+ return (OS_R_TMO);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ /* Task is waiting to receive a message */
+ p_MCB->state = 1U;
+ }
+ rt_block(timeout, WAIT_MBX);
+#ifndef __CMSIS_RTOS
+ os_tsk.run->msg = message;
+#endif
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- rt_mbx_check ----------------------------------*/
+
+OS_RESULT rt_mbx_check (OS_ID mailbox) {
+ /* Check for free space in a mailbox. Returns the number of messages */
+ /* that can be stored to a mailbox. It returns 0 when mailbox is full. */
+ P_MCB p_MCB = mailbox;
+
+ return ((U32)(p_MCB->size - p_MCB->count));
+}
+
+
+/*--------------------------- isr_mbx_send ----------------------------------*/
+
+void isr_mbx_send (OS_ID mailbox, void *p_msg) {
+ /* Same function as "os_mbx_send", but to be called by ISRs. */
+ P_MCB p_MCB = mailbox;
+
+ rt_psq_enq (p_MCB, (U32)p_msg);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- isr_mbx_receive -------------------------------*/
+
+OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message) {
+ /* Receive a message in the interrupt function. The interrupt function */
+ /* should not wait for a message since this would block the rtx os. */
+ P_MCB p_MCB = mailbox;
+
+ if (p_MCB->count) {
+ /* A message is available in the fifo buffer. */
+ *message = p_MCB->msg[p_MCB->last];
+ if ((p_MCB->p_lnk != NULL) && (p_MCB->state == 2U)) {
+ /* A task is locked waiting to send message */
+ rt_psq_enq (p_MCB, 0U);
+ rt_psh_req ();
+ }
+ rt_dec (&p_MCB->count);
+ if (++p_MCB->last == p_MCB->size) {
+ p_MCB->last = 0U;
+ }
+ return (OS_R_MBX);
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mbx_psh ------------------------------------*/
+
+void rt_mbx_psh (P_MCB p_CB, void *p_msg) {
+ /* Store the message to the mailbox queue or pass it to task directly. */
+ P_TCB p_TCB;
+ void *mem;
+
+ if (p_CB->p_lnk != NULL) switch (p_CB->state) {
+#ifdef __CMSIS_RTOS
+ case 3:
+ /* Task is waiting to allocate memory, remove it from the waiting list */
+ mem = rt_alloc_box(p_msg);
+ if (mem == NULL) { break; }
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+ rt_ret_val(p_TCB, (U32)mem);
+ p_TCB->state = READY;
+ rt_rmv_dly (p_TCB);
+ rt_put_prio (&os_rdy, p_TCB);
+ break;
+#endif
+ case 2:
+ /* Task is waiting to send a message, remove it from the waiting list */
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val(p_TCB, 0U/*osOK*/);
+#else
+ rt_ret_val(p_TCB, OS_R_OK);
+#endif
+ p_CB->msg[p_CB->first] = p_TCB->msg;
+ rt_inc (&p_CB->count);
+ if (++p_CB->first == p_CB->size) {
+ p_CB->first = 0U;
+ }
+ p_TCB->state = READY;
+ rt_rmv_dly (p_TCB);
+ rt_put_prio (&os_rdy, p_TCB);
+ break;
+ case 1:
+ /* Task is waiting for a message, pass the message to the task directly */
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val2(p_TCB, 0x10U/*osEventMessage*/, (U32)p_msg);
+#else
+ *p_TCB->msg = p_msg;
+ rt_ret_val (p_TCB, OS_R_MBX);
+#endif
+ p_TCB->state = READY;
+ rt_rmv_dly (p_TCB);
+ rt_put_prio (&os_rdy, p_TCB);
+ break;
+ default:
+ break;
+ } else {
+ /* No task is waiting for a message, store it to the mailbox queue */
+ if (p_CB->count < p_CB->size) {
+ p_CB->msg[p_CB->first] = p_msg;
+ rt_inc (&p_CB->count);
+ if (++p_CB->first == p_CB->size) {
+ p_CB->first = 0U;
+ }
+ }
+ else {
+ os_error (OS_ERR_MBX_OVF);
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Mailbox.h b/CMSIS/RTOS/RTX/SRC/rt_Mailbox.h
new file mode 100644
index 0000000..346d708
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Mailbox.h
@@ -0,0 +1,46 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MAILBOX.H
+ * Purpose: Implements waits and wake-ups for mailbox messages
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void rt_mbx_init (OS_ID mailbox, U16 mbx_size);
+extern OS_RESULT rt_mbx_send (OS_ID mailbox, void *p_msg, U16 timeout);
+extern OS_RESULT rt_mbx_wait (OS_ID mailbox, void **message, U16 timeout);
+extern OS_RESULT rt_mbx_check (OS_ID mailbox);
+extern void isr_mbx_send (OS_ID mailbox, void *p_msg);
+extern OS_RESULT isr_mbx_receive (OS_ID mailbox, void **message);
+extern void rt_mbx_psh (P_MCB p_CB, void *p_msg);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_MemBox.c b/CMSIS/RTOS/RTX/SRC/rt_MemBox.c
new file mode 100644
index 0000000..01d1e22
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_MemBox.c
@@ -0,0 +1,168 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MEMBOX.C
+ * Purpose: Interface functions for fixed memory block management system
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_MemBox.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- _init_box -------------------------------------*/
+
+U32 _init_box (void *box_mem, U32 box_size, U32 blk_size) {
+ /* Initialize memory block system, returns 0 if OK, 1 if fails. */
+ void *end;
+ void *blk;
+ void *next;
+ U32 sizeof_bm;
+
+ /* Create memory structure. */
+ if (blk_size & BOX_ALIGN_8) {
+ /* Memory blocks 8-byte aligned. */
+ blk_size = ((blk_size & ~BOX_ALIGN_8) + 7U) & ~(U32)7U;
+ sizeof_bm = (sizeof (struct OS_BM) + 7U) & ~(U32)7U;
+ }
+ else {
+ /* Memory blocks 4-byte aligned. */
+ blk_size = (blk_size + 3U) & ~(U32)3U;
+ sizeof_bm = sizeof (struct OS_BM);
+ }
+ if (blk_size == 0U) {
+ return (1U);
+ }
+ if ((blk_size + sizeof_bm) > box_size) {
+ return (1U);
+ }
+ /* Create a Memory structure. */
+ blk = ((U8 *) box_mem) + sizeof_bm;
+ ((P_BM) box_mem)->free = blk;
+ end = ((U8 *) box_mem) + box_size;
+ ((P_BM) box_mem)->end = end;
+ ((P_BM) box_mem)->blk_size = blk_size;
+
+ /* Link all free blocks using offsets. */
+ end = ((U8 *) end) - blk_size;
+ while (1) {
+ next = ((U8 *) blk) + blk_size;
+ if (next > end) { break; }
+ *((void **)blk) = next;
+ blk = next;
+ }
+ /* end marker */
+ *((void **)blk) = 0U;
+ return (0U);
+}
+
+/*--------------------------- rt_alloc_box ----------------------------------*/
+
+void *rt_alloc_box (void *box_mem) {
+ /* Allocate a memory block and return start address. */
+ void **free;
+#ifndef __USE_EXCLUSIVE_ACCESS
+ U32 irq_mask;
+
+ irq_mask = (U32)__disable_irq ();
+ free = ((P_BM) box_mem)->free;
+ if (free) {
+ ((P_BM) box_mem)->free = *free;
+ }
+ if (irq_mask == 0U) { __enable_irq (); }
+#else
+ do {
+ if ((free = (void **)__ldrex(&((P_BM) box_mem)->free)) == 0U) {
+ __clrex();
+ break;
+ }
+ } while (__strex((U32)*free, &((P_BM) box_mem)->free));
+#endif
+ return (free);
+}
+
+
+/*--------------------------- _calloc_box -----------------------------------*/
+
+void *_calloc_box (void *box_mem) {
+ /* Allocate a 0-initialized memory block and return start address. */
+ void *free;
+ U32 *p;
+ U32 i;
+
+ free = _alloc_box (box_mem);
+ if (free) {
+ p = free;
+ for (i = ((P_BM) box_mem)->blk_size; i; i -= 4U) {
+ *p = 0U;
+ p++;
+ }
+ }
+ return (free);
+}
+
+
+/*--------------------------- rt_free_box -----------------------------------*/
+
+U32 rt_free_box (void *box_mem, void *box) {
+ /* Free a memory block, returns 0 if OK, 1 if box does not belong to box_mem */
+#ifndef __USE_EXCLUSIVE_ACCESS
+ U32 irq_mask;
+#endif
+
+ if ((box < box_mem) || (box >= ((P_BM) box_mem)->end)) {
+ return (1U);
+ }
+
+#ifndef __USE_EXCLUSIVE_ACCESS
+ irq_mask = (U32)__disable_irq ();
+ *((void **)box) = ((P_BM) box_mem)->free;
+ ((P_BM) box_mem)->free = box;
+ if (irq_mask == 0U) { __enable_irq (); }
+#else
+ do {
+ do {
+ *((void **)box) = ((P_BM) box_mem)->free;
+ __DMB();
+ } while (*(void**)box != (void *)__ldrex(&((P_BM) box_mem)->free));
+ } while (__strex ((U32)box, &((P_BM) box_mem)->free));
+#endif
+ return (0U);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_MemBox.h b/CMSIS/RTOS/RTX/SRC/rt_MemBox.h
new file mode 100644
index 0000000..c9d7e7c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_MemBox.h
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MEMBOX.H
+ * Purpose: Interface functions for fixed memory block management system
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+#define rt_init_box _init_box
+#define rt_calloc_box _calloc_box
+extern U32 _init_box (void *box_mem, U32 box_size, U32 blk_size);
+extern void *rt_alloc_box (void *box_mem);
+extern void * _calloc_box (void *box_mem);
+extern U32 rt_free_box (void *box_mem, void *box);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Memory.c b/CMSIS/RTOS/RTX/SRC/rt_Memory.c
new file mode 100644
index 0000000..b0079b5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Memory.c
@@ -0,0 +1,140 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MEMORY.C
+ * Purpose: Interface functions for Dynamic Memory Management System
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "rt_Memory.h"
+
+
+/* Functions */
+
+// Initialize Dynamic Memory pool
+// Parameters:
+// pool: Pointer to memory pool
+// size: Size of memory pool in bytes
+// Return: 0 - OK, 1 - Error
+
+U32 rt_init_mem (void *pool, U32 size) {
+ MEMP *ptr;
+
+ if ((pool == NULL) || (size < sizeof(MEMP))) { return (1U); }
+
+ ptr = (MEMP *)pool;
+ ptr->next = (MEMP *)((U32)pool + size - sizeof(MEMP *));
+ ptr->next->next = NULL;
+ ptr->len = 0U;
+
+ return (0U);
+}
+
+// Allocate Memory from Memory pool
+// Parameters:
+// pool: Pointer to memory pool
+// size: Size of memory in bytes to allocate
+// Return: Pointer to allocated memory
+
+void *rt_alloc_mem (void *pool, U32 size) {
+ MEMP *p, *p_search, *p_new;
+ U32 hole_size;
+
+ if ((pool == NULL) || (size == 0U)) { return NULL; }
+
+ /* Add header offset to 'size' */
+ size += sizeof(MEMP);
+ /* Make sure that block is 4-byte aligned */
+ size = (size + 3U) & ~(U32)3U;
+
+ p_search = (MEMP *)pool;
+ while (1) {
+ hole_size = (U32)p_search->next - (U32)p_search;
+ hole_size -= p_search->len;
+ /* Check if hole size is big enough */
+ if (hole_size >= size) { break; }
+ p_search = p_search->next;
+ if (p_search->next == NULL) {
+ /* Failed, we are at the end of the list */
+ return NULL;
+ }
+ }
+
+ if (p_search->len == 0U) {
+ /* No block is allocated, set the Length of the first element */
+ p_search->len = size;
+ p = (MEMP *)(((U32)p_search) + sizeof(MEMP));
+ } else {
+ /* Insert new list element into the memory list */
+ p_new = (MEMP *)((U32)p_search + p_search->len);
+ p_new->next = p_search->next;
+ p_new->len = size;
+ p_search->next = p_new;
+ p = (MEMP *)(((U32)p_new) + sizeof(MEMP));
+ }
+
+ return (p);
+}
+
+// Free Memory and return it to Memory pool
+// Parameters:
+// pool: Pointer to memory pool
+// mem: Pointer to memory to free
+// Return: 0 - OK, 1 - Error
+
+U32 rt_free_mem (void *pool, void *mem) {
+ MEMP *p_search, *p_prev, *p_return;
+
+ if ((pool == NULL) || (mem == NULL)) { return (1U); }
+
+ p_return = (MEMP *)((U32)mem - sizeof(MEMP));
+
+ /* Set list header */
+ p_prev = NULL;
+ p_search = (MEMP *)pool;
+ while (p_search != p_return) {
+ p_prev = p_search;
+ p_search = p_search->next;
+ if (p_search == NULL) {
+ /* Valid Memory block not found */
+ return (1U);
+ }
+ }
+
+ if (p_prev == NULL) {
+ /* First block to be released, only set length to 0 */
+ p_search->len = 0U;
+ } else {
+ /* Discard block from chain list */
+ p_prev->next = p_search->next;
+ }
+
+ return (0U);
+}
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Memory.h b/CMSIS/RTOS/RTX/SRC/rt_Memory.h
new file mode 100644
index 0000000..da881e5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Memory.h
@@ -0,0 +1,44 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MEMORY.H
+ * Purpose: Interface functions for Dynamic Memory Management System
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Types */
+typedef struct mem { /* << Memory Pool management struct >> */
+ struct mem *next; /* Next Memory Block in the list */
+ U32 len; /* Length of data block */
+} MEMP;
+
+/* Functions */
+extern U32 rt_init_mem (void *pool, U32 size);
+extern void *rt_alloc_mem (void *pool, U32 size);
+extern U32 rt_free_mem (void *pool, void *mem);
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Mutex.c b/CMSIS/RTOS/RTX/SRC/rt_Mutex.c
new file mode 100644
index 0000000..de92ddd
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Mutex.c
@@ -0,0 +1,257 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MUTEX.C
+ * Purpose: Implements mutex synchronization objects
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Mutex.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_mut_init -----------------------------------*/
+
+void rt_mut_init (OS_ID mutex) {
+ /* Initialize a mutex object */
+ P_MUCB p_MCB = mutex;
+
+ p_MCB->cb_type = MUCB;
+ p_MCB->level = 0U;
+ p_MCB->p_lnk = NULL;
+ p_MCB->owner = NULL;
+ p_MCB->p_mlnk = NULL;
+}
+
+
+/*--------------------------- rt_mut_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_mut_delete (OS_ID mutex) {
+ /* Delete a mutex object */
+ P_MUCB p_MCB = mutex;
+ P_TCB p_TCB;
+ P_MUCB p_mlnk;
+ U8 prio;
+
+ if (p_MCB->level != 0U) {
+
+ p_TCB = p_MCB->owner;
+
+ /* Remove mutex from task mutex owner list. */
+ p_mlnk = p_TCB->p_mlnk;
+ if (p_mlnk == p_MCB) {
+ p_TCB->p_mlnk = p_MCB->p_mlnk;
+ }
+ else {
+ while (p_mlnk) {
+ if (p_mlnk->p_mlnk == p_MCB) {
+ p_mlnk->p_mlnk = p_MCB->p_mlnk;
+ break;
+ }
+ p_mlnk = p_mlnk->p_mlnk;
+ }
+ }
+
+ /* Restore owner task's priority. */
+ prio = p_TCB->prio_base;
+ p_mlnk = p_TCB->p_mlnk;
+ while (p_mlnk) {
+ if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
+ /* A task with higher priority is waiting for mutex. */
+ prio = p_mlnk->p_lnk->prio;
+ }
+ p_mlnk = p_mlnk->p_mlnk;
+ }
+ if (p_TCB->prio != prio) {
+ p_TCB->prio = prio;
+ if (p_TCB != os_tsk.run) {
+ rt_resort_prio (p_TCB);
+ }
+ }
+
+ }
+
+ while (p_MCB->p_lnk != NULL) {
+ /* A task is waiting for mutex. */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+ rt_ret_val(p_TCB, 0U/*osOK*/);
+ rt_rmv_dly(p_TCB);
+ p_TCB->state = READY;
+ rt_put_prio (&os_rdy, p_TCB);
+ }
+
+ if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+ /* preempt running task */
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_dispatch (NULL);
+ }
+
+ p_MCB->cb_type = 0U;
+
+ return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_mut_release --------------------------------*/
+
+OS_RESULT rt_mut_release (OS_ID mutex) {
+ /* Release a mutex object */
+ P_MUCB p_MCB = mutex;
+ P_TCB p_TCB;
+ P_MUCB p_mlnk;
+ U8 prio;
+
+ if ((p_MCB->level == 0U) || (p_MCB->owner != os_tsk.run)) {
+ /* Unbalanced mutex release or task is not the owner */
+ return (OS_R_NOK);
+ }
+ if (--p_MCB->level != 0U) {
+ return (OS_R_OK);
+ }
+
+ /* Remove mutex from task mutex owner list. */
+ p_mlnk = os_tsk.run->p_mlnk;
+ if (p_mlnk == p_MCB) {
+ os_tsk.run->p_mlnk = p_MCB->p_mlnk;
+ }
+ else {
+ while (p_mlnk) {
+ if (p_mlnk->p_mlnk == p_MCB) {
+ p_mlnk->p_mlnk = p_MCB->p_mlnk;
+ break;
+ }
+ p_mlnk = p_mlnk->p_mlnk;
+ }
+ }
+
+ /* Restore owner task's priority. */
+ prio = os_tsk.run->prio_base;
+ p_mlnk = os_tsk.run->p_mlnk;
+ while (p_mlnk) {
+ if ((p_mlnk->p_lnk != NULL) && (p_mlnk->p_lnk->prio > prio)) {
+ /* A task with higher priority is waiting for mutex. */
+ prio = p_mlnk->p_lnk->prio;
+ }
+ p_mlnk = p_mlnk->p_mlnk;
+ }
+ os_tsk.run->prio = prio;
+
+ if (p_MCB->p_lnk != NULL) {
+ /* A task is waiting for mutex. */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val(p_TCB, 0U/*osOK*/);
+#else
+ rt_ret_val(p_TCB, OS_R_MUT);
+#endif
+ rt_rmv_dly (p_TCB);
+ /* A waiting task becomes the owner of this mutex. */
+ p_MCB->level = 1U;
+ p_MCB->owner = p_TCB;
+ p_MCB->p_mlnk = p_TCB->p_mlnk;
+ p_TCB->p_mlnk = p_MCB;
+ /* Priority inversion, check which task continues. */
+ if (os_tsk.run->prio >= rt_rdy_prio()) {
+ rt_dispatch (p_TCB);
+ }
+ else {
+ /* Ready task has higher priority than running task. */
+ rt_put_prio (&os_rdy, os_tsk.run);
+ rt_put_prio (&os_rdy, p_TCB);
+ os_tsk.run->state = READY;
+ p_TCB->state = READY;
+ rt_dispatch (NULL);
+ }
+ }
+ else {
+ /* Check if own priority lowered by priority inversion. */
+ if (rt_rdy_prio() > os_tsk.run->prio) {
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_dispatch (NULL);
+ }
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_mut_wait -----------------------------------*/
+
+OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout) {
+ /* Wait for a mutex, continue when mutex is free. */
+ P_MUCB p_MCB = mutex;
+
+ if (p_MCB->level == 0U) {
+ p_MCB->owner = os_tsk.run;
+ p_MCB->p_mlnk = os_tsk.run->p_mlnk;
+ os_tsk.run->p_mlnk = p_MCB;
+ goto inc;
+ }
+ if (p_MCB->owner == os_tsk.run) {
+ /* OK, running task is the owner of this mutex. */
+inc:p_MCB->level++;
+ return (OS_R_OK);
+ }
+ /* Mutex owned by another task, wait until released. */
+ if (timeout == 0U) {
+ return (OS_R_TMO);
+ }
+ /* Raise the owner task priority if lower than current priority. */
+ /* This priority inversion is called priority inheritance. */
+ if (p_MCB->owner->prio < os_tsk.run->prio) {
+ p_MCB->owner->prio = os_tsk.run->prio;
+ rt_resort_prio (p_MCB->owner);
+ }
+ if (p_MCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_MCB, os_tsk.run);
+ }
+ else {
+ p_MCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_MCB;
+ }
+ rt_block(timeout, WAIT_MUT);
+ return (OS_R_TMO);
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Mutex.h b/CMSIS/RTOS/RTX/SRC/rt_Mutex.h
new file mode 100644
index 0000000..15383c1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Mutex.h
@@ -0,0 +1,43 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_MUTEX.H
+ * Purpose: Implements mutex synchronization objects
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void rt_mut_init (OS_ID mutex);
+extern OS_RESULT rt_mut_delete (OS_ID mutex);
+extern OS_RESULT rt_mut_release (OS_ID mutex);
+extern OS_RESULT rt_mut_wait (OS_ID mutex, U16 timeout);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Robin.c b/CMSIS/RTOS/RTX/SRC/rt_Robin.c
new file mode 100644
index 0000000..5ba1c4e
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Robin.c
@@ -0,0 +1,83 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_ROBIN.C
+ * Purpose: Round Robin Task switching
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+struct OS_ROBIN os_robin;
+
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_init_robin ---------------------------------*/
+
+__weak void rt_init_robin (void) {
+ /* Initialize Round Robin variables. */
+ os_robin.task = NULL;
+ os_robin.tout = (U16)os_rrobin;
+}
+
+/*--------------------------- rt_chk_robin ----------------------------------*/
+
+__weak void rt_chk_robin (void) {
+ /* Check if Round Robin timeout expired and switch to the next ready task.*/
+ P_TCB p_new;
+
+ if (os_robin.task != os_rdy.p_lnk) {
+ /* New task was suspended, reset Round Robin timeout. */
+ os_robin.task = os_rdy.p_lnk;
+ os_robin.time = (U16)os_time + os_robin.tout - 1U;
+ }
+ if (os_robin.time == (U16)os_time) {
+ /* Round Robin timeout has expired, swap Robin tasks. */
+ os_robin.task = NULL;
+ p_new = rt_get_first (&os_rdy);
+ rt_put_prio ((P_XCB)&os_rdy, p_new);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Robin.h b/CMSIS/RTOS/RTX/SRC/rt_Robin.h
new file mode 100644
index 0000000..13bba5f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Robin.h
@@ -0,0 +1,44 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_ROBIN.H
+ * Purpose: Round Robin Task switching definitions
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern struct OS_ROBIN os_robin;
+
+/* Functions */
+extern void rt_init_robin (void);
+extern void rt_chk_robin (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Semaphore.c b/CMSIS/RTOS/RTX/SRC/rt_Semaphore.c
new file mode 100644
index 0000000..65a1903
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Semaphore.c
@@ -0,0 +1,182 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_SEMAPHORE.C
+ * Purpose: Implements binary and counting semaphores
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_List.h"
+#include "rt_Task.h"
+#include "rt_Semaphore.h"
+#include "rt_HAL_CM.h"
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_sem_init -----------------------------------*/
+
+void rt_sem_init (OS_ID semaphore, U16 token_count) {
+ /* Initialize a semaphore */
+ P_SCB p_SCB = semaphore;
+
+ p_SCB->cb_type = SCB;
+ p_SCB->p_lnk = NULL;
+ p_SCB->tokens = token_count;
+}
+
+
+/*--------------------------- rt_sem_delete ---------------------------------*/
+
+#ifdef __CMSIS_RTOS
+OS_RESULT rt_sem_delete (OS_ID semaphore) {
+ /* Delete semaphore */
+ P_SCB p_SCB = semaphore;
+ P_TCB p_TCB;
+
+ while (p_SCB->p_lnk != NULL) {
+ /* A task is waiting for token */
+ p_TCB = rt_get_first ((P_XCB)p_SCB);
+ rt_ret_val(p_TCB, 0U);
+ rt_rmv_dly(p_TCB);
+ p_TCB->state = READY;
+ rt_put_prio (&os_rdy, p_TCB);
+ }
+
+ if ((os_rdy.p_lnk != NULL) && (os_rdy.p_lnk->prio > os_tsk.run->prio)) {
+ /* preempt running task */
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_dispatch (NULL);
+ }
+
+ p_SCB->cb_type = 0U;
+
+ return (OS_R_OK);
+}
+#endif
+
+
+/*--------------------------- rt_sem_send -----------------------------------*/
+
+OS_RESULT rt_sem_send (OS_ID semaphore) {
+ /* Return a token to semaphore */
+ P_SCB p_SCB = semaphore;
+ P_TCB p_TCB;
+
+ if (p_SCB->p_lnk != NULL) {
+ /* A task is waiting for token */
+ p_TCB = rt_get_first ((P_XCB)p_SCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val(p_TCB, 1U);
+#else
+ rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+ rt_rmv_dly (p_TCB);
+ rt_dispatch (p_TCB);
+ }
+ else {
+ /* Store token. */
+ p_SCB->tokens++;
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sem_wait -----------------------------------*/
+
+OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout) {
+ /* Obtain a token; possibly wait for it */
+ P_SCB p_SCB = semaphore;
+
+ if (p_SCB->tokens) {
+ p_SCB->tokens--;
+ return (OS_R_OK);
+ }
+ /* No token available: wait for one */
+ if (timeout == 0U) {
+ return (OS_R_TMO);
+ }
+ if (p_SCB->p_lnk != NULL) {
+ rt_put_prio ((P_XCB)p_SCB, os_tsk.run);
+ }
+ else {
+ p_SCB->p_lnk = os_tsk.run;
+ os_tsk.run->p_lnk = NULL;
+ os_tsk.run->p_rlnk = (P_TCB)p_SCB;
+ }
+ rt_block(timeout, WAIT_SEM);
+ return (OS_R_TMO);
+}
+
+
+/*--------------------------- isr_sem_send ----------------------------------*/
+
+void isr_sem_send (OS_ID semaphore) {
+ /* Same function as "os_sem_send", but to be called by ISRs */
+ P_SCB p_SCB = semaphore;
+
+ rt_psq_enq (p_SCB, 0U);
+ rt_psh_req ();
+}
+
+
+/*--------------------------- rt_sem_psh ------------------------------------*/
+
+void rt_sem_psh (P_SCB p_CB) {
+ /* Check if task has to be waken up */
+ P_TCB p_TCB;
+
+ if (p_CB->p_lnk != NULL) {
+ /* A task is waiting for token */
+ p_TCB = rt_get_first ((P_XCB)p_CB);
+ rt_rmv_dly (p_TCB);
+ p_TCB->state = READY;
+#ifdef __CMSIS_RTOS
+ rt_ret_val(p_TCB, 1U);
+#else
+ rt_ret_val(p_TCB, OS_R_SEM);
+#endif
+ rt_put_prio (&os_rdy, p_TCB);
+ }
+ else {
+ /* Store token */
+ p_CB->tokens++;
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Semaphore.h b/CMSIS/RTOS/RTX/SRC/rt_Semaphore.h
new file mode 100644
index 0000000..8c18ffa
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Semaphore.h
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_SEMAPHORE.H
+ * Purpose: Implements binary and counting semaphores
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Functions */
+extern void rt_sem_init (OS_ID semaphore, U16 token_count);
+extern OS_RESULT rt_sem_delete(OS_ID semaphore);
+extern OS_RESULT rt_sem_send (OS_ID semaphore);
+extern OS_RESULT rt_sem_wait (OS_ID semaphore, U16 timeout);
+extern void isr_sem_send (OS_ID semaphore);
+extern void rt_sem_psh (P_SCB p_CB);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_System.c b/CMSIS/RTOS/RTX/SRC/rt_System.c
new file mode 100644
index 0000000..c7433fb
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_System.c
@@ -0,0 +1,325 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_SYSTEM.C
+ * Purpose: System Task Manager
+ * Rev.: V4.81
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_System.h"
+#include "rt_Event.h"
+#include "rt_List.h"
+#include "rt_Mailbox.h"
+#include "rt_Semaphore.h"
+#include "rt_Time.h"
+#include "rt_Timer.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+S32 os_tick_irqn;
+
+/*----------------------------------------------------------------------------
+ * Local Variables
+ *---------------------------------------------------------------------------*/
+
+static volatile BIT os_lock;
+static volatile BIT os_psh_flag;
+static U8 pend_flags;
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+#define RL_RTX_VER 0x481
+
+#if defined (__CC_ARM)
+__asm void $$RTX$$version (void) {
+ /* Export a version number symbol for a version control. */
+
+ EXPORT __RL_RTX_VER
+
+__RL_RTX_VER EQU RL_RTX_VER
+}
+#endif
+
+
+/*--------------------------- rt_suspend ------------------------------------*/
+
+extern U32 sysUserTimerWakeupTime(void);
+
+U32 rt_suspend (void) {
+ /* Suspend OS scheduler */
+ U32 delta = 0xFFFFU;
+#ifdef __CMSIS_RTOS
+ U32 sleep;
+#endif
+
+ rt_tsk_lock();
+
+ if (os_dly.p_dlnk) {
+ delta = os_dly.delta_time;
+ }
+#ifdef __CMSIS_RTOS
+ sleep = sysUserTimerWakeupTime();
+ if (sleep < delta) { delta = sleep; }
+#else
+ if (os_tmr.next) {
+ if (os_tmr.tcnt < delta) delta = os_tmr.tcnt;
+ }
+#endif
+
+ return (delta);
+}
+
+
+/*--------------------------- rt_resume -------------------------------------*/
+
+extern void sysUserTimerUpdate (U32 sleep_time);
+
+void rt_resume (U32 sleep_time) {
+ /* Resume OS scheduler after suspend */
+ P_TCB next;
+ U32 delta;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ os_robin.task = NULL;
+
+ /* Update delays. */
+ if (os_dly.p_dlnk) {
+ delta = sleep_time;
+ if (delta >= os_dly.delta_time) {
+ delta -= os_dly.delta_time;
+ os_time += os_dly.delta_time;
+ os_dly.delta_time = 1U;
+ while (os_dly.p_dlnk) {
+ rt_dec_dly();
+ if (delta == 0U) { break; }
+ delta--;
+ os_time++;
+ }
+ } else {
+ os_time += delta;
+ os_dly.delta_time -= (U16)delta;
+ }
+ } else {
+ os_time += sleep_time;
+ }
+
+ /* Check the user timers. */
+#ifdef __CMSIS_RTOS
+ sysUserTimerUpdate(sleep_time);
+#else
+ if (os_tmr.next) {
+ delta = sleep_time;
+ if (delta >= os_tmr.tcnt) {
+ delta -= os_tmr.tcnt;
+ os_tmr.tcnt = 1U;
+ while (os_tmr.next) {
+ rt_tmr_tick();
+ if (delta == 0U) { break; }
+ delta--;
+ }
+ } else {
+ os_tmr.tcnt -= delta;
+ }
+ }
+#endif
+
+ /* Switch back to highest ready task */
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+
+ rt_tsk_unlock();
+}
+
+
+/*--------------------------- rt_tsk_lock -----------------------------------*/
+
+void rt_tsk_lock (void) {
+ /* Prevent task switching by locking out scheduler */
+ if (os_tick_irqn < 0) {
+ OS_LOCK();
+ os_lock = __TRUE;
+ OS_UNPEND(pend_flags);
+ } else {
+ OS_X_LOCK((U32)os_tick_irqn);
+ os_lock = __TRUE;
+ OS_X_UNPEND(pend_flags);
+ }
+}
+
+
+/*--------------------------- rt_tsk_unlock ---------------------------------*/
+
+void rt_tsk_unlock (void) {
+ /* Unlock scheduler and re-enable task switching */
+ if (os_tick_irqn < 0) {
+ OS_UNLOCK();
+ os_lock = __FALSE;
+ OS_PEND(pend_flags, os_psh_flag);
+ os_psh_flag = __FALSE;
+ } else {
+ OS_X_UNLOCK((U32)os_tick_irqn);
+ os_lock = __FALSE;
+ OS_X_PEND(pend_flags, os_psh_flag);
+ os_psh_flag = __FALSE;
+ }
+}
+
+
+/*--------------------------- rt_psh_req ------------------------------------*/
+
+void rt_psh_req (void) {
+ /* Initiate a post service handling request if required. */
+ if (os_lock == __FALSE) {
+ OS_PEND_IRQ();
+ }
+ else {
+ os_psh_flag = __TRUE;
+ }
+}
+
+
+/*--------------------------- rt_pop_req ------------------------------------*/
+
+void rt_pop_req (void) {
+ /* Process an ISR post service requests. */
+ struct OS_XCB *p_CB;
+ P_TCB next;
+ U32 idx;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ idx = os_psq->last;
+ while (os_psq->count) {
+ p_CB = os_psq->q[idx].id;
+ if (p_CB->cb_type == TCB) {
+ /* Is of TCB type */
+ rt_evt_psh ((P_TCB)p_CB, (U16)os_psq->q[idx].arg);
+ }
+ else if (p_CB->cb_type == MCB) {
+ /* Is of MCB type */
+ rt_mbx_psh ((P_MCB)p_CB, (void *)os_psq->q[idx].arg);
+ }
+ else {
+ /* Must be of SCB type */
+ rt_sem_psh ((P_SCB)p_CB);
+ }
+ if (++idx == os_psq->size) { idx = 0U; }
+ rt_dec (&os_psq->count);
+ }
+ os_psq->last = (U8)idx;
+
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+}
+
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+__weak S32 os_tick_init (void) {
+ /* Initialize SysTick timer as system tick timer. */
+ rt_systick_init();
+ return (-1); /* Return IRQ number of SysTick timer */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+__weak U32 os_tick_val (void) {
+ /* Get SysTick timer current value (0 .. OS_TRV). */
+ return rt_systick_val();
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+__weak U32 os_tick_ovf (void) {
+ /* Get SysTick timer overflow flag */
+ return rt_systick_ovf();
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+__weak void os_tick_irqack (void) {
+ /* Acknowledge timer interrupt. */
+}
+
+
+/*--------------------------- rt_systick ------------------------------------*/
+
+extern void sysTimerTick(void);
+
+void rt_systick (void) {
+ /* Check for system clock update, suspend running task. */
+ P_TCB next;
+
+ os_tsk.run->state = READY;
+ rt_put_rdy_first (os_tsk.run);
+
+ /* Check Round Robin timeout. */
+ rt_chk_robin ();
+
+ /* Update delays. */
+ os_time++;
+ rt_dec_dly ();
+
+ /* Check the user timers. */
+#ifdef __CMSIS_RTOS
+ sysTimerTick();
+#else
+ rt_tmr_tick ();
+#endif
+
+ /* Switch back to highest ready task */
+ next = rt_get_first (&os_rdy);
+ rt_switch_req (next);
+}
+
+/*--------------------------- rt_stk_check ----------------------------------*/
+
+__weak void rt_stk_check (void) {
+ /* Check for stack overflow. */
+ if ((os_tsk.run->tsk_stack < (U32)os_tsk.run->stack) ||
+ (os_tsk.run->stack[0] != MAGIC_WORD)) {
+ os_error (OS_ERR_STK_OVF);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_System.h b/CMSIS/RTOS/RTX/SRC/rt_System.h
new file mode 100644
index 0000000..4c1c5e2
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_System.h
@@ -0,0 +1,51 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_SYSTEM.H
+ * Purpose: System Task Manager definitions
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+#define os_psq ((P_PSQ)&os_fifo)
+extern S32 os_tick_irqn;
+
+/* Functions */
+extern U32 rt_suspend (void);
+extern void rt_resume (U32 sleep_time);
+extern void rt_tsk_lock (void);
+extern void rt_tsk_unlock (void);
+extern void rt_psh_req (void);
+extern void rt_pop_req (void);
+extern void rt_systick (void);
+extern void rt_stk_check (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Task.c b/CMSIS/RTOS/RTX/SRC/rt_Task.c
new file mode 100644
index 0000000..b1315c8
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Task.c
@@ -0,0 +1,446 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TASK.C
+ * Purpose: Task functions and system start up.
+ * Rev.: V4.80
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_System.h"
+#include "rt_Task.h"
+#include "rt_List.h"
+#include "rt_MemBox.h"
+#include "rt_Robin.h"
+#include "rt_HAL_CM.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Running and next task info. */
+struct OS_TSK os_tsk;
+
+/* Task Control Blocks of idle demon */
+struct OS_TCB os_idle_TCB;
+
+
+/*----------------------------------------------------------------------------
+ * Local Functions
+ *---------------------------------------------------------------------------*/
+
+static OS_TID rt_get_TID (void) {
+ U32 tid;
+
+ for (tid = 1U; tid <= os_maxtaskrun; tid++) {
+ if (os_active_TCB[tid-1U] == NULL) {
+ return ((OS_TID)tid);
+ }
+ }
+ return (0U);
+}
+
+
+/*--------------------------- rt_init_context -------------------------------*/
+
+static void rt_init_context (P_TCB p_TCB, U8 priority, FUNCP task_body) {
+ /* Initialize general part of the Task Control Block. */
+ p_TCB->cb_type = TCB;
+ p_TCB->state = READY;
+ p_TCB->prio = priority;
+ p_TCB->prio_base = priority;
+ p_TCB->p_lnk = NULL;
+ p_TCB->p_rlnk = NULL;
+ p_TCB->p_dlnk = NULL;
+ p_TCB->p_blnk = NULL;
+ p_TCB->p_mlnk = NULL;
+ p_TCB->delta_time = 0U;
+ p_TCB->interval_time = 0U;
+ p_TCB->events = 0U;
+ p_TCB->waits = 0U;
+ p_TCB->stack_frame = 0U;
+
+ if (p_TCB->priv_stack == 0U) {
+ /* Allocate the memory space for the stack. */
+ p_TCB->stack = rt_alloc_box (mp_stk);
+ }
+ rt_init_stack (p_TCB, task_body);
+}
+
+
+/*--------------------------- rt_switch_req ---------------------------------*/
+
+void rt_switch_req (P_TCB p_new) {
+ /* Switch to next task (identified by "p_new"). */
+ os_tsk.new = p_new;
+ p_new->state = RUNNING;
+ DBG_TASK_SWITCH(p_new->task_id);
+}
+
+
+/*--------------------------- rt_dispatch -----------------------------------*/
+
+void rt_dispatch (P_TCB next_TCB) {
+ /* Dispatch next task if any identified or dispatch highest ready task */
+ /* "next_TCB" identifies a task to run or has value NULL (=no next task) */
+ if (next_TCB == NULL) {
+ /* Running task was blocked: continue with highest ready task */
+ next_TCB = rt_get_first (&os_rdy);
+ rt_switch_req (next_TCB);
+ }
+ else {
+ /* Check which task continues */
+ if (next_TCB->prio > os_tsk.run->prio) {
+ /* preempt running task */
+ rt_put_rdy_first (os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_switch_req (next_TCB);
+ }
+ else {
+ /* put next task into ready list, no task switch takes place */
+ next_TCB->state = READY;
+ rt_put_prio (&os_rdy, next_TCB);
+ }
+ }
+}
+
+
+/*--------------------------- rt_block --------------------------------------*/
+
+void rt_block (U16 timeout, U8 block_state) {
+ /* Block running task and choose next ready task. */
+ /* "timeout" sets a time-out value or is 0xffff (=no time-out). */
+ /* "block_state" defines the appropriate task state */
+ P_TCB next_TCB;
+
+ if (timeout) {
+ if (timeout < 0xFFFFU) {
+ rt_put_dly (os_tsk.run, timeout);
+ }
+ os_tsk.run->state = block_state;
+ next_TCB = rt_get_first (&os_rdy);
+ rt_switch_req (next_TCB);
+ }
+}
+
+
+/*--------------------------- rt_tsk_pass -----------------------------------*/
+
+void rt_tsk_pass (void) {
+ /* Allow tasks of same priority level to run cooperatively.*/
+ P_TCB p_new;
+
+ p_new = rt_get_same_rdy_prio();
+ if (p_new != NULL) {
+ rt_put_prio ((P_XCB)&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_switch_req (p_new);
+ }
+}
+
+
+/*--------------------------- rt_tsk_self -----------------------------------*/
+
+OS_TID rt_tsk_self (void) {
+ /* Return own task identifier value. */
+ if (os_tsk.run == NULL) {
+ return (0U);
+ }
+ return ((OS_TID)os_tsk.run->task_id);
+}
+
+
+/*--------------------------- rt_tsk_prio -----------------------------------*/
+
+OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio) {
+ /* Change execution priority of a task to "new_prio". */
+ P_TCB p_task;
+
+ if (task_id == 0U) {
+ /* Change execution priority of calling task. */
+ os_tsk.run->prio = new_prio;
+ os_tsk.run->prio_base = new_prio;
+run:if (rt_rdy_prio() > new_prio) {
+ rt_put_prio (&os_rdy, os_tsk.run);
+ os_tsk.run->state = READY;
+ rt_dispatch (NULL);
+ }
+ return (OS_R_OK);
+ }
+
+ /* Find the task in the "os_active_TCB" array. */
+ if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
+ /* Task with "task_id" not found or not started. */
+ return (OS_R_NOK);
+ }
+ p_task = os_active_TCB[task_id-1U];
+ p_task->prio = new_prio;
+ p_task->prio_base = new_prio;
+ if (p_task == os_tsk.run) {
+ goto run;
+ }
+ rt_resort_prio (p_task);
+ if (p_task->state == READY) {
+ /* Task enqueued in a ready list. */
+ p_task = rt_get_first (&os_rdy);
+ rt_dispatch (p_task);
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_tsk_create ---------------------------------*/
+
+OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv) {
+ /* Start a new task declared with "task". */
+ P_TCB task_context;
+ U32 i;
+
+ /* Priority 0 is reserved for idle task! */
+ if ((prio_stksz & 0xFFU) == 0U) {
+ prio_stksz += 1U;
+ }
+ task_context = rt_alloc_box (mp_tcb);
+ if (task_context == NULL) {
+ return (0U);
+ }
+ /* If "size != 0" use a private user provided stack. */
+ task_context->stack = stk;
+ task_context->priv_stack = (U16)(prio_stksz >> 8);
+ /* Pass parameter 'argv' to 'rt_init_context' */
+ task_context->msg = argv;
+ /* For 'size == 0' system allocates the user stack from the memory pool. */
+ rt_init_context (task_context, (U8)(prio_stksz & 0xFFU), task);
+
+ /* Find a free entry in 'os_active_TCB' table. */
+ i = rt_get_TID ();
+ if (i == 0U) {
+ return (0U);
+ }
+ os_active_TCB[i-1U] = task_context;
+ task_context->task_id = (U8)i;
+ DBG_TASK_NOTIFY(task_context, __TRUE);
+ rt_dispatch (task_context);
+ return ((OS_TID)i);
+}
+
+
+/*--------------------------- rt_tsk_delete ---------------------------------*/
+
+OS_RESULT rt_tsk_delete (OS_TID task_id) {
+ /* Terminate the task identified with "task_id". */
+ P_TCB task_context;
+ P_TCB p_TCB;
+ P_MUCB p_MCB, p_MCB0;
+
+ if ((task_id == 0U) || (task_id == os_tsk.run->task_id)) {
+ /* Terminate itself. */
+ os_tsk.run->state = INACTIVE;
+ os_tsk.run->tsk_stack = rt_get_PSP ();
+ rt_stk_check ();
+ p_MCB = os_tsk.run->p_mlnk;
+ while (p_MCB) {
+ /* Release mutexes owned by this task */
+ if (p_MCB->p_lnk) {
+ /* A task is waiting for mutex. */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val (p_TCB, 0U/*osOK*/);
+#else
+ rt_ret_val (p_TCB, OS_R_MUT);
+#endif
+ rt_rmv_dly (p_TCB);
+ p_TCB->state = READY;
+ rt_put_prio (&os_rdy, p_TCB);
+ /* A waiting task becomes the owner of this mutex. */
+ p_MCB0 = p_MCB->p_mlnk;
+ p_MCB->level = 1U;
+ p_MCB->owner = p_TCB;
+ p_MCB->p_mlnk = p_TCB->p_mlnk;
+ p_TCB->p_mlnk = p_MCB;
+ p_MCB = p_MCB0;
+ }
+ else {
+ p_MCB0 = p_MCB->p_mlnk;
+ p_MCB->level = 0U;
+ p_MCB->owner = NULL;
+ p_MCB->p_mlnk = NULL;
+ p_MCB = p_MCB0;
+ }
+ }
+ os_active_TCB[os_tsk.run->task_id-1U] = NULL;
+ rt_free_box (mp_stk, os_tsk.run->stack);
+ os_tsk.run->stack = NULL;
+ DBG_TASK_NOTIFY(os_tsk.run, __FALSE);
+ rt_free_box (mp_tcb, os_tsk.run);
+ os_tsk.run = NULL;
+ rt_dispatch (NULL);
+ /* The program should never come to this point. */
+ }
+ else {
+ /* Find the task in the "os_active_TCB" array. */
+ if ((task_id > os_maxtaskrun) || (os_active_TCB[task_id-1U] == NULL)) {
+ /* Task with "task_id" not found or not started. */
+ return (OS_R_NOK);
+ }
+ task_context = os_active_TCB[task_id-1U];
+ rt_rmv_list (task_context);
+ rt_rmv_dly (task_context);
+ p_MCB = task_context->p_mlnk;
+ while (p_MCB) {
+ /* Release mutexes owned by this task */
+ if (p_MCB->p_lnk) {
+ /* A task is waiting for mutex. */
+ p_TCB = rt_get_first ((P_XCB)p_MCB);
+#ifdef __CMSIS_RTOS
+ rt_ret_val (p_TCB, 0U/*osOK*/);
+#else
+ rt_ret_val (p_TCB, OS_R_MUT);
+#endif
+ rt_rmv_dly (p_TCB);
+ p_TCB->state = READY;
+ rt_put_prio (&os_rdy, p_TCB);
+ /* A waiting task becomes the owner of this mutex. */
+ p_MCB0 = p_MCB->p_mlnk;
+ p_MCB->level = 1U;
+ p_MCB->owner = p_TCB;
+ p_MCB->p_mlnk = p_TCB->p_mlnk;
+ p_TCB->p_mlnk = p_MCB;
+ p_MCB = p_MCB0;
+ }
+ else {
+ p_MCB0 = p_MCB->p_mlnk;
+ p_MCB->level = 0U;
+ p_MCB->owner = NULL;
+ p_MCB->p_mlnk = NULL;
+ p_MCB = p_MCB0;
+ }
+ }
+ os_active_TCB[task_id-1U] = NULL;
+ rt_free_box (mp_stk, task_context->stack);
+ task_context->stack = NULL;
+ DBG_TASK_NOTIFY(task_context, __FALSE);
+ rt_free_box (mp_tcb, task_context);
+ if (rt_rdy_prio() > os_tsk.run->prio) {
+ /* Ready task has higher priority than running task. */
+ os_tsk.run->state = READY;
+ rt_put_prio (&os_rdy, os_tsk.run);
+ rt_dispatch (NULL);
+ }
+ }
+ return (OS_R_OK);
+}
+
+
+/*--------------------------- rt_sys_init -----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_init (void) {
+#else
+void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk) {
+#endif
+ /* Initialize system and start up task declared with "first_task". */
+ U32 i;
+
+ DBG_INIT();
+
+ /* Initialize dynamic memory and task TCB pointers to NULL. */
+ for (i = 0U; i < os_maxtaskrun; i++) {
+ os_active_TCB[i] = NULL;
+ }
+ rt_init_box (mp_tcb, (U32)mp_tcb_size, sizeof(struct OS_TCB));
+ rt_init_box (mp_stk, mp_stk_size, BOX_ALIGN_8 | (U16)(os_stackinfo));
+ rt_init_box ((U32 *)m_tmr, (U32)mp_tmr_size, sizeof(struct OS_TMR));
+
+ /* Set up TCB of idle demon */
+ os_idle_TCB.task_id = 255U;
+ os_idle_TCB.priv_stack = 0U;
+ rt_init_context (&os_idle_TCB, 0U, os_idle_demon);
+
+ /* Set up ready list: initially empty */
+ os_rdy.cb_type = HCB;
+ os_rdy.p_lnk = NULL;
+ /* Set up delay list: initially empty */
+ os_dly.cb_type = HCB;
+ os_dly.p_dlnk = NULL;
+ os_dly.p_blnk = NULL;
+ os_dly.delta_time = 0U;
+
+ /* Fix SP and system variables to assume idle task is running */
+ /* Transform main program into idle task by assuming idle TCB */
+#ifndef __CMSIS_RTOS
+ rt_set_PSP (os_idle_TCB.tsk_stack+32U);
+#endif
+ os_tsk.run = &os_idle_TCB;
+ os_tsk.run->state = RUNNING;
+
+ /* Initialize ps queue */
+ os_psq->first = 0U;
+ os_psq->last = 0U;
+ os_psq->size = os_fifo_size;
+
+ rt_init_robin ();
+
+#ifndef __CMSIS_RTOS
+ /* Initialize SVC and PendSV */
+ rt_svc_init ();
+
+ /* Initialize and start system clock timer */
+ os_tick_irqn = os_tick_init ();
+ if (os_tick_irqn >= 0) {
+ OS_X_INIT((U32)os_tick_irqn);
+ }
+
+ /* Start up first user task before entering the endless loop */
+ rt_tsk_create (first_task, prio_stksz, stk, NULL);
+#endif
+}
+
+
+/*--------------------------- rt_sys_start ----------------------------------*/
+
+#ifdef __CMSIS_RTOS
+void rt_sys_start (void) {
+ /* Start system */
+
+ /* Initialize SVC and PendSV */
+ rt_svc_init ();
+
+ /* Initialize and start system clock timer */
+ os_tick_irqn = os_tick_init ();
+ if (os_tick_irqn >= 0) {
+ OS_X_INIT((U32)os_tick_irqn);
+ }
+}
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Task.h b/CMSIS/RTOS/RTX/SRC/rt_Task.h
new file mode 100644
index 0000000..e285e43
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Task.h
@@ -0,0 +1,81 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TASK.H
+ * Purpose: Task functions and system start up.
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Definitions */
+
+/* Values for 'state' */
+#define INACTIVE 0U
+#define READY 1U
+#define RUNNING 2U
+#define WAIT_DLY 3U
+#define WAIT_ITV 4U
+#define WAIT_OR 5U
+#define WAIT_AND 6U
+#define WAIT_SEM 7U
+#define WAIT_MBX 8U
+#define WAIT_MUT 9U
+
+/* Return codes */
+#define OS_R_TMO 0x01U
+#define OS_R_EVT 0x02U
+#define OS_R_SEM 0x03U
+#define OS_R_MBX 0x04U
+#define OS_R_MUT 0x05U
+
+#define OS_R_OK 0x00U
+#define OS_R_NOK 0xFFU
+
+/* Variables */
+extern struct OS_TSK os_tsk;
+extern struct OS_TCB os_idle_TCB;
+
+/* Functions */
+extern void rt_switch_req (P_TCB p_new);
+extern void rt_dispatch (P_TCB next_TCB);
+extern void rt_block (U16 timeout, U8 block_state);
+extern void rt_tsk_pass (void);
+extern OS_TID rt_tsk_self (void);
+extern OS_RESULT rt_tsk_prio (OS_TID task_id, U8 new_prio);
+extern OS_TID rt_tsk_create (FUNCP task, U32 prio_stksz, void *stk, void *argv);
+extern OS_RESULT rt_tsk_delete (OS_TID task_id);
+#ifdef __CMSIS_RTOS
+extern void rt_sys_init (void);
+extern void rt_sys_start (void);
+#else
+extern void rt_sys_init (FUNCP first_task, U32 prio_stksz, void *stk);
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Time.c b/CMSIS/RTOS/RTX/SRC/rt_Time.c
new file mode 100644
index 0000000..ba29252
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Time.c
@@ -0,0 +1,93 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TIME.C
+ * Purpose: Delay and interval wait functions
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Task.h"
+#include "rt_Time.h"
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* Free running system tick counter */
+U32 os_time;
+
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+
+/*--------------------------- rt_time_get -----------------------------------*/
+
+U32 rt_time_get (void) {
+ /* Get system time tick */
+ return (os_time);
+}
+
+
+/*--------------------------- rt_dly_wait -----------------------------------*/
+
+void rt_dly_wait (U16 delay_time) {
+ /* Delay task by "delay_time" */
+ rt_block (delay_time, WAIT_DLY);
+}
+
+
+/*--------------------------- rt_itv_set ------------------------------------*/
+
+void rt_itv_set (U16 interval_time) {
+ /* Set interval length and define start of first interval */
+ os_tsk.run->interval_time = interval_time;
+ os_tsk.run->delta_time = interval_time + (U16)os_time;
+}
+
+
+/*--------------------------- rt_itv_wait -----------------------------------*/
+
+void rt_itv_wait (void) {
+ /* Wait for interval end and define start of next one */
+ U16 delta;
+
+ delta = os_tsk.run->delta_time - (U16)os_time;
+ os_tsk.run->delta_time += os_tsk.run->interval_time;
+ if ((delta & 0x8000U) == 0U) {
+ rt_block (delta, WAIT_ITV);
+ }
+}
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Time.h b/CMSIS/RTOS/RTX/SRC/rt_Time.h
new file mode 100644
index 0000000..ab34d1a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Time.h
@@ -0,0 +1,46 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TIME.H
+ * Purpose: Delay and interval wait functions definitions
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern U32 os_time;
+
+/* Functions */
+extern U32 rt_time_get (void);
+extern void rt_dly_wait (U16 delay_time);
+extern void rt_itv_set (U16 interval_time);
+extern void rt_itv_wait (void);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Timer.c b/CMSIS/RTOS/RTX/SRC/rt_Timer.c
new file mode 100644
index 0000000..b08e6be
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Timer.c
@@ -0,0 +1,134 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TIMER.C
+ * Purpose: User timer functions
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "rt_TypeDef.h"
+#include "RTX_Config.h"
+#include "rt_Timer.h"
+#include "rt_MemBox.h"
+
+#ifndef __CMSIS_RTOS
+
+
+/*----------------------------------------------------------------------------
+ * Global Variables
+ *---------------------------------------------------------------------------*/
+
+/* User Timer list pointer */
+struct OS_XTMR os_tmr;
+
+/*----------------------------------------------------------------------------
+ * Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- rt_tmr_tick -----------------------------------*/
+
+void rt_tmr_tick (void) {
+ /* Decrement delta count of timer list head. Timers having the value of */
+ /* zero are removed from the list and the callback function is called. */
+ P_TMR p;
+
+ if (os_tmr.next == NULL) {
+ return;
+ }
+ os_tmr.tcnt--;
+ while ((os_tmr.tcnt == 0U) && ((p = os_tmr.next) != NULL)) {
+ /* Call a user provided function to handle an elapsed timer */
+ os_tmr_call (p->info);
+ os_tmr.tcnt = p->tcnt;
+ os_tmr.next = p->next;
+ rt_free_box ((U32 *)m_tmr, p);
+ }
+}
+
+/*--------------------------- rt_tmr_create ---------------------------------*/
+
+OS_ID rt_tmr_create (U16 tcnt, U16 info) {
+ /* Create an user timer and put it into the chained timer list using */
+ /* a timeout count value of "tcnt". User parameter "info" is used as a */
+ /* parameter for the user provided callback function "os_tmr_call ()". */
+ P_TMR p_tmr, p;
+ U32 delta,itcnt = tcnt;
+
+ if ((tcnt == 0U) || (m_tmr == NULL)) {
+ return (NULL);
+ }
+ p_tmr = rt_alloc_box ((U32 *)m_tmr);
+ if (!p_tmr) {
+ return (NULL);
+ }
+ p_tmr->info = info;
+ p = (P_TMR)&os_tmr;
+ delta = p->tcnt;
+ while ((delta < itcnt) && (p->next != NULL)) {
+ p = p->next;
+ delta += p->tcnt;
+ }
+ /* Right place found, insert timer into the list */
+ p_tmr->next = p->next;
+ p_tmr->tcnt = (U16)(delta - itcnt);
+ p->next = p_tmr;
+ p->tcnt -= p_tmr->tcnt;
+ return (p_tmr);
+}
+
+/*--------------------------- rt_tmr_kill -----------------------------------*/
+
+OS_ID rt_tmr_kill (OS_ID timer) {
+ /* Remove user timer from the chained timer list. */
+ P_TMR p, p_tmr;
+
+ p_tmr = (P_TMR)timer;
+ p = (P_TMR)&os_tmr;
+ /* Search timer list for requested timer */
+ while (p->next != p_tmr) {
+ if (p->next == NULL) {
+ /* Failed, "timer" is not in the timer list */
+ return (p_tmr);
+ }
+ p = p->next;
+ }
+ /* Timer was found, remove it from the list */
+ p->next = p_tmr->next;
+ p->tcnt += p_tmr->tcnt;
+ rt_free_box ((U32 *)m_tmr, p_tmr);
+ /* Timer killed */
+ return (NULL);
+}
+
+
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_Timer.h b/CMSIS/RTOS/RTX/SRC/rt_Timer.h
new file mode 100644
index 0000000..c655e49
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_Timer.h
@@ -0,0 +1,45 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TIMER.H
+ * Purpose: User timer functions
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Variables */
+extern struct OS_XTMR os_tmr;
+
+/* Functions */
+extern void rt_tmr_tick (void);
+extern OS_ID rt_tmr_create (U16 tcnt, U16 info);
+extern OS_ID rt_tmr_kill (OS_ID timer);
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/SRC/rt_TypeDef.h b/CMSIS/RTOS/RTX/SRC/rt_TypeDef.h
new file mode 100644
index 0000000..f126cc8
--- /dev/null
+++ b/CMSIS/RTOS/RTX/SRC/rt_TypeDef.h
@@ -0,0 +1,167 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RT_TYPEDEF.H
+ * Purpose: Type Definitions
+ * Rev.: V4.79
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+/* Types */
+typedef char S8;
+typedef unsigned char U8;
+typedef short S16;
+typedef unsigned short U16;
+typedef int S32;
+typedef unsigned int U32;
+typedef long long S64;
+typedef unsigned long long U64;
+typedef unsigned char BIT;
+typedef unsigned int BOOL;
+typedef void (*FUNCP)(void);
+
+typedef U32 OS_TID;
+typedef void *OS_ID;
+typedef U32 OS_RESULT;
+
+typedef struct OS_TCB {
+ /* General part: identical for all implementations. */
+ U8 cb_type; /* Control Block Type */
+ U8 state; /* Task state */
+ U8 prio; /* Execution priority */
+ U8 task_id; /* Task ID value for optimized TCB access */
+ struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
+ struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
+ struct OS_TCB *p_dlnk; /* Link pointer for delay list */
+ struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
+ U16 delta_time; /* Time until time out */
+ U16 interval_time; /* Time interval for periodic waits */
+ U16 events; /* Event flags */
+ U16 waits; /* Wait flags */
+ void **msg; /* Direct message passing when task waits */
+ struct OS_MUCB *p_mlnk; /* Link pointer for mutex owner list */
+ U8 prio_base; /* Base priority */
+
+ /* Hardware dependant part: specific for CM processor */
+ U8 stack_frame; /* Stack frame: 0=Basic, 1=Extended, */
+ /* (2=VFP/D16 stacked, 4=NEON/D32 stacked) */
+ U16 priv_stack; /* Private stack size, 0= system assigned */
+ U32 tsk_stack; /* Current task Stack pointer (R13) */
+ U32 *stack; /* Pointer to Task Stack memory block */
+
+ /* Task entry point used for uVision debugger */
+ FUNCP ptask; /* Task entry address */
+} *P_TCB;
+#define TCB_STACKF 37 /* 'stack_frame' offset */
+#define TCB_TSTACK 40 /* 'tsk_stack' offset */
+
+typedef struct OS_PSFE { /* Post Service Fifo Entry */
+ void *id; /* Object Identification */
+ U32 arg; /* Object Argument */
+} *P_PSFE;
+
+typedef struct OS_PSQ { /* Post Service Queue */
+ U8 first; /* FIFO Head Index */
+ U8 last; /* FIFO Tail Index */
+ U8 count; /* Number of stored items in FIFO */
+ U8 size; /* FIFO Size */
+ struct OS_PSFE q[1]; /* FIFO Content */
+} *P_PSQ;
+
+typedef struct OS_TSK {
+ P_TCB run; /* Current running task */
+ P_TCB new; /* Scheduled task to run */
+} *P_TSK;
+
+typedef struct OS_ROBIN { /* Round Robin Control */
+ P_TCB task; /* Round Robin task */
+ U16 time; /* Round Robin switch time */
+ U16 tout; /* Round Robin timeout */
+} *P_ROBIN;
+
+typedef struct OS_XCB {
+ U8 cb_type; /* Control Block Type */
+ struct OS_TCB *p_lnk; /* Link pointer for ready/sem. wait list */
+ struct OS_TCB *p_rlnk; /* Link pointer for sem./mbx lst backwards */
+ struct OS_TCB *p_dlnk; /* Link pointer for delay list */
+ struct OS_TCB *p_blnk; /* Link pointer for delay list backwards */
+ U16 delta_time; /* Time until time out */
+} *P_XCB;
+
+typedef struct OS_MCB {
+ U8 cb_type; /* Control Block Type */
+ U8 state; /* State flag variable */
+ U8 isr_st; /* State flag variable for isr functions */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for message */
+ U16 first; /* Index of the message list begin */
+ U16 last; /* Index of the message list end */
+ U16 count; /* Actual number of stored messages */
+ U16 size; /* Maximum number of stored messages */
+ void *msg[1]; /* FIFO for Message pointers 1st element */
+} *P_MCB;
+
+typedef struct OS_SCB {
+ U8 cb_type; /* Control Block Type */
+ U8 mask; /* Semaphore token mask */
+ U16 tokens; /* Semaphore tokens */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for tokens */
+} *P_SCB;
+
+typedef struct OS_MUCB {
+ U8 cb_type; /* Control Block Type */
+ U16 level; /* Call nesting level */
+ struct OS_TCB *p_lnk; /* Chain of tasks waiting for mutex */
+ struct OS_TCB *owner; /* Mutex owner task */
+ struct OS_MUCB *p_mlnk; /* Chain of mutexes by owner task */
+} *P_MUCB;
+
+typedef struct OS_XTMR {
+ struct OS_TMR *next;
+ U16 tcnt;
+} *P_XTMR;
+
+typedef struct OS_TMR {
+ struct OS_TMR *next; /* Link pointer to Next timer */
+ U16 tcnt; /* Timer delay count */
+ U16 info; /* User defined call info */
+} *P_TMR;
+
+typedef struct OS_BM {
+ void *free; /* Pointer to first free memory block */
+ void *end; /* Pointer to memory block end */
+ U32 blk_size; /* Memory block size */
+} *P_BM;
+
+/* Definitions */
+#define __TRUE 1U
+#define __FALSE 0U
+#define NULL ((void *) 0)
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvopt
new file mode 100644
index 0000000..d72f069
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=898,200,1264,746,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>3</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM0.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\system_ARMCM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM0.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\LIB\ARM\RTX_CM0.lib</PathWithFileName>
+ <FilenameWithoutPath>RTX_CM0.lib</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>..\..\main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvproj
new file mode 100644
index 0000000..9f4ce60
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/ARM/Template.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M0"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>0</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM0.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system_ARMCM0.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_CM0.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\..\..\LIB\ARM\RTX_CM0.lib</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/ARM/startup_ARMCM0.s b/CMSIS/RTOS/RTX/Templates/CM0/ARM/startup_ARMCM0.s
new file mode 100644
index 0000000..91268dc
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/ARM/startup_ARMCM0.s
@@ -0,0 +1,253 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/ARMCM0.h b/CMSIS/RTOS/RTX/Templates/CM0/ARMCM0.h
new file mode 100644
index 0000000..6e1e697
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/ARMCM0.h
@@ -0,0 +1,277 @@
+/**************************************************************************//**
+ * @file ARMCM0.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM0 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef ARMCM0_H
+#define ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
+
+
+
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+/* ---------------------- ARMCM0 Specific Interrupt Numbers --------------------- */
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
+ TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
+ TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
+ MCIA_IRQn = 4, /*!< MCIa Interrupt */
+ MCIB_IRQn = 5, /*!< MCIb Interrupt */
+ UART0_IRQn = 6, /*!< UART0 Interrupt */
+ UART1_IRQn = 7, /*!< UART1 Interrupt */
+ UART2_IRQn = 8, /*!< UART2 Interrupt */
+ UART4_IRQn = 9, /*!< UART4 Interrupt */
+ AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
+ CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
+ ENET_IRQn = 12, /*!< Ethernet Interrupt */
+ USBDC_IRQn = 13, /*!< USB Device Interrupt */
+ USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
+ CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
+ FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
+ CAN_IRQn = 17, /*!< CAN Interrupt */
+ LIN_IRQn = 18, /*!< LIN Interrupt */
+ I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
+ CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
+ UART3_IRQn = 30, /*!< UART3 Interrupt */
+ SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+#define __CM0_REV 0x0000 /*!< Core revision r0p0 */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include <core_cm0.h> /* Processor and core peripherals */
+#include "system_ARMCM0.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ CPU FPGA System (CPU_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
+ __IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
+ uint32_t RESERVED0[2];
+ __IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
+ __IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
+ __IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
+ uint32_t RESERVED1[3];
+ __IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
+ __IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
+} ARM_CPU_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ DUT FPGA System (DUT_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
+ __I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
+ __I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
+} ARM_DUT_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ Timer (TIM) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+} ARM_TIM_TypeDef;
+
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
+ union {
+ __I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
+ __O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
+ };
+ uint32_t RESERVED0[4];
+ __IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
+ uint32_t RESERVED1[1];
+ __IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
+ __IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
+ __IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
+ __IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
+ __IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
+ __IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
+ __IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
+ __IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
+ __IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
+ __O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
+ __IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
+} ARM_UART_TypeDef;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA memory map ------------------------------- */
+#define ARM_FLASH_BASE (0x00000000UL)
+#define ARM_RAM_BASE (0x20000000UL)
+#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
+#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
+
+#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
+#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
+
+/* -------------------------- DUT FPGA memory map ------------------------------- */
+#define ARM_APB_BASE (0x40000000UL)
+#define ARM_AHB_BASE (0x4FF00000UL)
+#define ARM_DMC_BASE (0x60000000UL)
+#define ARM_SMC_BASE (0xA0000000UL)
+
+#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
+#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
+#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
+#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
+#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
+#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
+#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA Peripherals ------------------------------ */
+#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
+#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
+
+/* -------------------------- DUT FPGA Peripherals ------------------------------ */
+#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
+#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
+#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
+#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
+#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
+#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
+#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM0_H */
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/G++/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM0/G++/ARMCMx.ld
new file mode 100644
index 0000000..577d3c5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/G++/ARMCMx.ld
@@ -0,0 +1,198 @@
+/* Linker script for Cortex-M
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ .heap :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) :
+ {
+ *(.stack)
+ } >ram
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/G++/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM0/G++/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/G++/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvopt
new file mode 100644
index 0000000..9cae63f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM0.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM0.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM0.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM0.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM0.a</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>../../main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvproj
new file mode 100644
index 0000000..3672eb6
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/G++/Template.uvproj
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M0"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CS3__</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM0.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM0.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM0.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM0.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM0.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/G++/startup_ARMCM0.s b/CMSIS/RTOS/RTX/Templates/CM0/G++/startup_ARMCM0.s
new file mode 100644
index 0000000..9b44e87
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/G++/startup_ARMCM0.s
@@ -0,0 +1,232 @@
+/**************************************************************************//**
+ * @file startup_ARMCM0.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM0 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note Version CodeSourcery Sourcery G++ Lite (with CS3)
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+// <h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Stack_Size, 0x00000400
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Heap_Size, 0x00000C00
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack /* Top of Stack */
+ .long __cs3_reset /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+ .thumb
+
+
+/* Reset Handler */
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=_start
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+/* Exception Handlers */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro def_irq_handler handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/GCC/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM0/GCC/ARMCMx.ld
new file mode 100644
index 0000000..e89c98f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/GCC/ARMCMx.ld
@@ -0,0 +1,188 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64k
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16k
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/GCC/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvopt
new file mode 100644
index 0000000..ed550af
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvopt
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DARMCM1.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TARMCM1.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>127</TopLine>
+ <CurrentLine>142</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM0.S</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM0.S</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM0.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM0.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM0.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM0.a</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>4</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvproj
new file mode 100644
index 0000000..43f9572
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/GCC/Template.uvproj
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M0</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4803</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DARMCM1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M0"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM0.S</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\startup_ARMCM0.S</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM0.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM0.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM0.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM0.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/GCC/startup_ARMCM0.S b/CMSIS/RTOS/RTX/Templates/CM0/GCC/startup_ARMCM0.S
new file mode 100644
index 0000000..9ab0963
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/GCC/startup_ARMCM0.S
@@ -0,0 +1,320 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V2.0
+ * Date: 16 August 2013
+ *
+ */
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv6-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 1
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ blt .L_loop0_0_done
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ b .L_loop0_0
+
+.L_loop0_0_done:
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .L_loop1_done
+
+.L_loop1:
+ subs r3, #4
+ ldr r0, [r1,r3]
+ str r0, [r2,r3]
+ bgt .L_loop1
+
+.L_loop1_done:
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ blt .L_loop2_0_done
+ str r0, [r1, r2]
+ b .L_loop2_0
+.L_loop2_0_done:
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+
+ subs r2, r1
+ ble .L_loop3_done
+
+.L_loop3:
+ subs r2, #4
+ str r0, [r1, r2]
+ bgt .L_loop3
+.L_loop3_done:
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.ewp b/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.ewp
new file mode 100644
index 0000000..9db2c1c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.ewp
@@ -0,0 +1,1846 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>2</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Debug\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Debug\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Debug\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>19</version>
+ <state>34</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave</name>
+ <version>19</version>
+ <state>34</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>19</version>
+ <state>34</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>0000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
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+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>Template.srec</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>Template.out</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\generic_cortex.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <group>
+ <name>RTX Configuration</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\RTX_Conf_CM.c</name>
+ </file>
+ </group>
+ <group>
+ <name>RTX Library</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\LIB\IAR\RTX_CM0.a</name>
+ </file>
+ </group>
+ <group>
+ <name>Source Files</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\main.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Startup</name>
+ <file>
+ <name>$PROJ_DIR$\startup_ARMCM0.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\system_ARMCM0.c</name>
+ </file>
+ </group>
+</project>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.eww b/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.eww
new file mode 100644
index 0000000..e09d1b5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/IAR/Template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\Template.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/IAR/startup_ARMCM0.s b/CMSIS/RTOS/RTX/Templates/CM0/IAR/startup_ARMCM0.s
new file mode 100644
index 0000000..86698d7
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/IAR/startup_ARMCM0.s
@@ -0,0 +1,283 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM0.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM0 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD 0
+ DCD 0
+ DCD 0
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD 0
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.c b/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.c
new file mode 100644
index 0000000..77de2db
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.c
@@ -0,0 +1,80 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM0 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include "ARMCM0.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI ( 8000000UL)
+#define __XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (5*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.h b/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.h
new file mode 100644
index 0000000..8d66949
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM0/system_ARMCM0.h
@@ -0,0 +1,75 @@
+/**************************************************************************//**
+ * @file system_ARMCM0.h
+ * @brief CMSIS Device System Header File for
+ * ARMCM0 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_ARMCM0_H
+#define SYSTEM_ARMCM0_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM0_H */
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvopt
new file mode 100644
index 0000000..a3460cf
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=898,200,1264,746,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=128,160,362,697,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM3.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM3.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\system_ARMCM3.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM3.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\LIB\ARM\RTX_CM3.lib</PathWithFileName>
+ <FilenameWithoutPath>RTX_CM3.lib</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>..\..\main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvproj
new file mode 100644
index 0000000..70c5ef9
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/ARM/Template.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M3</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4349</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3>"" ()</Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM3.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system_ARMCM3.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_CM3.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\..\..\LIB\ARM\RTX_CM3.lib</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/ARM/startup_ARMCM3.s b/CMSIS/RTOS/RTX/Templates/CM3/ARM/startup_ARMCM3.s
new file mode 100644
index 0000000..512649d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/ARM/startup_ARMCM3.s
@@ -0,0 +1,273 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/ARMCM3.h b/CMSIS/RTOS/RTX/Templates/CM3/ARMCM3.h
new file mode 100644
index 0000000..6a9052b
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/ARMCM3.h
@@ -0,0 +1,277 @@
+/**************************************************************************//**
+ * @file ARMCM3.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM3 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef ARMCM3_H
+#define ARMCM3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+/* ---------------------- ARMCM3 Specific Interrupt Numbers --------------------- */
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
+ TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
+ TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
+ MCIA_IRQn = 4, /*!< MCIa Interrupt */
+ MCIB_IRQn = 5, /*!< MCIb Interrupt */
+ UART0_IRQn = 6, /*!< UART0 Interrupt */
+ UART1_IRQn = 7, /*!< UART1 Interrupt */
+ UART2_IRQn = 8, /*!< UART2 Interrupt */
+ UART4_IRQn = 9, /*!< UART4 Interrupt */
+ AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
+ CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
+ ENET_IRQn = 12, /*!< Ethernet Interrupt */
+ USBDC_IRQn = 13, /*!< USB Device Interrupt */
+ USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
+ CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
+ FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
+ CAN_IRQn = 17, /*!< CAN Interrupt */
+ LIN_IRQn = 18, /*!< LIN Interrupt */
+ I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
+ CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
+ UART3_IRQn = 30, /*!< UART3 Interrupt */
+ SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+#define __CM3_REV 0x0201 /*!< Core revision r2p1 */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+#include <core_cm3.h> /* Processor and core peripherals */
+#include "system_ARMCM3.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ CPU FPGA System (CPU_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
+ __IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
+ uint32_t RESERVED0[2];
+ __IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
+ __IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
+ __IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
+ uint32_t RESERVED1[3];
+ __IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
+ __IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
+} ARM_CPU_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ DUT FPGA System (DUT_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
+ __I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
+ __I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
+} ARM_DUT_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ Timer (TIM) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+} ARM_TIM_TypeDef;
+
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
+ union {
+ __I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
+ __O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
+ };
+ uint32_t RESERVED0[4];
+ __IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
+ uint32_t RESERVED1[1];
+ __IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
+ __IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
+ __IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
+ __IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
+ __IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
+ __IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
+ __IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
+ __IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
+ __IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
+ __O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
+ __IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
+} ARM_UART_TypeDef;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA memory map ------------------------------- */
+#define ARM_FLASH_BASE (0x00000000UL)
+#define ARM_RAM_BASE (0x20000000UL)
+#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
+#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
+
+#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
+#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
+
+/* -------------------------- DUT FPGA memory map ------------------------------- */
+#define ARM_APB_BASE (0x40000000UL)
+#define ARM_AHB_BASE (0x4FF00000UL)
+#define ARM_DMC_BASE (0x60000000UL)
+#define ARM_SMC_BASE (0xA0000000UL)
+
+#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
+#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
+#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
+#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
+#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
+#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
+#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA Peripherals ------------------------------ */
+#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
+#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
+
+/* -------------------------- DUT FPGA Peripherals ------------------------------ */
+#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
+#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
+#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
+#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
+#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
+#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
+#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM3_H */
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/G++/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM3/G++/ARMCMx.ld
new file mode 100644
index 0000000..577d3c5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/G++/ARMCMx.ld
@@ -0,0 +1,198 @@
+/* Linker script for Cortex-M
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ .heap :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) :
+ {
+ *(.stack)
+ } >ram
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/G++/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM3/G++/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/G++/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvopt
new file mode 100644
index 0000000..a444d29
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM3.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM3.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM3.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM3.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM3.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM3.a</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>../../main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvproj
new file mode 100644
index 0000000..82e74b1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/G++/Template.uvproj
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M3</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4349</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define>__CS3__</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM3.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM3.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM3.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM3.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM3.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/G++/startup_ARMCM3.s b/CMSIS/RTOS/RTX/Templates/CM3/G++/startup_ARMCM3.s
new file mode 100644
index 0000000..231d27b
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/G++/startup_ARMCM3.s
@@ -0,0 +1,256 @@
+/**************************************************************************//**
+ * @file startup_ARMCM3.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM3 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note Version CodeSourcery Sourcery G++ Lite (with CS3)
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+// <h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Stack_Size, 0x00000400
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Heap_Size, 0x00000C00
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack /* Top of Stack */
+ .long __cs3_reset /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+ .thumb
+
+
+/* Reset Handler */
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=_start
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+/* Exception Handlers */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+MemManage_Handler:
+ B .
+ .size MemManage_Handler, . - MemManage_Handler
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ B .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro def_irq_handler handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/GCC/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM3/GCC/ARMCMx.ld
new file mode 100644
index 0000000..e89c98f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/GCC/ARMCMx.ld
@@ -0,0 +1,188 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64k
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16k
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/GCC/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvopt
new file mode 100644
index 0000000..36372ce
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvopt
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>127</TopLine>
+ <CurrentLine>142</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM3.S</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM3.S</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM3.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM3.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM3.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM3.a</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>4</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvproj
new file mode 100644
index 0000000..bcf547a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/GCC/Template.uvproj
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M3</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M3") ESEL ELITTLE</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>4349</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM3</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM3</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M3"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM3.S</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\startup_ARMCM3.S</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM3.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM3.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM3.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/GCC/startup_ARMCM3.S b/CMSIS/RTOS/RTX/Templates/CM3/GCC/startup_ARMCM3.S
new file mode 100644
index 0000000..bb81bcf
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/GCC/startup_ARMCM3.S
@@ -0,0 +1,314 @@
+/* File: startup_ARMCM3.S
+ * Purpose: startup file for Cortex-M3 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V2.0
+ * Date: 16 August 2013
+ *
+ */
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.ewp b/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.ewp
new file mode 100644
index 0000000..e78c24d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.ewp
@@ -0,0 +1,1846 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>2</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Debug\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Debug\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Debug\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>19</version>
+ <state>37</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave</name>
+ <version>19</version>
+ <state>37</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>19</version>
+ <state>37</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>0000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
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+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
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+ </option>
+ <option>
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+ <option>
+ <name>AWarnOne</name>
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+ <name>AWarnRange1</name>
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+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>1</state>
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+ <option>
+ <name>AltRegisterNames</name>
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+ <name>ADefines</name>
+ <state></state>
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+ <option>
+ <name>AList</name>
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+ <name>AListHeader</name>
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+ <option>
+ <name>AListing</name>
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+ <name>MacDefs</name>
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+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
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+ <option>
+ <name>MacExec</name>
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+ <option>
+ <name>OnlyAssed</name>
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+ <name>MultiLine</name>
+ <state>0</state>
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+ <name>PageLengthCheck</name>
+ <state>0</state>
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+ <option>
+ <name>PageLength</name>
+ <state>80</state>
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+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
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+ <option>
+ <name>AXRef</name>
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+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
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+ </option>
+ <option>
+ <name>AProcessor</name>
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+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
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+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
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+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
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+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>Template.srec</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
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+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
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+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>Template.out</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
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+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
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+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
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+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
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+ <option>
+ <name>IlinkMapFile</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkLogInitialization</name>
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+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\generic_cortex.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
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+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
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+ <name>IlinkTreatAsWarn</name>
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+ <name>IlinkTreatAsErr</name>
+ <state></state>
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+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
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+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
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+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
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+ <name>FillerEnd</name>
+ <state>0x0</state>
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+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
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+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
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+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
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+ <name>CrcPoly</name>
+ <state>0x11021</state>
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+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
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+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
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+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
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+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
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+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
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+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
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+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
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+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
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+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
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+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
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+ </configuration>
+ <configuration>
+ <name>Release</name>
+ <toolchain>
+ <name>ARM</name>
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+ <debug>0</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
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+ <debug>0</debug>
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+ <name>ExePath</name>
+ <state>Release\Exe</state>
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+ <option>
+ <name>ObjPath</name>
+ <state>Release\Obj</state>
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+ <option>
+ <name>ListPath</name>
+ <state>Release\List</state>
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+ <option>
+ <name>Variant</name>
+ <version>19</version>
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+ <option>
+ <name>GEndianMode</name>
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+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter.</state>
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+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>0</state>
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+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter.</state>
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+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
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+ <name>FPU</name>
+ <version>2</version>
+ <state>0</state>
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+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
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+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
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+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+ <option>
+ <name>OGProductVersion</name>
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+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
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+ <name>GeneralEnableMisra</name>
+ <state>0</state>
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+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
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+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>0</state>
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+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
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+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
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+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
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+ <name>GeneralMisraRules98</name>
+ <version>0</version>
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+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
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+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
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+ <name>GFPUCoreSlave</name>
+ <version>19</version>
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+ <name>GBECoreSlave</name>
+ <version>19</version>
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+ <name>OGUseCmsis</name>
+ <state>1</state>
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+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
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+ <name>CCDefines</name>
+ <state>NDEBUG</state>
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+ <name>CCPreprocFile</name>
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+ <name>CCPreprocComments</name>
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+ <name>CCPreprocLine</name>
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+ <name>CCListCFile</name>
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+ <name>CCListCMnemonics</name>
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+ <name>CCEnableRemarks</name>
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+ <name>CCDiagSuppress</name>
+ <state></state>
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+ <name>CCDiagRemark</name>
+ <state></state>
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+ <name>CCDiagWarning</name>
+ <state></state>
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+ <option>
+ <name>CCDiagError</name>
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+ <name>CCObjPrefix</name>
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+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>1111111</state>
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+ <name>CCDebugInfo</name>
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+ <name>IProcessor</name>
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+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
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+ <name>CCLangConformance</name>
+ <state>0</state>
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+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
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+ <option>
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+ <name>CCMultibyteSupport</name>
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+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
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+ <option>
+ <name>CCCompilerRuntimeInfo</name>
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+ <name>IFpuProcessor</name>
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+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
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+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
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+ <name>PreInclude</name>
+ <state></state>
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+ <name>CompilerMisraOverride</name>
+ <state>0</state>
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+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
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+ <name>CCStdIncCheck</name>
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+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
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+ <option>
+ <name>IProcessorMode2</name>
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+ <name>CCOptLevel</name>
+ <state>3</state>
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+ <name>CCOptStrategy</name>
+ <version>0</version>
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+ <name>CCOptLevelSlave</name>
+ <state>3</state>
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+ <version>0</version>
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+ <version>0</version>
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+ <name>CCPosIndRwpi</name>
+ <state>0</state>
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+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
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+ <option>
+ <name>IccLang</name>
+ <state>0</state>
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+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
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+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
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+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
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+ <name>IccExceptions</name>
+ <state>1</state>
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+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
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+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
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+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
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+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>Template.srec</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>Template.out</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\generic_cortex.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <group>
+ <name>RTX Configuration</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\RTX_Conf_CM.c</name>
+ </file>
+ </group>
+ <group>
+ <name>RTX Library</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\LIB\IAR\RTX_CM3.a</name>
+ </file>
+ </group>
+ <group>
+ <name>Source Files</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\main.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Startup</name>
+ <file>
+ <name>$PROJ_DIR$\startup_ARMCM3.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\system_ARMCM3.c</name>
+ </file>
+ </group>
+</project>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.eww b/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.eww
new file mode 100644
index 0000000..e09d1b5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/IAR/Template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\Template.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/IAR/startup_ARMCM3.s b/CMSIS/RTOS/RTX/Templates/CM3/IAR/startup_ARMCM3.s
new file mode 100644
index 0000000..e80bbb3
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/IAR/startup_ARMCM3.s
@@ -0,0 +1,305 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM3.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM3 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.c b/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.c
new file mode 100644
index 0000000..359330c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.c
@@ -0,0 +1,84 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM3 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include "ARMCM3.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI ( 8000000UL)
+#define __XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (5*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.h b/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.h
new file mode 100644
index 0000000..4510b89
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM3/system_ARMCM3.h
@@ -0,0 +1,75 @@
+/**************************************************************************//**
+ * @file system_ARMCM3.h
+ * @brief CMSIS Device System Header File for
+ * ARMCM3 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_ARMCM3_H
+#define SYSTEM_ARMCM3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM3_H */
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvopt
new file mode 100644
index 0000000..e6d8bd9
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <CLKADS>12000000</CLKADS>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>79</PageWidth>
+ <PageLength>66</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile></sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=898,200,1264,746,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=128,160,362,697,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM4.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM4.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\system_ARMCM4.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM4.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\..\LIB\ARM\RTX_CM4.lib</PathWithFileName>
+ <FilenameWithoutPath>RTX_CM4.lib</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>..\..\main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>..\..\main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvproj
new file mode 100644
index 0000000..236fd91
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/ARM/Template.uvproj
@@ -0,0 +1,435 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x4</ToolsetNumber>
+ <ToolsetName>ARM-ADS</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M4 FPU</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>5237</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>0</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>0</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M4"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>1</StupSel>
+ <useUlib>1</useUlib>
+ <EndSel>1</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>0</RoSelD>
+ <RwSelD>5</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>1</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>0</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>1</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>0</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x4000</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>0</wLevel>
+ <uThumb>0</uThumb>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x20000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM4.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\system_ARMCM4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_CM4.lib</FileName>
+ <FileType>4</FileType>
+ <FilePath>..\..\..\LIB\ARM\RTX_CM4.lib</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>..\..\main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/ARM/startup_ARMCM4.s b/CMSIS/RTOS/RTX/Templates/CM4/ARM/startup_ARMCM4.s
new file mode 100644
index 0000000..a51fee7
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/ARM/startup_ARMCM4.s
@@ -0,0 +1,273 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+;/*
+;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+;*/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000C00
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT TIM0_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT MCIA_IRQHandler [WEAK]
+ EXPORT MCIB_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT AACI_IRQHandler [WEAK]
+ EXPORT CLCD_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT USBDC_IRQHandler [WEAK]
+ EXPORT USBHC_IRQHandler [WEAK]
+ EXPORT CHLCD_IRQHandler [WEAK]
+ EXPORT FLEXRAY_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT LIN_IRQHandler [WEAK]
+ EXPORT I2C_IRQHandler [WEAK]
+ EXPORT CPU_CLCD_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+
+WDT_IRQHandler
+RTC_IRQHandler
+TIM0_IRQHandler
+TIM2_IRQHandler
+MCIA_IRQHandler
+MCIB_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+UART4_IRQHandler
+AACI_IRQHandler
+CLCD_IRQHandler
+ENET_IRQHandler
+USBDC_IRQHandler
+USBHC_IRQHandler
+CHLCD_IRQHandler
+FLEXRAY_IRQHandler
+CAN_IRQHandler
+LIN_IRQHandler
+I2C_IRQHandler
+CPU_CLCD_IRQHandler
+SPI_IRQHandler
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+
+__user_initial_stackheap PROC
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+ ENDP
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/ARMCM4.h b/CMSIS/RTOS/RTX/Templates/CM4/ARMCM4.h
new file mode 100644
index 0000000..463ba02
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/ARMCM4.h
@@ -0,0 +1,278 @@
+/**************************************************************************//**
+ * @file ARMCM4.h
+ * @brief CMSIS Core Peripheral Access Layer Header File for
+ * ARMCM4 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef ARMCM4_H
+#define ARMCM4_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* ------------------------- Interrupt Number Definition ------------------------ */
+
+typedef enum IRQn
+{
+/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
+
+/* ---------------------- ARMCM4 Specific Interrupt Numbers --------------------- */
+ WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
+ RTC_IRQn = 1, /*!< Real Time Clock Interrupt */
+ TIM0_IRQn = 2, /*!< Timer0 / Timer1 Interrupt */
+ TIM2_IRQn = 3, /*!< Timer2 / Timer3 Interrupt */
+ MCIA_IRQn = 4, /*!< MCIa Interrupt */
+ MCIB_IRQn = 5, /*!< MCIb Interrupt */
+ UART0_IRQn = 6, /*!< UART0 Interrupt */
+ UART1_IRQn = 7, /*!< UART1 Interrupt */
+ UART2_IRQn = 8, /*!< UART2 Interrupt */
+ UART4_IRQn = 9, /*!< UART4 Interrupt */
+ AACI_IRQn = 10, /*!< AACI / AC97 Interrupt */
+ CLCD_IRQn = 11, /*!< CLCD Combined Interrupt */
+ ENET_IRQn = 12, /*!< Ethernet Interrupt */
+ USBDC_IRQn = 13, /*!< USB Device Interrupt */
+ USBHC_IRQn = 14, /*!< USB Host Controller Interrupt */
+ CHLCD_IRQn = 15, /*!< Character LCD Interrupt */
+ FLEXRAY_IRQn = 16, /*!< Flexray Interrupt */
+ CAN_IRQn = 17, /*!< CAN Interrupt */
+ LIN_IRQn = 18, /*!< LIN Interrupt */
+ I2C_IRQn = 19, /*!< I2C ADC/DAC Interrupt */
+ CPU_CLCD_IRQn = 28, /*!< CPU CLCD Combined Interrupt */
+ UART3_IRQn = 30, /*!< UART3 Interrupt */
+ SPI_IRQn = 31, /*!< SPI Touchscreen Interrupt */
+} IRQn_Type;
+
+
+/* ================================================================================ */
+/* ================ Processor and Core Peripheral Section ================ */
+/* ================================================================================ */
+
+/* -------- Configuration of the Cortex-M4 Processor and Core Peripherals ------- */
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
+#define __MPU_PRESENT 1 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present or not */
+
+#include <core_cm4.h> /* Processor and core peripherals */
+#include "system_ARMCM4.h" /* System Header */
+
+
+/* ================================================================================ */
+/* ================ Device Specific Peripheral Section ================ */
+/* ================================================================================ */
+
+/* ------------------- Start of section using anonymous unions ------------------ */
+#if defined(__CC_ARM)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__ICCARM__)
+ #pragma language=extended
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning 586
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+/* ================================================================================ */
+/* ================ CPU FPGA System (CPU_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t MEMCFG; /* Offset: 0x004 (R/W) Remap and Alias Memory Control */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __I uint32_t TS; /* Offset: 0x010 (R/ ) Touchscreen Register */
+ __IO uint32_t CTRL1; /* Offset: 0x014 (R/W) Misc Control Functions */
+ uint32_t RESERVED0[2];
+ __IO uint32_t CLKCFG; /* Offset: 0x020 (R/W) System Clock Configuration */
+ __IO uint32_t WSCFG; /* Offset: 0x024 (R/W) Flash Waitstate Configuration */
+ __IO uint32_t CPUCFG; /* Offset: 0x028 (R/W) Processor Configuration */
+ uint32_t RESERVED1[3];
+ __IO uint32_t BASE; /* Offset: 0x038 (R/W) ROM Table base Address */
+ __IO uint32_t ID2; /* Offset: 0x03C (R/W) Secondary Identification Register */
+} ARM_CPU_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ DUT FPGA System (DUT_SYS) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __I uint32_t ID; /* Offset: 0x000 (R/ ) Board and FPGA Identifier */
+ __IO uint32_t PERCFG; /* Offset: 0x004 (R/W) Peripheral Control Signals */
+ __I uint32_t SW; /* Offset: 0x008 (R/ ) Switch States */
+ __IO uint32_t LED; /* Offset: 0x00C (R/W) LED Output States */
+ __IO uint32_t SEG7; /* Offset: 0x010 (R/W) 7-segment LED Output States */
+ __I uint32_t CNT25MHz; /* Offset: 0x014 (R/ ) Freerunning counter incrementing at 25MHz */
+ __I uint32_t CNT100Hz; /* Offset: 0x018 (R/ ) Freerunning counter incrementing at 100Hz */
+} ARM_DUT_SYS_TypeDef;
+
+
+/* ================================================================================ */
+/* ================ Timer (TIM) ================ */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
+ __I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
+ __IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
+ __O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
+ __I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
+ __I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
+ __IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
+ uint32_t RESERVED0[1];
+ __IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
+ __I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
+ __IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
+ __O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
+ __I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
+ __I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
+ __IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
+} ARM_TIM_TypeDef;
+
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+ __IO uint32_t DR; /* Offset: 0x000 (R/W) Data */
+ union {
+ __I uint32_t RSR; /* Offset: 0x000 (R/ ) Receive Status */
+ __O uint32_t ECR; /* Offset: 0x000 ( /W) Error Clear */
+ };
+ uint32_t RESERVED0[4];
+ __IO uint32_t FR; /* Offset: 0x018 (R/W) Flags */
+ uint32_t RESERVED1[1];
+ __IO uint32_t ILPR; /* Offset: 0x020 (R/W) IrDA Low-power Counter */
+ __IO uint32_t IBRD; /* Offset: 0x024 (R/W) Interger Baud Rate */
+ __IO uint32_t FBRD; /* Offset: 0x028 (R/W) Fractional Baud Rate */
+ __IO uint32_t LCR_H; /* Offset: 0x02C (R/W) Line Control */
+ __IO uint32_t CR; /* Offset: 0x030 (R/W) Control */
+ __IO uint32_t IFLS; /* Offset: 0x034 (R/W) Interrupt FIFO Level Select */
+ __IO uint32_t IMSC; /* Offset: 0x038 (R/W) Interrupt Mask Set / Clear */
+ __IO uint32_t RIS; /* Offset: 0x03C (R/W) Raw Interrupt Status */
+ __IO uint32_t MIS; /* Offset: 0x040 (R/W) Masked Interrupt Status */
+ __O uint32_t ICR; /* Offset: 0x044 ( /W) Interrupt Clear */
+ __IO uint32_t DMACR; /* Offset: 0x048 (R/W) DMA Control */
+} ARM_UART_TypeDef;
+
+
+/* -------------------- End of section using anonymous unions ------------------- */
+#if defined(__CC_ARM)
+ #pragma pop
+#elif defined(__ICCARM__)
+ /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+ /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+ #pragma warning restore
+#else
+ #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================ Peripheral memory map ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA memory map ------------------------------- */
+#define ARM_FLASH_BASE (0x00000000UL)
+#define ARM_RAM_BASE (0x20000000UL)
+#define ARM_RAM_FPGA_BASE (0x1EFF0000UL)
+#define ARM_CPU_CFG_BASE (0xDFFF0000UL)
+
+#define ARM_CPU_SYS_BASE (ARM_CPU_CFG_BASE + 0x00000)
+#define ARM_UART3_BASE (ARM_CPU_CFG_BASE + 0x05000)
+
+/* -------------------------- DUT FPGA memory map ------------------------------- */
+#define ARM_APB_BASE (0x40000000UL)
+#define ARM_AHB_BASE (0x4FF00000UL)
+#define ARM_DMC_BASE (0x60000000UL)
+#define ARM_SMC_BASE (0xA0000000UL)
+
+#define ARM_TIM0_BASE (ARM_APB_BASE + 0x02000)
+#define ARM_TIM2_BASE (ARM_APB_BASE + 0x03000)
+#define ARM_DUT_SYS_BASE (ARM_APB_BASE + 0x04000)
+#define ARM_UART0_BASE (ARM_APB_BASE + 0x06000)
+#define ARM_UART1_BASE (ARM_APB_BASE + 0x07000)
+#define ARM_UART2_BASE (ARM_APB_BASE + 0x08000)
+#define ARM_UART4_BASE (ARM_APB_BASE + 0x09000)
+
+
+/* ================================================================================ */
+/* ================ Peripheral declaration ================ */
+/* ================================================================================ */
+/* -------------------------- CPU FPGA Peripherals ------------------------------ */
+#define ARM_CPU_SYS ((ARM_CPU_SYS_TypeDef *) ARM_CPU_SYS_BASE)
+#define ARM_UART3 (( ARM_UART_TypeDef *) ARM_UART3_BASE)
+
+/* -------------------------- DUT FPGA Peripherals ------------------------------ */
+#define ARM_DUT_SYS ((ARM_DUT_SYS_TypeDef *) ARM_DUT_SYS_BASE)
+#define ARM_TIM0 (( ARM_TIM_TypeDef *) ARM_TIM0_BASE)
+#define ARM_TIM2 (( ARM_TIM_TypeDef *) ARM_TIM2_BASE)
+#define ARM_UART0 (( ARM_UART_TypeDef *) ARM_UART0_BASE)
+#define ARM_UART1 (( ARM_UART_TypeDef *) ARM_UART1_BASE)
+#define ARM_UART2 (( ARM_UART_TypeDef *) ARM_UART2_BASE)
+#define ARM_UART4 (( ARM_UART_TypeDef *) ARM_UART4_BASE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ARMCM4_H */
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/G++/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM4/G++/ARMCMx.ld
new file mode 100644
index 0000000..577d3c5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/G++/ARMCMx.ld
@@ -0,0 +1,198 @@
+/* Linker script for Cortex-M
+ *
+ * Version:CodeSourcery Sourcery G++ Lite 2007q3-53
+ * BugURL:https://support.codesourcery.com/GNUToolchain/
+ *
+ * Copyright 2007 CodeSourcery.
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply. */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+ENTRY(_start)
+SEARCH_DIR(.)
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
+
+MEMORY
+{
+ rom (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
+}
+
+/* These force the linker to search for particular symbols from
+ * the start of the link process and thus ensure the user's
+ * overrides are picked up
+ */
+EXTERN(__cs3_reset_cortex_m)
+EXTERN(__cs3_interrupt_vector_cortex_m)
+EXTERN(__cs3_start_c main __cs3_stack __cs3_stack_size __cs3_heap_end)
+
+PROVIDE(__cs3_stack = __cs3_region_start_ram + __cs3_region_size_ram);
+PROVIDE(__cs3_stack_size = __cs3_region_start_ram + __cs3_region_size_ram - _end);
+PROVIDE(__cs3_heap_start = _end);
+PROVIDE(__cs3_heap_end = __cs3_region_start_ram + __cs3_region_size_ram);
+
+SECTIONS
+{
+ .text :
+ {
+ CREATE_OBJECT_SYMBOLS
+ __cs3_region_start_rom = .;
+ *(.cs3.region-head.rom)
+ __cs3_interrupt_vector = __cs3_interrupt_vector_cortex_m;
+ *(.cs3.interrupt_vector)
+ /* Make sure we pulled in an interrupt vector. */
+ ASSERT (. != __cs3_interrupt_vector_cortex_m, "No interrupt vector");
+ *(.rom)
+ *(.rom.b)
+
+ __cs3_reset = __cs3_reset_cortex_m;
+ *(.cs3.reset)
+ /* Make sure we pulled in some reset code. */
+ ASSERT (. != __cs3_reset, "No reset code");
+
+ *(.text .text.* .gnu.linkonce.t.*)
+ *(.plt)
+ *(.gnu.warning)
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+ *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.gcc_except_table)
+ *(.eh_frame_hdr)
+ *(.eh_frame)
+
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(0x4);
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+
+ . = ALIGN(4);
+ __cs3_regions = .;
+ LONG (0)
+ LONG (__cs3_region_init_ram)
+ LONG (__cs3_region_start_ram)
+ LONG (__cs3_region_init_size_ram)
+ LONG (__cs3_region_zero_size_ram)
+ }
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } >rom
+ __exidx_end = .;
+ .text.align :
+ {
+ . = ALIGN(8);
+ _etext = .;
+ } >rom
+ __cs3_region_size_rom = LENGTH(rom);
+ __cs3_region_num = 1;
+
+ .data :
+ {
+ __cs3_region_start_ram = .;
+ *(.cs3.region-head.ram)
+ KEEP(*(.jcr))
+ *(.got.plt) *(.got)
+ *(.shdata)
+ *(.data .data.* .gnu.linkonce.d.*)
+ *(.ram)
+ . = ALIGN (8);
+ _edata = .;
+ } >ram AT>rom
+ .bss :
+ {
+ *(.shbss)
+ *(.bss .bss.* .gnu.linkonce.b.*)
+ *(COMMON)
+ *(.ram.b)
+ . = ALIGN (8);
+ _end = .;
+ __end = .;
+ } >ram AT>rom
+ .heap :
+ {
+ *(.heap)
+ } >ram
+ .stack (__cs3_stack - __cs3_stack_size) :
+ {
+ *(.stack)
+ } >ram
+ __cs3_region_init_ram = LOADADDR (.data);
+ __cs3_region_init_size_ram = _edata - __cs3_region_start_ram;
+ __cs3_region_zero_size_ram = _end - _edata;
+ __cs3_region_size_ram = LENGTH(ram);
+ __cs3_region_num = 1;
+
+ .stab 0 (NOLOAD) : { *(.stab) }
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }
+ /* DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/G++/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM4/G++/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/G++/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvopt
new file mode 100644
index 0000000..c4060f1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvopt
@@ -0,0 +1,279 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>2</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM4.s</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM4.s</FilenameWithoutPath>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM4.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM4.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>0</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM4.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM4.a</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ </File>
+ </Group>
+
+ <MDIGroups>
+ <Orientation>1</Orientation>
+ <ActiveMDIGroup>0</ActiveMDIGroup>
+ <MDIGroup>
+ <Size>100</Size>
+ <ActiveTab>0</ActiveTab>
+ <Documents>
+ <Doc>
+ <Name>../../main.c</Name>
+ <ColumnNumber>0</ColumnNumber>
+ <TopLine>1</TopLine>
+ <CurrentLine>1</CurrentLine>
+ </Doc>
+ </Documents>
+ </MDIGroup>
+ </MDIGroups>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvproj
new file mode 100644
index 0000000..002ba0e
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/G++/Template.uvproj
@@ -0,0 +1,345 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M4 FPU</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>5237</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M4"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp</MiscControls>
+ <Define>__CS3__</Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp -Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM4.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_ARMCM4.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM4.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM4.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/G++/startup_ARMCM4.s b/CMSIS/RTOS/RTX/Templates/CM4/G++/startup_ARMCM4.s
new file mode 100644
index 0000000..d58db54
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/G++/startup_ARMCM4.s
@@ -0,0 +1,256 @@
+/**************************************************************************//**
+ * @file startup_ARMCM4.s
+ * @brief CMSIS Core Device Startup File for
+ * ARMCM4 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note Version CodeSourcery Sourcery G++ Lite (with CS3)
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+
+/*
+// <h> Stack Configuration
+// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Stack_Size, 0x00000400
+ .section ".stack", "w"
+ .align 3
+ .globl __cs3_stack_mem
+ .globl __cs3_stack_size
+__cs3_stack_mem:
+ .if Stack_Size
+ .space Stack_Size
+ .endif
+ .size __cs3_stack_mem, . - __cs3_stack_mem
+ .set __cs3_stack_size, . - __cs3_stack_mem
+
+
+/*
+// <h> Heap Configuration
+// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+ .equ Heap_Size, 0x00000C00
+ .section ".heap", "w"
+ .align 3
+ .globl __cs3_heap_start
+ .globl __cs3_heap_end
+__cs3_heap_start:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+__cs3_heap_end:
+
+
+/* Vector Table */
+
+ .section ".cs3.interrupt_vector"
+ .globl __cs3_interrupt_vector_cortex_m
+ .type __cs3_interrupt_vector_cortex_m, %object
+
+__cs3_interrupt_vector_cortex_m:
+ .long __cs3_stack /* Top of Stack */
+ .long __cs3_reset /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
+
+
+ .thumb
+
+
+/* Reset Handler */
+
+ .section .cs3.reset,"x",%progbits
+ .thumb_func
+ .globl __cs3_reset_cortex_m
+ .type __cs3_reset_cortex_m, %function
+__cs3_reset_cortex_m:
+ .fnstart
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0,=_start
+ BX R0
+ .pool
+ .cantunwind
+ .fnend
+ .size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
+
+ .section ".text"
+
+/* Exception Handlers */
+
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ B .
+ .size NMI_Handler, . - NMI_Handler
+
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ B .
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .weak MemManage_Handler
+ .type MemManage_Handler, %function
+MemManage_Handler:
+ B .
+ .size MemManage_Handler, . - MemManage_Handler
+
+ .weak BusFault_Handler
+ .type BusFault_Handler, %function
+BusFault_Handler:
+ B .
+ .size BusFault_Handler, . - BusFault_Handler
+
+ .weak UsageFault_Handler
+ .type UsageFault_Handler, %function
+UsageFault_Handler:
+ B .
+ .size UsageFault_Handler, . - UsageFault_Handler
+
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ B .
+ .size SVC_Handler, . - SVC_Handler
+
+ .weak DebugMon_Handler
+ .type DebugMon_Handler, %function
+DebugMon_Handler:
+ B .
+ .size DebugMon_Handler, . - DebugMon_Handler
+
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ B .
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ B .
+ .size SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+ .globl Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ B .
+ .size Default_Handler, . - Default_Handler
+
+ .macro def_irq_handler handler
+ .weak \handler
+ .set \handler, Default_Handler
+ .endm
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/GCC/ARMCMx.ld b/CMSIS/RTOS/RTX/Templates/CM4/GCC/ARMCMx.ld
new file mode 100644
index 0000000..e89c98f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/GCC/ARMCMx.ld
@@ -0,0 +1,188 @@
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64k
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 16k
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/GCC/Sim.ini b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Sim.ini
new file mode 100644
index 0000000..9ff8832
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Sim.ini
@@ -0,0 +1 @@
+MAP 0x20000000,0x20003FFF READ WRITE
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvopt b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvopt
new file mode 100644
index 0000000..a8979fa
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvopt
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Extensions>
+ <cExt>*.c</cExt>
+ <aExt>*.s*; *.src; *.a*</aExt>
+ <oExt>*.obj</oExt>
+ <lExt>*.lib</lExt>
+ <tExt>*.txt; *.h; *.inc</tExt>
+ <pExt>*.plm</pExt>
+ <CppX>*.cpp</CppX>
+ </Extensions>
+
+ <DaveTm>
+ <dwLowDateTime>0</dwLowDateTime>
+ <dwHighDateTime>0</dwHighDateTime>
+ </DaveTm>
+
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <CLKARM>12000000</CLKARM>
+ <OPTTT>
+ <gFlags>1</gFlags>
+ <BeepAtEnd>1</BeepAtEnd>
+ <RunSim>1</RunSim>
+ <RunTarget>0</RunTarget>
+ </OPTTT>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <FlashByte>65535</FlashByte>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ </OPTHX>
+ <OPTLEX>
+ <PageWidth>120</PageWidth>
+ <PageLength>65</PageLength>
+ <TabStop>8</TabStop>
+ <ListingPath>.\lst\</ListingPath>
+ </OPTLEX>
+ <ListingPage>
+ <CreateCListing>1</CreateCListing>
+ <CreateAListing>1</CreateAListing>
+ <CreateLListing>1</CreateLListing>
+ <CreateIListing>0</CreateIListing>
+ <AsmCond>1</AsmCond>
+ <AsmSymb>1</AsmSymb>
+ <AsmXref>0</AsmXref>
+ <CCond>1</CCond>
+ <CCode>0</CCode>
+ <CListInc>0</CListInc>
+ <CSymb>0</CSymb>
+ <LinkerCodeListing>0</LinkerCodeListing>
+ </ListingPage>
+ <OPTXL>
+ <LMap>1</LMap>
+ <LComments>1</LComments>
+ <LGenerateSymbols>1</LGenerateSymbols>
+ <LLibSym>1</LLibSym>
+ <LLines>1</LLines>
+ <LLocSym>1</LLocSym>
+ <LPubSym>1</LPubSym>
+ <LXref>0</LXref>
+ <LExpSel>0</LExpSel>
+ </OPTXL>
+ <OPTFL>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <IsCurrentTarget>1</IsCurrentTarget>
+ </OPTFL>
+ <CpuCode>255</CpuCode>
+ <DllOpt>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDllName>DCM.DLL</SimDlgDllName>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDllName>TCM.DLL</TargetDlgDllName>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOpt>
+ <DebugOpt>
+ <uSim>1</uSim>
+ <uTrg>0</uTrg>
+ <sLdApp>1</sLdApp>
+ <sGomain>1</sGomain>
+ <sRbreak>1</sRbreak>
+ <sRwatch>1</sRwatch>
+ <sRmem>1</sRmem>
+ <sRfunc>1</sRfunc>
+ <sRbox>1</sRbox>
+ <tLdApp>1</tLdApp>
+ <tGomain>0</tGomain>
+ <tRbreak>1</tRbreak>
+ <tRwatch>1</tRwatch>
+ <tRmem>1</tRmem>
+ <tRfunc>0</tRfunc>
+ <tRbox>1</tRbox>
+ <tRtrace>0</tRtrace>
+ <sRunDeb>0</sRunDeb>
+ <sLrtime>0</sLrtime>
+ <nTsel>-1</nTsel>
+ <sDll></sDll>
+ <sDllPa></sDllPa>
+ <sDlgDll></sDlgDll>
+ <sDlgPa></sDlgPa>
+ <sIfile>.\Sim.ini</sIfile>
+ <tDll></tDll>
+ <tDllPa></tDllPa>
+ <tDlgDll></tDlgDll>
+ <tDlgPa></tDlgPa>
+ <tIfile></tIfile>
+ <pMon></pMon>
+ </DebugOpt>
+ <TargetDriverDllRegistry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>DLGDARM</Key>
+ <Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)</Name>
+ </SetRegEntry>
+ <SetRegEntry>
+ <Number>0</Number>
+ <Key>ARMDBGFLAGS</Key>
+ <Name>-T0</Name>
+ </SetRegEntry>
+ </TargetDriverDllRegistry>
+ <Breakpoint/>
+ <DebugFlag>
+ <trace>0</trace>
+ <periodic>1</periodic>
+ <aLwin>1</aLwin>
+ <aCover>0</aCover>
+ <aSer1>0</aSer1>
+ <aSer2>0</aSer2>
+ <aPa>0</aPa>
+ <viewmode>1</viewmode>
+ <vrSel>0</vrSel>
+ <aSym>0</aSym>
+ <aTbox>0</aTbox>
+ <AscS1>0</AscS1>
+ <AscS2>0</AscS2>
+ <AscS3>0</AscS3>
+ <aSer3>0</aSer3>
+ <eProf>0</eProf>
+ <aLa>0</aLa>
+ <aPa1>0</aPa1>
+ <AscS4>0</AscS4>
+ <aSer4>0</aSer4>
+ <StkLoc>0</StkLoc>
+ <TrcWin>0</TrcWin>
+ <newCpu>0</newCpu>
+ <uProt>0</uProt>
+ </DebugFlag>
+ <Tracepoint>
+ <THDelay>0</THDelay>
+ </Tracepoint>
+ <LintExecutable></LintExecutable>
+ <LintConfigFile></LintConfigFile>
+ </TargetOption>
+ </Target>
+
+ <Group>
+ <GroupName>Startup</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>1</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>127</TopLine>
+ <CurrentLine>142</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>.\startup_ARMCM4.S</PathWithFileName>
+ <FilenameWithoutPath>startup_ARMCM4.S</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ <File>
+ <GroupNumber>1</GroupNumber>
+ <FileNumber>2</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../system_ARMCM4.c</PathWithFileName>
+ <FilenameWithoutPath>system_ARMCM4.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>2</GroupNumber>
+ <FileNumber>3</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../RTX_Conf_CM.c</PathWithFileName>
+ <FilenameWithoutPath>RTX_Conf_CM.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>3</GroupNumber>
+ <FileNumber>4</FileNumber>
+ <FileType>4</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>0</TopLine>
+ <CurrentLine>0</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../../LIB/GCC/libRTX_CM4.a</PathWithFileName>
+ <FilenameWithoutPath>libRTX_CM4.a</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <tvExp>1</tvExp>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <cbSel>0</cbSel>
+ <RteFlg>0</RteFlg>
+ <File>
+ <GroupNumber>4</GroupNumber>
+ <FileNumber>5</FileNumber>
+ <FileType>1</FileType>
+ <tvExp>0</tvExp>
+ <Focus>0</Focus>
+ <ColumnNumber>0</ColumnNumber>
+ <tvExpOptDlg>0</tvExpOptDlg>
+ <TopLine>1</TopLine>
+ <CurrentLine>4</CurrentLine>
+ <bDave2>0</bDave2>
+ <PathWithFileName>../../main.c</PathWithFileName>
+ <FilenameWithoutPath>main.c</FilenameWithoutPath>
+ <RteFlg>0</RteFlg>
+ <bShared>0</bShared>
+ </File>
+ </Group>
+
+</ProjectOpt>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvproj b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvproj
new file mode 100644
index 0000000..affc602
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/GCC/Template.uvproj
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
+
+ <SchemaVersion>1.1</SchemaVersion>
+
+ <Header>### uVision Project, (C) Keil Software</Header>
+
+ <Targets>
+ <Target>
+ <TargetName>Simulator</TargetName>
+ <ToolsetNumber>0x3</ToolsetNumber>
+ <ToolsetName>ARM-GNU</ToolsetName>
+ <TargetOption>
+ <TargetCommonOption>
+ <Device>Cortex-M4 FPU</Device>
+ <Vendor>ARM</Vendor>
+ <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2</Cpu>
+ <FlashUtilSpec></FlashUtilSpec>
+ <StartupFile></StartupFile>
+ <FlashDriverDll></FlashDriverDll>
+ <DeviceId>5237</DeviceId>
+ <RegisterFile></RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath></RegisterFilePath>
+ <DBRegisterFilePath></DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\obj\</OutputDirectory>
+ <OutputName>Template</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>0</BrowseInformation>
+ <ListingPath>.\lst\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments></SimDllArguments>
+ <SimDlgDll>DCM.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pCM4</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments></TargetDllArguments>
+ <TargetDlgDll>TCM.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>-1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile>.\Sim.ini</InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2></Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArm>
+ <ArmMisc>
+ <asLst>0</asLst>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>1</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <GCPUTYP>"Cortex-M4"</GCPUTYP>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>0</hadIROM>
+ <hadIRAM>0</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>2</RvdsVP>
+ <hadIRAM2>0</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM>
+ <IROM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <IRAM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IRAM2>
+ <IROM2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </IROM2>
+ </OnChipMemories>
+ </ArmMisc>
+ <Carm>
+ <arpcs>0</arpcs>
+ <stkchk>0</stkchk>
+ <reentr>0</reentr>
+ <interw>0</interw>
+ <bigend>0</bigend>
+ <Strict>0</Strict>
+ <Optim>2</Optim>
+ <wLevel>2</wLevel>
+ <uThumb>1</uThumb>
+ <VariousControls>
+ <MiscControls>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\;..\..\..\INC</IncludePath>
+ </VariousControls>
+ </Carm>
+ <Aarm>
+ <bBE>0</bBE>
+ <interw>0</interw>
+ <VariousControls>
+ <MiscControls>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard</MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aarm>
+ <LDarm>
+ <umfTarg>1</umfTarg>
+ <enaGarb>0</enaGarb>
+ <noStart>0</noStart>
+ <noStLib>0</noStLib>
+ <uMathLib>0</uMathLib>
+ <TextAddressRange></TextAddressRange>
+ <DataAddressRange></DataAddressRange>
+ <BSSAddressRange></BSSAddressRange>
+ <IncludeLibs></IncludeLibs>
+ <IncludeDir></IncludeDir>
+ <Misc>-mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -Wl,--gc-sections</Misc>
+ <ScatterFile>.\ARMCMx.ld</ScatterFile>
+ </LDarm>
+ </TargetArm>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Startup</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_ARMCM4.S</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\startup_ARMCM4.S</FilePath>
+ </File>
+ <File>
+ <FileName>system_ARMCM4.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../system_ARMCM4.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Configuration</GroupName>
+ <Files>
+ <File>
+ <FileName>RTX_Conf_CM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../RTX_Conf_CM.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>RTX Library</GroupName>
+ <Files>
+ <File>
+ <FileName>libRTX_CM4.a</FileName>
+ <FileType>4</FileType>
+ <FilePath>../../../LIB/GCC/libRTX_CM4.a</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Source Files</GroupName>
+ <Files>
+ <File>
+ <FileName>main.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>../../main.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/GCC/startup_ARMCM4.S b/CMSIS/RTOS/RTX/Templates/CM4/GCC/startup_ARMCM4.S
new file mode 100644
index 0000000..3342e95
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/GCC/startup_ARMCM4.S
@@ -0,0 +1,314 @@
+/* File: startup_ARMCM4.S
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V2.0
+ * Date: 16 August 2013
+ *
+ */
+/* Copyright (c) 2011 - 2013 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x00000400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x00000C00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long WDT_IRQHandler /* 0: Watchdog Timer */
+ .long RTC_IRQHandler /* 1: Real Time Clock */
+ .long TIM0_IRQHandler /* 2: Timer0 / Timer1 */
+ .long TIM2_IRQHandler /* 3: Timer2 / Timer3 */
+ .long MCIA_IRQHandler /* 4: MCIa */
+ .long MCIB_IRQHandler /* 5: MCIb */
+ .long UART0_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long UART1_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long UART2_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long UART4_IRQHandler /* 9: UART4 - not connected */
+ .long AACI_IRQHandler /* 10: AACI / AC97 */
+ .long CLCD_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long ENET_IRQHandler /* 12: Ethernet */
+ .long USBDC_IRQHandler /* 13: USB Device */
+ .long USBHC_IRQHandler /* 14: USB Host Controller */
+ .long CHLCD_IRQHandler /* 15: Character LCD */
+ .long FLEXRAY_IRQHandler /* 16: Flexray */
+ .long CAN_IRQHandler /* 17: CAN */
+ .long LIN_IRQHandler /* 18: LIN */
+ .long I2C_IRQHandler /* 19: I2C ADC/DAC */
+ .long 0 /* 20: Reserved */
+ .long 0 /* 21: Reserved */
+ .long 0 /* 22: Reserved */
+ .long 0 /* 23: Reserved */
+ .long 0 /* 24: Reserved */
+ .long 0 /* 25: Reserved */
+ .long 0 /* 26: Reserved */
+ .long 0 /* 27: Reserved */
+ .long CPU_CLCD_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long 0 /* 29: Reserved - CPU FPGA */
+ .long UART3_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long SPI_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Firstly it copies data from read only memory to RAM. There are two schemes
+ * to copy. One can copy more than one sections. Another can only copy
+ * one section. The former scheme needs more instructions and read-only
+ * data to implement than the latter.
+ * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of triplets, each of which specify:
+ * offset 0: LMA of start of a section to copy from
+ * offset 4: VMA of start of a section to copy to
+ * offset 8: size of the section to copy. Must be multiply of 4
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r4, =__copy_table_start__
+ ldr r5, =__copy_table_end__
+
+.L_loop0:
+ cmp r4, r5
+ bge .L_loop0_done
+ ldr r1, [r4]
+ ldr r2, [r4, #4]
+ ldr r3, [r4, #8]
+
+.L_loop0_0:
+ subs r3, #4
+ ittt ge
+ ldrge r0, [r1, r3]
+ strge r0, [r2, r3]
+ bge .L_loop0_0
+
+ adds r4, #12
+ b .L_loop0
+
+.L_loop0_done:
+#else
+/* Single section scheme.
+ *
+ * The ranges of copy from/to are specified by following symbols
+ * __etext: LMA of start of the section to copy from. Usually end of text
+ * __data_start__: VMA of start of the section to copy to
+ * __data_end__: VMA of end of the section to copy to
+ *
+ * All addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.L_loop1:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * There are two schemes too. One can clear multiple BSS sections. Another
+ * can only clear one section. The former is more size expensive than the
+ * latter.
+ *
+ * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/* Multiple sections scheme.
+ *
+ * Between symbol address __copy_table_start__ and __copy_table_end__,
+ * there are array of tuples specifying:
+ * offset 0: Start of a BSS section
+ * offset 4: Size of this BSS section. Must be multiply of 4
+ */
+ ldr r3, =__zero_table_start__
+ ldr r4, =__zero_table_end__
+
+.L_loop2:
+ cmp r3, r4
+ bge .L_loop2_done
+ ldr r1, [r3]
+ ldr r2, [r3, #4]
+ movs r0, 0
+
+.L_loop2_0:
+ subs r2, #4
+ itt ge
+ strge r0, [r1, r2]
+ bge .L_loop2_0
+
+ adds r3, #8
+ b .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/* Single BSS section scheme.
+ *
+ * The BSS section is specified by following symbols
+ * __bss_start__: start of the BSS section.
+ * __bss_end__: end of the BSS section.
+ *
+ * Both addresses must be aligned to 4 bytes boundary.
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.L_loop3:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+ bl SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+ bl __START
+
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak Default_Handler
+ .type Default_Handler, %function
+Default_Handler:
+ b .
+ .size Default_Handler, . - Default_Handler
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_handler NMI_Handler
+ def_irq_handler HardFault_Handler
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler SVC_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler PendSV_Handler
+ def_irq_handler SysTick_Handler
+
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler TIM0_IRQHandler
+ def_irq_handler TIM2_IRQHandler
+ def_irq_handler MCIA_IRQHandler
+ def_irq_handler MCIB_IRQHandler
+ def_irq_handler UART0_IRQHandler
+ def_irq_handler UART1_IRQHandler
+ def_irq_handler UART2_IRQHandler
+ def_irq_handler UART3_IRQHandler
+ def_irq_handler UART4_IRQHandler
+ def_irq_handler AACI_IRQHandler
+ def_irq_handler CLCD_IRQHandler
+ def_irq_handler ENET_IRQHandler
+ def_irq_handler USBDC_IRQHandler
+ def_irq_handler USBHC_IRQHandler
+ def_irq_handler CHLCD_IRQHandler
+ def_irq_handler FLEXRAY_IRQHandler
+ def_irq_handler CAN_IRQHandler
+ def_irq_handler LIN_IRQHandler
+ def_irq_handler I2C_IRQHandler
+ def_irq_handler CPU_CLCD_IRQHandler
+ def_irq_handler SPI_IRQHandler
+
+ .end
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.ewp b/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.ewp
new file mode 100644
index 0000000..48f692c
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.ewp
@@ -0,0 +1,1846 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+ <fileVersion>2</fileVersion>
+ <configuration>
+ <name>Debug</name>
+ <toolchain>
+ <name>ARM</name>
+ </toolchain>
+ <debug>1</debug>
+ <settings>
+ <name>General</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <version>21</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>ExePath</name>
+ <state>Debug\Exe</state>
+ </option>
+ <option>
+ <name>ObjPath</name>
+ <state>Debug\Obj</state>
+ </option>
+ <option>
+ <name>ListPath</name>
+ <state>Debug\List</state>
+ </option>
+ <option>
+ <name>Variant</name>
+ <version>19</version>
+ <state>39</state>
+ </option>
+ <option>
+ <name>GEndianMode</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input variant</name>
+ <version>3</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Input description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>Output variant</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>Output description</name>
+ <state>Automatic choice of formatter.</state>
+ </option>
+ <option>
+ <name>GOutputBinary</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FPU</name>
+ <version>2</version>
+ <state>5</state>
+ </option>
+ <option>
+ <name>OGCoreOrChip</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelect</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GRuntimeLibSelectSlave</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+ </option>
+ <option>
+ <name>OGProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>OGLastSavedByProductVersion</name>
+ <state>6.30.3.53229</state>
+ </option>
+ <option>
+ <name>GeneralEnableMisra</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraVerbose</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
+ </option>
+ <option>
+ <name>GenLowLevelInterface</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>GEndianModeBE</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGBufferedTerminalOutput</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GenStdoutInterface</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>GeneralMisraVer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>GeneralMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>RTConfigPath2</name>
+ <state>$TOOLKIT_DIR$\INC\c\DLib_Config_Normal.h</state>
+ </option>
+ <option>
+ <name>GFPUCoreSlave</name>
+ <version>19</version>
+ <state>39</state>
+ </option>
+ <option>
+ <name>GBECoreSlave</name>
+ <version>19</version>
+ <state>39</state>
+ </option>
+ <option>
+ <name>OGUseCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OGUseCmsisDspLib</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>ICCARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>28</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>1</debug>
+ <option>
+ <name>CCDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCPreprocFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocComments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPreprocLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMnemonics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListCMessages</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCListAssSource</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagSuppress</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagRemark</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagWarning</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCDiagError</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCAllowList</name>
+ <version>1</version>
+ <state>0000000</state>
+ </option>
+ <option>
+ <name>CCDebugInfo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IEndianMode</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IExtraOptionsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CCLangConformance</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCSignedPlainChar</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCRequirePrototypes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCDiagWarnAreErr</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCompilerRuntimeInfo</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>CCLibConfigHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>PreInclude</name>
+ <state></state>
+ </option>
+ <option>
+ <name>CompilerMisraOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCIncludePath2</name>
+ <state>..\INC</state>
+ </option>
+ <option>
+ <name>CCStdIncCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCCodeSection</name>
+ <state>.text</state>
+ </option>
+ <option>
+ <name>IInterwork2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IProcessorMode2</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptLevel</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CCOptStrategy</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCOptLevelSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules98</name>
+ <version>0</version>
+ <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+ </option>
+ <option>
+ <name>CompilerMisraRules04</name>
+ <version>0</version>
+ <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+ </option>
+ <option>
+ <name>CCPosIndRopi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndRwpi</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CCPosIndNoDynInit</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccLang</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
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+ <option>
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+ <cmdline></cmdline>
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+ <name>IlinkBufferedTerminalOutput</name>
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+ <name>IlinkStdoutInterfaceSlave</name>
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+ <name>IlinkIElfToolPostProcess</name>
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+ <name>IlinkLogAutoLibSelect</name>
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+ <name>IlinkLogRedirSymbols</name>
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+ <name>IlinkLogUnusedFragments</name>
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+ <name>IlinkCrcReverseByteOrder</name>
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+ <name>IlinkCrcUseAsInput</name>
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+ <name>RTDescription</name>
+ <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
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+ <name>OGChipSelectEditMenu</name>
+ <state>Default None</state>
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+ <name>GEndianModeBE</name>
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+ <name>IccLang</name>
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+ <name>IccCDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccAllowVLA</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCppDialect</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccExceptions</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccRTTI</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccStaticDestr</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccCppInlineSemantics</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IccCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IccFloatSemantics</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>AARM</name>
+ <archiveVersion>2</archiveVersion>
+ <data>
+ <version>8</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>AObjPrefix</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AEndian</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>ACaseSensitivity</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacroChars</name>
+ <version>0</version>
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+ </option>
+ <option>
+ <name>AWarnEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnWhat</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AWarnOne</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange1</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AWarnRange2</name>
+ <state></state>
+ </option>
+ <option>
+ <name>ADebug</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AltRegisterNames</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ADefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AList</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AListHeader</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AListing</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>Includes</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacDefs</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MacExps</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>MacExec</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OnlyAssed</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>MultiLine</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLengthCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>PageLength</name>
+ <state>80</state>
+ </option>
+ <option>
+ <name>TabSpacing</name>
+ <state>8</state>
+ </option>
+ <option>
+ <name>AXRef</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDefines</name>
+ <state>0</state>
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+ <option>
+ <name>AXRefInternal</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AXRefDual</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AFpuProcessor</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>AOutputFile</name>
+ <state>$FILE_BNAME$.o</state>
+ </option>
+ <option>
+ <name>AMultibyteSupport</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsCheck</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>ALimitErrorsEdit</name>
+ <state>100</state>
+ </option>
+ <option>
+ <name>AIgnoreStdInclude</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AUserIncludes</name>
+ <state></state>
+ </option>
+ <option>
+ <name>AExtraOptionsCheckV2</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>AExtraOptionsV2</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>OBJCOPY</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>1</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>OOCOutputFormat</name>
+ <version>2</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OCOutputOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>OOCOutputFile</name>
+ <state>Template.srec</state>
+ </option>
+ <option>
+ <name>OOCCommandLineProducer</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>OOCObjCopyEnable</name>
+ <state>0</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>CUSTOM</name>
+ <archiveVersion>3</archiveVersion>
+ <data>
+ <extensions></extensions>
+ <cmdline></cmdline>
+ </data>
+ </settings>
+ <settings>
+ <name>BICOMP</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ <settings>
+ <name>BUILDACTION</name>
+ <archiveVersion>1</archiveVersion>
+ <data>
+ <prebuild></prebuild>
+ <postbuild></postbuild>
+ </data>
+ </settings>
+ <settings>
+ <name>ILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>14</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IlinkLibIOConfig</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>XLinkMisraHandler</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkInputFileSlave</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOutputFile</name>
+ <state>Template.out</state>
+ </option>
+ <option>
+ <name>IlinkDebugInfoEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkKeepSymbols</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySymbol</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinarySegment</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkRawBinaryAlign</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkConfigDefines</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkMapFile</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkLogFile</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogInitialization</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogModule</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogSection</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogVeneer</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIcfFile</name>
+ <state>$TOOLKIT_DIR$\CONFIG\generic_cortex.icf</state>
+ </option>
+ <option>
+ <name>IlinkIcfFileSlave</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkEnableRemarks</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkSuppressDiags</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsRem</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsWarn</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkTreatAsErr</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkWarningsAreErrors</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkUseExtraOptions</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkExtraOptions</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkLowLevelInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAutoLibEnable</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkAdditionalLibs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkOverrideProgramEntryLabel</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabelSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkProgramEntryLabel</name>
+ <state>__iar_program_start</state>
+ </option>
+ <option>
+ <name>DoFill</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>FillerByte</name>
+ <state>0xFF</state>
+ </option>
+ <option>
+ <name>FillerStart</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>FillerEnd</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>CrcSize</name>
+ <version>0</version>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlign</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcAlgo</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcPoly</name>
+ <state>0x11021</state>
+ </option>
+ <option>
+ <name>CrcCompl</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcBitOrder</name>
+ <version>0</version>
+ <state>0</state>
+ </option>
+ <option>
+ <name>CrcInitialValue</name>
+ <state>0x0</state>
+ </option>
+ <option>
+ <name>DoCrc</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkBE8Slave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkBufferedTerminalOutput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkStdoutInterfaceSlave</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>CrcFullSize</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkIElfToolPostProcess</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogAutoLibSelect</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogRedirSymbols</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkLogUnusedFragments</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcReverseByteOrder</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCrcUseAsInput</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptInline</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsAllow</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptExceptionsForce</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkCmsis</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptMergeDuplSections</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkOptUseVfe</name>
+ <state>1</state>
+ </option>
+ <option>
+ <name>IlinkOptForceVfe</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackAnalysisEnable</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IlinkStackControlFile</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IlinkStackCallGraphFile</name>
+ <state></state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>IARCHIVE</name>
+ <archiveVersion>0</archiveVersion>
+ <data>
+ <version>0</version>
+ <wantNonLocal>1</wantNonLocal>
+ <debug>0</debug>
+ <option>
+ <name>IarchiveInputs</name>
+ <state></state>
+ </option>
+ <option>
+ <name>IarchiveOverride</name>
+ <state>0</state>
+ </option>
+ <option>
+ <name>IarchiveOutput</name>
+ <state>###Unitialized###</state>
+ </option>
+ </data>
+ </settings>
+ <settings>
+ <name>BILINK</name>
+ <archiveVersion>0</archiveVersion>
+ <data/>
+ </settings>
+ </configuration>
+ <group>
+ <name>RTX Configuration</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\RTX_Conf_CM.c</name>
+ </file>
+ </group>
+ <group>
+ <name>RTX Library</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\..\LIB\IAR\RTX_CM4.a</name>
+ </file>
+ </group>
+ <group>
+ <name>Source Files</name>
+ <file>
+ <name>$PROJ_DIR$\..\..\main.c</name>
+ </file>
+ </group>
+ <group>
+ <name>Startup</name>
+ <file>
+ <name>$PROJ_DIR$\startup_ARMCM4.s</name>
+ </file>
+ <file>
+ <name>$PROJ_DIR$\..\system_ARMCM4.c</name>
+ </file>
+ </group>
+</project>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.eww b/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.eww
new file mode 100644
index 0000000..e09d1b5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/IAR/Template.eww
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+ <project>
+ <path>$WS_DIR$\Template.ewp</path>
+ </project>
+ <batchBuild/>
+</workspace>
+
+
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/IAR/startup_ARMCM4.s b/CMSIS/RTOS/RTX/Templates/CM4/IAR/startup_ARMCM4.s
new file mode 100644
index 0000000..cfea95d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/IAR/startup_ARMCM4.s
@@ -0,0 +1,305 @@
+;/**************************************************************************//**
+; * @file startup_ARMCM4.s
+; * @brief CMSIS Core Device Startup File for
+; * ARMCM4 Device Series
+; * @version V1.08
+; * @date 23. November 2012
+; *
+; * @note
+; *
+; ******************************************************************************/
+;/* Copyright (c) 2011 - 2012 ARM LIMITED
+;
+; All rights reserved.
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; - Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; - Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; - Neither the name of ARM nor the names of its contributors may be used
+; to endorse or promote products derived from this software without
+; specific prior written permission.
+; *
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+; POSSIBILITY OF SUCH DAMAGE.
+; ---------------------------------------------------------------------------*/
+
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+ PUBLIC __vector_table_0x1c
+ PUBLIC __Vectors
+ PUBLIC __Vectors_End
+ PUBLIC __Vectors_Size
+
+ DATA
+
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler
+
+ DCD NMI_Handler
+ DCD HardFault_Handler
+ DCD MemManage_Handler
+ DCD BusFault_Handler
+ DCD UsageFault_Handler
+__vector_table_0x1c
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD 0
+ DCD SVC_Handler
+ DCD DebugMon_Handler
+ DCD 0
+ DCD PendSV_Handler
+ DCD SysTick_Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 0: Watchdog Timer
+ DCD RTC_IRQHandler ; 1: Real Time Clock
+ DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
+ DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
+ DCD MCIA_IRQHandler ; 4: MCIa
+ DCD MCIB_IRQHandler ; 5: MCIb
+ DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
+ DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
+ DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
+ DCD UART4_IRQHandler ; 9: UART4 - not connected
+ DCD AACI_IRQHandler ; 10: AACI / AC97
+ DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
+ DCD ENET_IRQHandler ; 12: Ethernet
+ DCD USBDC_IRQHandler ; 13: USB Device
+ DCD USBHC_IRQHandler ; 14: USB Host Controller
+ DCD CHLCD_IRQHandler ; 15: Character LCD
+ DCD FLEXRAY_IRQHandler ; 16: Flexray
+ DCD CAN_IRQHandler ; 17: CAN
+ DCD LIN_IRQHandler ; 18: LIN
+ DCD I2C_IRQHandler ; 19: I2C ADC/DAC
+ DCD 0 ; 20: Reserved
+ DCD 0 ; 21: Reserved
+ DCD 0 ; 22: Reserved
+ DCD 0 ; 23: Reserved
+ DCD 0 ; 24: Reserved
+ DCD 0 ; 25: Reserved
+ DCD 0 ; 26: Reserved
+ DCD 0 ; 27: Reserved
+ DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
+ DCD 0 ; 29: Reserved - CPU FPGA
+ DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
+ DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
+__Vectors_End
+
+__Vectors EQU __vector_table
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:REORDER(2)
+Reset_Handler
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WDT_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+WDT_IRQHandler
+ B WDT_IRQHandler
+
+ PUBWEAK RTC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+RTC_IRQHandler
+ B RTC_IRQHandler
+
+ PUBWEAK TIM0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM0_IRQHandler
+ B TIM0_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK MCIA_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIA_IRQHandler
+ B MCIA_IRQHandler
+
+ PUBWEAK MCIB_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+MCIB_IRQHandler
+ B MCIB_IRQHandler
+
+ PUBWEAK UART0_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART0_IRQHandler
+ B UART0_IRQHandler
+
+ PUBWEAK UART1_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART1_IRQHandler
+ B UART1_IRQHandler
+
+ PUBWEAK UART2_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART2_IRQHandler
+ B UART2_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK AACI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+AACI_IRQHandler
+ B AACI_IRQHandler
+
+ PUBWEAK CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CLCD_IRQHandler
+ B CLCD_IRQHandler
+
+ PUBWEAK ENET_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+ENET_IRQHandler
+ B ENET_IRQHandler
+
+ PUBWEAK USBDC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBDC_IRQHandler
+ B USBDC_IRQHandler
+
+ PUBWEAK USBHC_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+USBHC_IRQHandler
+ B USBHC_IRQHandler
+
+ PUBWEAK CHLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CHLCD_IRQHandler
+ B CHLCD_IRQHandler
+
+ PUBWEAK FLEXRAY_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+FLEXRAY_IRQHandler
+ B FLEXRAY_IRQHandler
+
+ PUBWEAK CAN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CAN_IRQHandler
+ B CAN_IRQHandler
+
+ PUBWEAK LIN_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+LIN_IRQHandler
+ B LIN_IRQHandler
+
+ PUBWEAK I2C_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+I2C_IRQHandler
+ B I2C_IRQHandler
+
+ PUBWEAK CPU_CLCD_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+CPU_CLCD_IRQHandler
+ B CPU_CLCD_IRQHandler
+
+ PUBWEAK UART3_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+UART3_IRQHandler
+ B UART3_IRQHandler
+
+ PUBWEAK SPI_IRQHandler
+ SECTION .text:CODE:REORDER(1)
+SPI_IRQHandler
+ B SPI_IRQHandler
+
+ END
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.c b/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.c
new file mode 100644
index 0000000..c2fc220
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.c
@@ -0,0 +1,88 @@
+/**************************************************************************//**
+ * @file system_ARMCM4.c
+ * @brief CMSIS Device System Source File for
+ * ARMCM4 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#include "ARMCM4.h"
+
+/*----------------------------------------------------------------------------
+ Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI ( 8000000UL)
+#define __XTAL ( 5000000UL) /* Oscillator frequency */
+
+#define __SYSTEM_CLOCK (5*__XTAL)
+
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+ #if (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
+ (3UL << 11*2) ); /* set CP11 Full Access */
+ #endif
+
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+ SystemCoreClock = __SYSTEM_CLOCK;
+
+}
diff --git a/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.h b/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.h
new file mode 100644
index 0000000..b5d605b
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/CM4/system_ARMCM4.h
@@ -0,0 +1,75 @@
+/**************************************************************************//**
+ * @file system_ARMCM4.h
+ * @brief CMSIS Device System Header File for
+ * ARMCM4 Device Series
+ * @version V1.08
+ * @date 23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef SYSTEM_ARMCM4_H
+#define SYSTEM_ARMCM4_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_ARMCM4_H */
diff --git a/CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c b/CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c
new file mode 100644
index 0000000..1db6c47
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/RTX_Conf_CM.c
@@ -0,0 +1,313 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS - RTX
+ *----------------------------------------------------------------------------
+ * Name: RTX_Conf_CM.C
+ * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ * Rev.: V4.70.1
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// <h>Thread Configuration
+// =======================
+//
+// <o>Number of concurrent running user threads <1-250>
+// <i> Defines max. number of user threads that will run at the same time.
+// <i> Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT 6
+#endif
+
+// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
+// <i> Defines default stack size for threads with osThreadDef stacksz = 0
+// <i> Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE 50 // this stack size value is in words
+#endif
+
+// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
+// <i> Defines stack size for main thread.
+// <i> Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 50 // this stack size value is in words
+#endif
+
+// <o>Number of threads with user-provided stack size <0-250>
+// <i> Defines the number of threads with user-provided stack size.
+// <i> Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT 0
+#endif
+
+// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
+// <i> Defines the combined stack size for threads with user-provided stack size.
+// <i> Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 0 // this stack size value is in words
+#endif
+
+// <q>Stack overflow checking
+// <i> Enable stack overflow checks at thread switch.
+// <i> Enabling this option increases slightly the execution time of a thread switch.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK 1
+#endif
+
+// <q>Stack usage watermark
+// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
+// <i> Enabling this option increases significantly the execution time of osThreadCreate.
+#ifndef OS_STKINIT
+#define OS_STKINIT 0
+#endif
+
+// <o>Processor mode for thread execution
+// <0=> Unprivileged mode
+// <1=> Privileged mode
+// <i> Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV 1
+#endif
+
+// </h>
+
+// <h>RTX Kernel Timer Tick Configuration
+// ======================================
+// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
+// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
+// <i> as time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK 1
+#endif
+//
+// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
+// <i> Defines the input frequency of the RTOS Kernel Timer.
+// <i> When the Cortex-M SysTick timer is used, the input clock
+// <i> is on most systems identical with the core clock.
+#ifndef OS_CLOCK
+ #define OS_CLOCK 12000000
+#endif
+
+// <o>RTX Timer tick interval value [us] <1-1000000>
+// <i> The RTX Timer tick interval value is used to calculate timeout values.
+// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
+// <i> Default: 1000 (1ms)
+#ifndef OS_TICK
+ #define OS_TICK 1000
+#endif
+
+// </h>
+
+// <h>System Configuration
+// =======================
+//
+// <e>Round-Robin Thread switching
+// ===============================
+//
+// <i> Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN 1
+#endif
+
+// <o>Round-Robin Timeout [ticks] <1-1000>
+// <i> Defines how long a thread will execute before a thread switch.
+// <i> Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT 5
+#endif
+
+// </e>
+
+// <e>User Timers
+// ==============
+// <i> Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS 1
+#endif
+
+// <o>Timer Thread Priority
+// <1=> Low
+// <2=> Below Normal <3=> Normal <4=> Above Normal
+// <5=> High
+// <6=> Realtime (highest)
+// <i> Defines priority for Timer Thread
+// <i> Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO 5
+#endif
+
+// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
+// <i> Defines stack size for Timer thread.
+// <i> Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ 50 // this stack size value is in words
+#endif
+
+// <o>Timer Callback Queue size <1-32>
+// <i> Number of concurrent active timer callback functions.
+// <i> Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS 4
+#endif
+
+// </e>
+
+// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
+// <12=> 12 entries <16=> 16 entries
+// <24=> 24 entries <32=> 32 entries
+// <48=> 48 entries <64=> 64 entries
+// <96=> 96 entries
+// <i> ISR functions store requests to this buffer,
+// <i> when they are called from the interrupt handler.
+// <i> Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ 16
+#endif
+
+// </h>
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+// Define max. number system mutexes that are used to protect
+// the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT 8
+#endif
+
+/*----------------------------------------------------------------------------
+ * RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ * Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+/// \brief The idle demon is running when no other thread is ready to run
+void os_idle_demon (void) {
+
+ for (;;) {
+ /* HERE: include optional user code to be executed when no thread runs.*/
+ }
+}
+
+#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+/// \brief Initializes an alternative hardware timer as RTX kernel timer
+/// \return IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+ return (-1); /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
+/// \return Current value of the alternative hardware timer
+uint32_t os_tick_val (void) {
+ return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+/// \brief Get alternative hardware timer's overflow flag
+/// \return Overflow flag\n
+/// - 1 : overflow
+/// - 0 : no overflow
+uint32_t os_tick_ovf (void) {
+ return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+/// \brief Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+ /* ... */
+}
+
+#endif // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+/* OS Error Codes */
+#define OS_ERROR_STACK_OVF 1
+#define OS_ERROR_FIFO_OVF 2
+#define OS_ERROR_MBX_OVF 3
+#define OS_ERROR_TIMER_OVF 4
+
+extern osThreadId svcThreadGetId (void);
+
+/// \brief Called when a runtime error is detected
+/// \param[in] error_code actual error code that has been detected
+void os_error (uint32_t error_code) {
+
+ /* HERE: include optional code to be executed on runtime error. */
+ switch (error_code) {
+ case OS_ERROR_STACK_OVF:
+ /* Stack overflow detected for the currently running task. */
+ /* Thread can be identified by calling svcThreadGetId(). */
+ break;
+ case OS_ERROR_FIFO_OVF:
+ /* ISR FIFO Queue buffer overflow detected. */
+ break;
+ case OS_ERROR_MBX_OVF:
+ /* Mailbox overflow detected. */
+ break;
+ case OS_ERROR_TIMER_OVF:
+ /* User Timer Callback Queue overflow detected. */
+ break;
+ default:
+ break;
+ }
+ for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ * RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/CMSIS/RTOS/RTX/Templates/main.c b/CMSIS/RTOS/RTX/Templates/main.c
new file mode 100644
index 0000000..a8b4bb5
--- /dev/null
+++ b/CMSIS/RTOS/RTX/Templates/main.c
@@ -0,0 +1,6 @@
+
+#include "cmsis_os.h" // CMSIS-RTOS API Functions
+
+int main (void) { // 'main' Thread Function
+ for (;;);
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c b/CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c
new file mode 100644
index 0000000..e006f9a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/MailQueue.c
@@ -0,0 +1,71 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Mail Queue creation & usage
+ *---------------------------------------------------------------------------*/
+
+void Thread_MailQueue1 (void const *argument); // thread function 1
+void Thread_MailQueue2 (void const *argument); // thread function 2
+osThreadId tid_Thread_MailQueue1; // thread id 1
+osThreadId tid_Thread_MailQueue2; // thread id 2
+osThreadDef (Thread_MailQueue1, osPriorityNormal, 1, 0); // thread object 1
+osThreadDef (Thread_MailQueue2, osPriorityNormal, 1, 0); // thread object 2
+
+#define MAILQUEUE_OBJECTS 16 // number of Message Queue Objects
+typedef struct { // object data type
+ uint8_t Buf[32];
+ uint8_t Idx;
+} MAILQUEUE_OBJ_t;
+
+osMailQId qid_MailQueue; // mail queue id
+osMailQDef (MailQueue, MAILQUEUE_OBJECTS, MAILQUEUE_OBJ_t); // mail queue object
+
+
+int Init_MailQueue (void) {
+
+ qid_MailQueue = osMailCreate (osMailQ(MailQueue), NULL); // create mail queue
+ if (!qid_MailQueue) {
+ ; // Mail Queue object not created, handle failure
+ }
+
+ tid_Thread_MailQueue1 = osThreadCreate (osThread(Thread_MailQueue1), NULL);
+ if (!tid_Thread_MailQueue1) return(-1);
+ tid_Thread_MailQueue2 = osThreadCreate (osThread(Thread_MailQueue2), NULL);
+ if (!tid_Thread_MailQueue2) return(-1);
+
+ return(0);
+}
+
+void Thread_MailQueue1 (void const *argument) {
+ MAILQUEUE_OBJ_t *pMail = 0;
+
+ while (1) {
+ ; // Insert thread code here...
+ pMail = osMailAlloc (qid_MailQueue, osWaitForever); // Allocate memory
+ if (pMail) {
+ pMail->Buf[0] = 0xff; // Set the mail content
+ pMail->Idx = 0;
+ osMailPut (qid_MailQueue, pMail); // Send Mail
+ }
+
+ osThreadYield (); // suspend thread
+ }
+}
+
+void Thread_MailQueue2 (void const *argument) {
+ MAILQUEUE_OBJ_t *pMail = 0;
+ osEvent evt;
+
+ while (1) {
+ ; // Insert thread code here...
+ evt = osMailGet (qid_MailQueue, osWaitForever); // wait for mail
+ if (evt.status == osEventMail) {
+ pMail = evt.value.p;
+ if (pMail) {
+ ; // process data
+ osMailFree (qid_MailQueue, pMail); // free memory allocated for mail
+ }
+ }
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c b/CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c
new file mode 100644
index 0000000..67f159a
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/MemPool.c
@@ -0,0 +1,63 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Memory Pool creation & usage
+ *---------------------------------------------------------------------------*/
+
+#define MEMPOOL_OBJECTS 16 // number of Memory Pool Objects
+
+typedef struct { // object data type
+ uint8_t Buf[32];
+ uint8_t Idx;
+} MEM_BLOCK_t;
+
+void Thread_MemPool (void const *argument); // thread function
+osThreadId tid_Thread_MemPool; // thread id
+osThreadDef (Thread_MemPool, osPriorityNormal, 1, 0); // thread object
+
+osPoolId mpid_MemPool; // memory pool id
+osPoolDef (MemPool, MEMPOOL_OBJECTS, MEM_BLOCK_t); // memory pool object
+
+
+int Init_MemPool (void) {
+
+ mpid_MemPool = osPoolCreate (osPool (MemPool)); // create Mem Pool
+ if (!mpid_MemPool) {
+ ; // MemPool object not created, handle failure
+ }
+
+ tid_Thread_MemPool = osThreadCreate (osThread(Thread_MemPool), NULL);
+ if (!tid_Thread_MemPool) return(-1);
+
+ return(0);
+}
+
+void Thread_MemPool (void const *argument) {
+ osStatus status;
+ MEM_BLOCK_t *pMem = 0;
+
+ while (1) {
+ ; // Insert thread code here...
+
+ pMem = (MEM_BLOCK_t *)osPoolCAlloc (mpid_MemPool); // get Mem Block
+ if (pMem) { // Mem Block was available
+ pMem->Buf[0] = 0x55; // do some work...
+ pMem->Idx = 0;
+
+ status = osPoolFree (mpid_MemPool, pMem); // free mem block
+ switch (status) {
+ case osOK:
+ break;
+ case osErrorParameter:
+ break;
+ case osErrorValue:
+ break;
+ default:
+ break;
+ }
+ }
+
+ osThreadYield (); // suspend thread
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c b/CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c
new file mode 100644
index 0000000..9d8626d
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/MsgQueue.c
@@ -0,0 +1,85 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Message Queue creation & usage
+ *---------------------------------------------------------------------------*/
+
+void Thread_MsgQueue1 (void const *argument); // thread function 1
+void Thread_MsgQueue2 (void const *argument); // thread function 2
+osThreadId tid_Thread_MsgQueue1; // thread id 1
+osThreadId tid_Thread_MsgQueue2; // thread id 2
+osThreadDef (Thread_MsgQueue1, osPriorityNormal, 1, 0); // thread object 1
+osThreadDef (Thread_MsgQueue2, osPriorityNormal, 1, 0); // thread object 2
+
+#define MSGQUEUE_OBJECTS 16 // number of Message Queue Objects
+
+typedef struct { // object data type
+ uint8_t Buf[32];
+ uint8_t Idx;
+} MEM_BLOCK_t;
+
+typedef struct { // object data type
+ uint8_t Buf[32];
+ uint8_t Idx;
+} MSGQUEUE_OBJ_t;
+
+osPoolId mpid_MemPool2; // memory pool id
+osPoolDef (MemPool2, MSGQUEUE_OBJECTS, MEM_BLOCK_t); // memory pool object
+
+osMessageQId mid_MsgQueue; // message queue id
+osMessageQDef (MsgQueue, MSGQUEUE_OBJECTS, MSGQUEUE_OBJ_t); // message queue object
+
+
+int Init_MsgQueue (void) {
+
+ mpid_MemPool2 = osPoolCreate (osPool (MemPool2)); // create Mem Pool
+ if (!mpid_MemPool2) {
+ ; // MemPool object not created, handle failure
+ }
+
+ mid_MsgQueue = osMessageCreate (osMessageQ(MsgQueue), NULL); // create msg queue
+ if (!mid_MsgQueue) {
+ ; // Message Queue object not created, handle failure
+ }
+
+ tid_Thread_MsgQueue1 = osThreadCreate (osThread(Thread_MsgQueue1), NULL);
+ if (!tid_Thread_MsgQueue1) return(-1);
+ tid_Thread_MsgQueue2 = osThreadCreate (osThread(Thread_MsgQueue2), NULL);
+ if (!tid_Thread_MsgQueue2) return(-1);
+
+ return(0);
+}
+
+void Thread_MsgQueue1 (void const *argument) {
+ MEM_BLOCK_t *pMsg = 0;
+
+ while (1) {
+ ; // Insert thread code here...
+ pMsg = (MEM_BLOCK_t *)osPoolCAlloc (mpid_MemPool2); // get Mem Block
+ if (pMsg) { // Mem Block was available
+ pMsg->Buf[0] = 0x55; // do some work...
+ pMsg->Idx = 0;
+ osMessagePut (mid_MsgQueue, (uint32_t)pMsg, osWaitForever); // Send Message
+ }
+
+ osThreadYield (); // suspend thread
+ }
+}
+
+void Thread_MsgQueue2 (void const *argument) {
+ osEvent evt;
+ MEM_BLOCK_t *pMsg = 0;
+
+ while (1) {
+ ; // Insert thread code here...
+ evt = osMessageGet (mid_MsgQueue, osWaitForever); // wait for message
+ if (evt.status == osEventMessage) {
+ pMsg = evt.value.p;
+ if (pMsg) {
+ ; // process data
+ osPoolFree (mpid_MemPool2, pMsg); // free memory allocated for message
+ }
+ }
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c b/CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c
new file mode 100644
index 0000000..bfb71f1
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/Mutex.c
@@ -0,0 +1,55 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Mutex creation & usage
+ *---------------------------------------------------------------------------*/
+
+void Thread_Mutex (void const *argument); // thread function
+osThreadId tid_Thread_Mutex; // thread id
+osThreadDef (Thread_Mutex, osPriorityNormal, 1, 0); // thread object
+
+osMutexId mid_Thread_Mutex; // mutex id
+osMutexDef (SampleMutex); // mutex name definition
+
+
+int Init_Mutex (void) {
+
+ mid_Thread_Mutex = osMutexCreate (osMutex (SampleMutex));
+ if (!tid_Thread_Mutex) {
+ ; // Mutex object not created, handle failure
+ }
+
+ tid_Thread_Mutex = osThreadCreate (osThread(Thread_Mutex), NULL);
+ if (!tid_Thread_Mutex) return(-1);
+
+ return(0);
+}
+
+void Thread_Mutex (void const *argument) {
+ osStatus status;
+
+ while (1) {
+ ; // Insert thread code here...
+
+ status = osMutexWait (mid_Thread_Mutex, NULL);
+ switch (status) {
+ case osOK:
+ ; // Use protected code here...
+ osMutexRelease (mid_Thread_Mutex);
+ break;
+ case osErrorTimeoutResource:
+ break;
+ case osErrorResource:
+ break;
+ case osErrorParameter:
+ break;
+ case osErrorISR:
+ break;
+ default:
+ break;
+ }
+
+ osThreadYield (); // suspend thread
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c b/CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c
new file mode 100644
index 0000000..e75b402
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/Semaphore.c
@@ -0,0 +1,51 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Semaphore creation & usage
+ *---------------------------------------------------------------------------*/
+
+void Thread_Semaphore (void const *argument); // thread function
+osThreadId tid_Thread_Semaphore; // thread id
+osThreadDef (Thread_Semaphore, osPriorityNormal, 1, 0); // thread object
+
+osSemaphoreId sid_Thread_Semaphore; // semaphore id
+osSemaphoreDef (SampleSemaphore); // semaphore object
+
+
+int Init_Semaphore (void) {
+
+ sid_Thread_Semaphore = osSemaphoreCreate (osSemaphore(SampleSemaphore), 1);
+ if (!sid_Thread_Semaphore) {
+ ; // Semaphore object not created, handle failure
+ }
+
+ tid_Thread_Semaphore = osThreadCreate (osThread(Thread_Semaphore), NULL);
+ if (!tid_Thread_Semaphore) return(-1);
+
+ return(0);
+}
+
+void Thread_Semaphore (void const *argument) {
+ int32_t val;
+
+ while (1) {
+ ; // Insert thread code here...
+
+ val = osSemaphoreWait (sid_Thread_Semaphore, 10); // wait 10 mSec
+ switch (val) {
+ case osOK:
+ ; // Use protected code here...
+ osSemaphoreRelease (sid_Thread_Semaphore); // Return a token back to a semaphore
+ break;
+ case osErrorResource:
+ break;
+ case osErrorParameter:
+ break;
+ default:
+ break;
+ }
+
+ osThreadYield (); // suspend thread
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c b/CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c
new file mode 100644
index 0000000..27be5a0
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/Thread.c
@@ -0,0 +1,26 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Thread 1 'Thread_Name': Sample thread
+ *---------------------------------------------------------------------------*/
+
+void Thread (void const *argument); // thread function
+osThreadId tid_Thread; // thread id
+osThreadDef (Thread, osPriorityNormal, 1, 0); // thread object
+
+int Init_Thread (void) {
+
+ tid_Thread = osThreadCreate (osThread(Thread), NULL);
+ if (!tid_Thread) return(-1);
+
+ return(0);
+}
+
+void Thread (void const *argument) {
+
+ while (1) {
+ ; // Insert thread code here...
+ osThreadYield (); // suspend thread
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c b/CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c
new file mode 100644
index 0000000..b073719
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/Timer.c
@@ -0,0 +1,60 @@
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+/*----------------------------------------------------------------------------
+ * Timer: Sample timer functions
+ *---------------------------------------------------------------------------*/
+
+
+/*----- One-Shoot Timer Example -----*/
+static void Timer1_Callback (void const *arg); // prototype for timer callback function
+
+static osTimerId id1; // timer id
+static uint32_t exec1; // argument for the timer call back function
+static osTimerDef (Timer1, Timer1_Callback); // define timers
+
+// One-Shoot Timer Function
+static void Timer1_Callback (void const *arg) {
+ // add user code here
+}
+
+
+/*----- Periodic Timer Example -----*/
+static void Timer2_Callback (void const *arg); // prototype for timer callback function
+
+static osTimerId id2; // timer id
+static uint32_t exec2; // argument for the timer call back function
+static osTimerDef (Timer2, Timer2_Callback);
+
+// Periodic Timer Example
+static void Timer2_Callback (void const *arg) {
+ // add user code here
+}
+
+
+// Example: Create and Start timers
+void Init_Timers (void) {
+ osStatus status; // function return status
+
+ // Create one-shoot timer
+ exec1 = 1;
+ id1 = osTimerCreate (osTimer(Timer1), osTimerOnce, &exec1);
+ if (id1 != NULL) { // One-shot timer created
+ // start timer with delay 100ms
+ status = osTimerStart (id1, 100);
+ if (status != osOK) {
+ // Timer could not be started
+ }
+ }
+
+ // Create periodic timer
+ exec2 = 2;
+ id2 = osTimerCreate (osTimer(Timer2), osTimerPeriodic, &exec2);
+ if (id2 != NULL) { // Periodic timer created
+ // start timer with periodic 1000ms interval
+ status = osTimerStart (id2, 1000);
+ if (status != osOK) {
+ // Timer could not be started
+ }
+ }
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/main.c b/CMSIS/RTOS/RTX/UserCodeTemplates/main.c
new file mode 100644
index 0000000..90aab03
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/main.c
@@ -0,0 +1,21 @@
+/*----------------------------------------------------------------------------
+ * CMSIS-RTOS 'main' function template
+ *---------------------------------------------------------------------------*/
+
+#define osObjectsPublic // define objects in main module
+#include "osObjects.h" // RTOS object definitions
+
+
+/*
+ * main: initialize and start the system
+ */
+int main (void) {
+ osKernelInitialize (); // initialize CMSIS-RTOS
+
+ // initialize peripherals here
+
+ // create 'thread' functions that start executing,
+ // example: tid_name = osThreadCreate (osThread(name), NULL);
+
+ osKernelStart (); // start thread execution
+}
diff --git a/CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h b/CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h
new file mode 100644
index 0000000..551c83f
--- /dev/null
+++ b/CMSIS/RTOS/RTX/UserCodeTemplates/osObjects.h
@@ -0,0 +1,70 @@
+/*----------------------------------------------------------------------------
+ * osObjects.h: CMSIS-RTOS global object definitions for an application
+ *----------------------------------------------------------------------------
+ *
+ * This header file defines global RTOS objects used throughout a project
+ *
+ * #define osObjectsPublic indicates that objects are defined; without that
+ * definition the objects are defined as external symbols.
+ *
+ *--------------------------------------------------------------------------*/
+
+
+#ifndef __osObjects
+#define __osObjects
+
+#if (!defined (osObjectsPublic))
+#define osObjectsExternal // define RTOS objects with extern attribute
+#endif
+
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+
+// global 'thread' functions ---------------------------------------------------
+/*
+Example:
+extern void sample_name (void const *argument); // thread function
+
+osThreadId tid_sample_name; // thread id
+osThreadDef (sample_name, osPriorityNormal, 1, 0); // thread object
+*/
+
+
+// global 'semaphores' ----------------------------------------------------------
+/*
+Example:
+osSemaphoreId sid_sample_name; // semaphore id
+osSemaphoreDef (sample_name); // semaphore object
+*/
+
+
+// global 'memory pools' --------------------------------------------------------
+/*
+Example:
+typedef struct sample_name type_sample_name; // object data type
+
+osPoolId mpid_sample_name; // memory pool id
+osPoolDef (sample_name, 16, type_sample_name); // memory pool object
+*/
+
+
+// global 'message queues' -------------------------------------------------------
+/*
+Example:
+typedef struct sample_name type_sample_name; // object data type
+
+osMessageQId mid_sample_name; // message queue id
+osMessageQDef (sample_name, 16, type_sample_name); // message queue object
+*/
+
+
+// global 'mail queues' ----------------------------------------------------------
+/*
+Example:
+typedef struct sample_name type_sample_name; // object data type
+
+osMailQId qid_sample_name; // mail queue id
+osMailQDef (sample_name, 16, type_sample_name); // mail queue object
+*/
+
+#endif // __osObjects
diff --git a/CMSIS/RTOS/Template/CPP/Mail.h b/CMSIS/RTOS/Template/CPP/Mail.h
new file mode 100644
index 0000000..d4056f4
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mail.h
@@ -0,0 +1,89 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MAIL_H
+#define MAIL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Mail class allow to control, send, receive, or wait for mail.
+ A mail is a memory block that is send to a thread or interrupt service routine.
+ \tparam T data type of a single message element.
+ \tparam queue_sz maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Mail {
+public:
+ /*! Create and Initialise Mail queue. */
+ Mail() {
+ #ifdef CMSIS_OS_RTX
+ memset(_mail_q, 0, sizeof(_mail_q));
+ _mail_p[0] = _mail_q;
+
+ memset(_mail_m, 0, sizeof(_mail_m));
+ _mail_p[1] = _mail_m;
+
+ _mail_def.pool = _mail_p;
+ _mail_def.queue_sz = queue_sz;
+ _mail_def.item_sz = sizeof(T);
+ #endif
+ _mail_id = osMailCreate(&_mail_def, NULL);
+ }
+
+ /*! Allocate a memory block of type T
+ \param millisec timeout value or 0 in case of no time-out. (default: 0).
+ \return pointer to memory block that can be filled with mail or NULL in case error.
+ */
+ T* alloc(uint32_t millisec=0) {
+ return (T*)osMailAlloc(_mail_id, millisec);
+ }
+
+ /*! Allocate a memory block of type T and set memory block to zero.
+ \param millisec timeout value or 0 in case of no time-out. (default: 0).
+ \return pointer to memory block that can be filled with mail or NULL in case error.
+ */
+ T* calloc(uint32_t millisec=0) {
+ return (T*)osMailCAlloc(_mail_id, millisec);
+ }
+
+ /*! Put a mail in the queue.
+ \param mptr memory block previously allocated with Mail::alloc or Mail::calloc.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus put(T *mptr) {
+ return osMailPut(_mail_id, (void*)mptr);
+ }
+
+ /*! Get a mail from a queue.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event that contains mail information or error code.
+ */
+ osEvent get(uint32_t millisec=osWaitForever) {
+ return osMailGet(_mail_id, millisec);
+ }
+
+ /*! Free a memory block from a mail.
+ \param mptr pointer to the memory block that was obtained with Mail::get.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus free(T *mptr) {
+ return osMailFree(_mail_id, (void*)mptr);
+ }
+
+private:
+ osMailQId _mail_id;
+ osMailQDef_t _mail_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _mail_q[4+(queue_sz)];
+ uint32_t _mail_m[3+((sizeof(T)+3)/4)*(queue_sz)];
+ void *_mail_p[2];
+#endif
+};
+
+}
+
+#endif
+
diff --git a/CMSIS/RTOS/Template/CPP/MemoryPool.h b/CMSIS/RTOS/Template/CPP/MemoryPool.h
new file mode 100644
index 0000000..f8325e8
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/MemoryPool.h
@@ -0,0 +1,62 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MEMORYPOOL_H
+#define MEMORYPOOL_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! Define and manage fixed-size memory pools of objects of a given type.
+ \tparam T data type of a single object (element).
+ \tparam queue_sz maximum number of objects (elements) in the memory pool.
+*/
+template<typename T, uint32_t pool_sz>
+class MemoryPool {
+public:
+ /*! Create and Initialize a memory pool. */
+ MemoryPool() {
+ #ifdef CMSIS_OS_RTX
+ memset(_pool_m, 0, sizeof(_pool_m));
+ _pool_def.pool = _pool_m;
+
+ _pool_def.pool_sz = pool_sz;
+ _pool_def.item_sz = sizeof(T);
+ #endif
+ _pool_id = osPoolCreate(&_pool_def);
+ }
+
+ /*! Allocate a memory block of type T from a memory pool.
+ \return address of the allocated memory block or NULL in case of no memory available.
+ */
+ T* alloc(void) {
+ return (T*)osPoolAlloc(_pool_id);
+ }
+
+ /*! Allocate a memory block of type T from a memory pool and set memory block to zero.
+ \return address of the allocated memory block or NULL in case of no memory available.
+ */
+ T* calloc(void) {
+ return (T*)osPoolCAlloc(_pool_id);
+ }
+
+ /*! Return an allocated memory block back to a specific memory pool.
+ \param address of the allocated memory block that is returned to the memory pool.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus free(T *block) {
+ return osPoolFree(_pool_id, (void*)block);
+ }
+
+private:
+ osPoolId _pool_id;
+ osPoolDef_t _pool_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _pool_m[3+((sizeof(T)+3)/4)*(pool_sz)];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Mutex.cpp b/CMSIS/RTOS/Template/CPP/Mutex.cpp
new file mode 100644
index 0000000..17469f2
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mutex.cpp
@@ -0,0 +1,31 @@
+#include "Mutex.h"
+
+#include <string.h>
+//#include "error.h"
+
+namespace rtos {
+
+Mutex::Mutex() {
+#ifdef CMSIS_OS_RTX
+ memset(_mutex_data, 0, sizeof(_mutex_data));
+ _osMutexDef.mutex = _mutex_data;
+#endif
+ _osMutexId = osMutexCreate(&_osMutexDef);
+ if (_osMutexId == NULL) {
+// error("Error initializing the mutex object\n");
+ }
+}
+
+osStatus Mutex::lock(uint32_t millisec) {
+ return osMutexWait(_osMutexId, millisec);
+}
+
+bool Mutex::trylock() {
+ return (osMutexWait(_osMutexId, 0) == osOK);
+}
+
+osStatus Mutex::unlock() {
+ return osMutexRelease(_osMutexId);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Mutex.h b/CMSIS/RTOS/Template/CPP/Mutex.h
new file mode 100644
index 0000000..09d3802
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Mutex.h
@@ -0,0 +1,43 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef MUTEX_H
+#define MUTEX_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Mutex class is used to synchronise the execution of threads.
+ This is for example used to protect access to a shared resource.
+*/
+class Mutex {
+public:
+ /*! Create and Initialize a Mutex object */
+ Mutex();
+
+ /*! Wait until a Mutex becomes available.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever)
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus lock(uint32_t millisec=osWaitForever);
+
+ /*! Try to lock the mutex, and return immediately
+ \return true if the mutex was acquired, false otherwise.
+ */
+ bool trylock();
+
+ /*! Unlock the mutex that has previously been locked by the same thread
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus unlock();
+
+private:
+ osMutexId _osMutexId;
+ osMutexDef_t _osMutexDef;
+#ifdef CMSIS_OS_RTX
+ int32_t _mutex_data[3];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Queue.h b/CMSIS/RTOS/Template/CPP/Queue.h
new file mode 100644
index 0000000..f001131
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Queue.h
@@ -0,0 +1,61 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#include <stdint.h>
+#include <string.h>
+
+#include "cmsis_os.h"
+#include "error.h"
+
+namespace rtos {
+
+/*! The Queue class allow to control, send, receive, or wait for messages.
+ A message can be a integer or pointer value to a certain type T that is send
+ to a thread or interrupt service routine.
+ \tparam T data type of a single message element.
+ \tparam queue_sz maximum number of messages in queue.
+*/
+template<typename T, uint32_t queue_sz>
+class Queue {
+public:
+ /*! Create and initialise a message Queue. */
+ Queue() {
+ #ifdef CMSIS_OS_RTX
+ memset(_queue_q, 0, sizeof(_queue_q));
+ _queue_def.pool = _queue_q;
+ _queue_def.queue_sz = queue_sz;
+ #endif
+ _queue_id = osMessageCreate(&_queue_def, NULL);
+ if (_queue_id == NULL) {
+ error("Error initialising the queue object\n");
+ }
+ }
+
+ /*! Put a message in a Queue.
+ \param data message pointer.
+ \param millisec timeout value or 0 in case of no time-out. (default: 0)
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus put(T* data, uint32_t millisec=0) {
+ return osMessagePut(_queue_id, (uint32_t)data, millisec);
+ }
+
+ /*! Get a message or Wait for a message from a Queue.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event information that includes the message and the status code.
+ */
+ osEvent get(uint32_t millisec=osWaitForever) {
+ return osMessageGet(_queue_id, millisec);
+ }
+
+private:
+ osMessageQId _queue_id;
+ osMessageQDef_t _queue_def;
+#ifdef CMSIS_OS_RTX
+ uint32_t _queue_q[4+(queue_sz)];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/RtosTimer.cpp b/CMSIS/RTOS/Template/CPP/RtosTimer.cpp
new file mode 100644
index 0000000..0f83215
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/RtosTimer.cpp
@@ -0,0 +1,28 @@
+#include "RtosTimer.h"
+
+#include <string.h>
+
+#include "cmsis_os.h"
+//#include "error.h"
+
+namespace rtos {
+
+RtosTimer::RtosTimer(void (*periodic_task)(void const *argument), os_timer_type type, void *argument) {
+#ifdef CMSIS_OS_RTX
+ _timer.ptimer = periodic_task;
+
+ memset(_timer_data, 0, sizeof(_timer_data));
+ _timer.timer = _timer_data;
+#endif
+ _timer_id = osTimerCreate(&_timer, type, argument);
+}
+
+osStatus RtosTimer::start(uint32_t millisec) {
+ return osTimerStart(_timer_id, millisec);
+}
+
+osStatus RtosTimer::stop(void) {
+ return osTimerStop(_timer_id);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/RtosTimer.h b/CMSIS/RTOS/Template/CPP/RtosTimer.h
new file mode 100644
index 0000000..6e989c1
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/RtosTimer.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef TIMER_H
+#define TIMER_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The RtosTimer class allow creating and and controlling of timer functions in the system.
+ A timer function is called when a time period expires whereby both on-shot and
+ periodic timers are possible. A timer can be started, restarted, or stopped.
+
+ Timers are handled in the thread osTimerThread.
+ Callback functions run under control of this thread and may use CMSIS-RTOS API calls.
+*/
+class RtosTimer {
+public:
+ /*! Create and Start timer.
+ \param task name of the timer call back function.
+ \param type osTimerOnce for one-shot or osTimerPeriodic for periodic behaviour. (default: osTimerPeriodic)
+ \param argument argument to the timer call back function. (default: NULL)
+ */
+ RtosTimer(void (*task)(void const *argument),
+ os_timer_type type=osTimerPeriodic,
+ void *argument=NULL);
+
+ /*! Stop the timer.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus stop(void);
+
+ /*! start a timer.
+ \param millisec time delay value of the timer.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus start(uint32_t millisec);
+
+private:
+ osTimerId _timer_id;
+ osTimerDef_t _timer;
+#ifdef CMSIS_OS_RTX
+ uint32_t _timer_data[5];
+#endif
+};
+
+}
+
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Semaphore.cpp b/CMSIS/RTOS/Template/CPP/Semaphore.cpp
new file mode 100644
index 0000000..0b7a827
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Semaphore.cpp
@@ -0,0 +1,24 @@
+#include "Semaphore.h"
+
+#include <string.h>
+//#include "error.h"
+
+namespace rtos {
+
+Semaphore::Semaphore(int32_t count) {
+#ifdef CMSIS_OS_RTX
+ memset(_semaphore_data, 0, sizeof(_semaphore_data));
+ _osSemaphoreDef.semaphore = _semaphore_data;
+#endif
+ _osSemaphoreId = osSemaphoreCreate(&_osSemaphoreDef, count);
+}
+
+int32_t Semaphore::wait(uint32_t millisec) {
+ return osSemaphoreWait(_osSemaphoreId, millisec);
+}
+
+osStatus Semaphore::release(void) {
+ return osSemaphoreRelease(_osSemaphoreId);
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Semaphore.h b/CMSIS/RTOS/Template/CPP/Semaphore.h
new file mode 100644
index 0000000..a94f277
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Semaphore.h
@@ -0,0 +1,38 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+namespace rtos {
+
+/*! The Semaphore class is used to manage and protect access to a set of shared resources. */
+class Semaphore {
+public:
+ /*! Create and Initialize a Semaphore object used for managing resources.
+ \param number of available resources; maximum index value is (count-1).
+ */
+ Semaphore(int32_t count);
+
+ /*! Wait until a Semaphore resource becomes available.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return number of available tokens, or -1 in case of incorrect parameters
+ */
+ int32_t wait(uint32_t millisec=osWaitForever);
+
+ /*! Release a Semaphore resource that was obtain with Semaphore::wait.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus release(void);
+
+private:
+ osSemaphoreId _osSemaphoreId;
+ osSemaphoreDef_t _osSemaphoreDef;
+#ifdef CMSIS_OS_RTX
+ uint32_t _semaphore_data[2];
+#endif
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/Thread.cpp b/CMSIS/RTOS/Template/CPP/Thread.cpp
new file mode 100644
index 0000000..97d8b7b
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Thread.cpp
@@ -0,0 +1,51 @@
+#include "Thread.h"
+
+namespace rtos {
+
+Thread::Thread(void (*task)(void const *argument),
+ void *argument,
+ osPriority priority,
+ uint32_t stacksize) {
+ // The actual fields of os_thread_def are implementation specific in every CMSIS-RTOS
+#ifdef CMSIS_OS_RTX
+ _thread_def.pthread = task;
+ _thread_def.tpriority = priority;
+ _thread_def.instances = 1;
+ _thread_def.stacksize = stacksize;
+#endif
+ _tid = osThreadCreate(&_thread_def, argument);
+}
+
+osStatus Thread::terminate() {
+ return osThreadTerminate(_tid);
+}
+
+osStatus Thread::set_priority(osPriority priority) {
+ return osThreadSetPriority(_tid, priority);
+}
+
+osPriority Thread::get_priority() {
+ return osThreadGetPriority(_tid);
+}
+
+int32_t Thread::signal_set(int32_t signals) {
+ return osSignalSet(_tid, signals);
+}
+
+osEvent Thread::signal_wait(int32_t signals, uint32_t millisec) {
+ return osSignalWait(signals, millisec);
+}
+
+osStatus Thread::wait(uint32_t millisec) {
+ return osDelay(millisec);
+}
+
+osStatus Thread::yield() {
+ return osThreadYield();
+}
+
+osThreadId Thread::gettid() {
+ return osThreadGetId();
+}
+
+}
diff --git a/CMSIS/RTOS/Template/CPP/Thread.h b/CMSIS/RTOS/Template/CPP/Thread.h
new file mode 100644
index 0000000..d1fd6ee
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/Thread.h
@@ -0,0 +1,78 @@
+/* Copyright (c) 2012 mbed.org */
+#ifndef THREAD_H
+#define THREAD_H
+
+#include <stdint.h>
+#include "cmsis_os.h"
+
+#define DEFAULT_STACK_SIZE 0x1000
+
+namespace rtos {
+
+/*! The Thread class allow defining, creating, and controlling thread functions in the system. */
+class Thread {
+public:
+ /*! Create a new thread, and start it executing the specified function.
+ \param task function to be executed by this thread.
+ \param argument pointer that is passed to the thread function as start argument. (default: NULL).
+ \param priority initial priority of the thread function. (default: osPriorityNormal).
+ \param stacksz stack size (in bytes) requirements for the thread function. (default: DEFAULT_STACK_SIZE).
+ */
+ Thread(void (*task)(void const *argument),
+ void *argument=NULL,
+ osPriority priority=osPriorityNormal,
+ uint32_t stacksize=DEFAULT_STACK_SIZE);
+
+ /*! Terminate execution of a thread and remove it from Active Threads
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus terminate();
+
+ /*! Set priority of an active thread
+ \param priority new priority value for the thread function.
+ \return status code that indicates the execution status of the function.
+ */
+ osStatus set_priority(osPriority priority);
+
+ /*! Get priority of an active thread
+ \ return current priority value of the thread function.
+ */
+ osPriority get_priority();
+
+ /*! Set the specified Signal Flags of an active thread.
+ \param signals specifies the signal flags of the thread that should be set.
+ \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
+ */
+ int32_t signal_set(int32_t signals);
+
+ /*! Wait for one or more Signal Flags to become signaled for the current RUNNING thread.
+ \param signals wait until all specified signal flags set or 0 for any single signal flag.
+ \param millisec timeout value or 0 in case of no time-out. (default: osWaitForever).
+ \return event flag information or error code.
+ */
+ static osEvent signal_wait(int32_t signals, uint32_t millisec=osWaitForever);
+
+
+ /*! Wait for a specified time period in millisec:
+ \param millisec time delay value
+ \return status code that indicates the execution status of the function.
+ */
+ static osStatus wait(uint32_t millisec);
+
+ /*! Pass control to next thread that is in state READY.
+ \return status code that indicates the execution status of the function.
+ */
+ static osStatus yield();
+
+ /*! Get the thread id of the current running thread.
+ \return thread ID for reference by other functions or NULL in case of error.
+ */
+ static osThreadId gettid();
+
+private:
+ osThreadId _tid;
+ osThreadDef_t _thread_def;
+};
+
+}
+#endif
diff --git a/CMSIS/RTOS/Template/CPP/rtos.h b/CMSIS/RTOS/Template/CPP/rtos.h
new file mode 100644
index 0000000..db1a785
--- /dev/null
+++ b/CMSIS/RTOS/Template/CPP/rtos.h
@@ -0,0 +1,17 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited. All rights reserved.
+ */
+#ifndef RTOS_H
+#define RTOS_H
+
+#include "Thread.h"
+#include "Mutex.h"
+#include "RtosTimer.h"
+#include "Semaphore.h"
+#include "Mail.h"
+#include "MemoryPool.h"
+#include "Queue.h"
+
+using namespace rtos;
+
+#endif
diff --git a/CMSIS/RTOS/Template/Hist.txt b/CMSIS/RTOS/Template/Hist.txt
new file mode 100644
index 0000000..8aa5cff
--- /dev/null
+++ b/CMSIS/RTOS/Template/Hist.txt
@@ -0,0 +1,39 @@
+This file describes the changes of the CMSIS-RTOS API interface for internal use
+================================================================================
+
+changes V1.0 -> V1.01
+=====================
+
+Preparation for C++ class interface
+===================================
+---> const attribute moved to macros (to support C++ interface).
+const attribute removed from typedef's (to allow C++ class interface).
+osThreadDef_t, osTimerDef_t, osMutexDef_t, osSemaphoreDef_t, osPoolDef_t, osMessageQDef_t, osMailQDef_t.
+
+const added to the osXxxxDef macros:
+osThreadDef, osTimerDef, osMutexDef, osSemaphoreDef, osPoolDef, osMessageQDef, osMailQDef
+
+Allow to remove Timer/Mutex/Semaphore objects
+=============================================
+Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
+
+
+Added function that initializes (but does not start) the osKernel
+=================================================================
+Added: osKernelInitialize
+osKernelStart changed to osKernelStart (void)
+
+====================================================================
+
+Version 1.02
+ Control functions for short timeouts in microsecond resolution:
+ Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTick_uSec
+ Removed: osSignalGet
+
+Still open for discussion
+=========================
+Adding Low Power extensions
+We have added Low Power extensions to RTX a while ago.
+http://www.keil.com/support/man/docs/rlarm/rlarm_ar_low_power.htm
+
+We should look into this solution (os_suspend/os_resume) and add this functionality to CMSIS RTOS by extending the API. Probably we can use the same two functions (renamed to fit CMSIS RTOS) but we need to check if this fits (for example os_resume parameter is in system ticks – same as in os_time_get)
diff --git a/CMSIS/RTOS/Template/Template.uvopt b/CMSIS/RTOS/Template/Template.uvopt
new file mode 100644
index 0000000..eb96e04
--- /dev/null
+++ b/CMSIS/RTOS/Template/Template.uvopt
@@ -0,0 +1,364 @@
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+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_opt.xsd">
+
+ <SchemaVersion>1.0</SchemaVersion>
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diff --git a/CMSIS/RTOS/Template/Template.uvproj b/CMSIS/RTOS/Template/Template.uvproj
new file mode 100644
index 0000000..56c7533
--- /dev/null
+++ b/CMSIS/RTOS/Template/Template.uvproj
@@ -0,0 +1,465 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+
+ <SchemaVersion>1.1</SchemaVersion>
+
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+
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+ <StartupFile>"STARTUP\NXP\LPC177x_8x\startup_LPC177x_8x.s" ("NXP LPC177x_8x Startup Code")</StartupFile>
+ <FlashDriverDll>UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000)</FlashDriverDll>
+ <DeviceId>5325</DeviceId>
+ <RegisterFile>LPC177x_8x.H</RegisterFile>
+ <MemoryEnv></MemoryEnv>
+ <Cmp></Cmp>
+ <Asm></Asm>
+ <Linker></Linker>
+ <OHString></OHString>
+ <InfinionOptionDll></InfinionOptionDll>
+ <SLE66CMisc></SLE66CMisc>
+ <SLE66AMisc></SLE66AMisc>
+ <SLE66LinkerMisc></SLE66LinkerMisc>
+ <SFDFile></SFDFile>
+ <UseEnv>0</UseEnv>
+ <BinPath></BinPath>
+ <IncludePath></IncludePath>
+ <LibPath></LibPath>
+ <RegisterFilePath>NXP\LPC177x_8x\</RegisterFilePath>
+ <DBRegisterFilePath>NXP\LPC177x_8x\</DBRegisterFilePath>
+ <TargetStatus>
+ <Error>0</Error>
+ <ExitCodeStop>0</ExitCodeStop>
+ <ButtonStop>0</ButtonStop>
+ <NotGenerated>0</NotGenerated>
+ <InvalidFlash>1</InvalidFlash>
+ </TargetStatus>
+ <OutputDirectory>.\</OutputDirectory>
+ <OutputName>RTOS</OutputName>
+ <CreateExecutable>1</CreateExecutable>
+ <CreateLib>0</CreateLib>
+ <CreateHexFile>0</CreateHexFile>
+ <DebugInformation>1</DebugInformation>
+ <BrowseInformation>1</BrowseInformation>
+ <ListingPath>.\</ListingPath>
+ <HexFormatSelection>1</HexFormatSelection>
+ <Merge32K>0</Merge32K>
+ <CreateBatchFile>0</CreateBatchFile>
+ <BeforeCompile>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ <nStopU1X>0</nStopU1X>
+ <nStopU2X>0</nStopU2X>
+ </BeforeCompile>
+ <BeforeMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </BeforeMake>
+ <AfterMake>
+ <RunUserProg1>0</RunUserProg1>
+ <RunUserProg2>0</RunUserProg2>
+ <UserProg1Name></UserProg1Name>
+ <UserProg2Name></UserProg2Name>
+ <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+ <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+ </AfterMake>
+ <SelectedForBatchBuild>0</SelectedForBatchBuild>
+ <SVCSIdString></SVCSIdString>
+ </TargetCommonOption>
+ <CommonProperty>
+ <UseCPPCompiler>0</UseCPPCompiler>
+ <RVCTCodeConst>0</RVCTCodeConst>
+ <RVCTZI>0</RVCTZI>
+ <RVCTOtherData>0</RVCTOtherData>
+ <ModuleSelection>0</ModuleSelection>
+ <IncludeInBuild>1</IncludeInBuild>
+ <AlwaysBuild>0</AlwaysBuild>
+ <GenerateAssemblyFile>0</GenerateAssemblyFile>
+ <AssembleAssemblyFile>0</AssembleAssemblyFile>
+ <PublicsOnly>0</PublicsOnly>
+ <StopOnExitCode>3</StopOnExitCode>
+ <CustomArgument></CustomArgument>
+ <IncludeLibraryModules></IncludeLibraryModules>
+ </CommonProperty>
+ <DllOption>
+ <SimDllName>SARMCM3.DLL</SimDllName>
+ <SimDllArguments>-MPU</SimDllArguments>
+ <SimDlgDll>DARMP1.DLL</SimDlgDll>
+ <SimDlgDllArguments>-pLPC1788</SimDlgDllArguments>
+ <TargetDllName>SARMCM3.DLL</TargetDllName>
+ <TargetDllArguments>-MPU</TargetDllArguments>
+ <TargetDlgDll>TARMP1.DLL</TargetDlgDll>
+ <TargetDlgDllArguments>-pLPC1788</TargetDlgDllArguments>
+ </DllOption>
+ <DebugOption>
+ <OPTHX>
+ <HexSelection>1</HexSelection>
+ <HexRangeLowAddress>0</HexRangeLowAddress>
+ <HexRangeHighAddress>0</HexRangeHighAddress>
+ <HexOffset>0</HexOffset>
+ <Oh166RecLen>16</Oh166RecLen>
+ </OPTHX>
+ <Simulator>
+ <UseSimulator>1</UseSimulator>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>1</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>1</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
+ </Simulator>
+ <Target>
+ <UseTarget>0</UseTarget>
+ <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
+ <RunToMain>0</RunToMain>
+ <RestoreBreakpoints>1</RestoreBreakpoints>
+ <RestoreWatchpoints>1</RestoreWatchpoints>
+ <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
+ <RestoreFunctions>0</RestoreFunctions>
+ <RestoreToolbox>1</RestoreToolbox>
+ <RestoreTracepoints>0</RestoreTracepoints>
+ </Target>
+ <RunDebugAfterBuild>0</RunDebugAfterBuild>
+ <TargetSelection>1</TargetSelection>
+ <SimDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ </SimDlls>
+ <TargetDlls>
+ <CpuDll></CpuDll>
+ <CpuDllArguments></CpuDllArguments>
+ <PeripheralDll></PeripheralDll>
+ <PeripheralDllArguments></PeripheralDllArguments>
+ <InitializationFile></InitializationFile>
+ <Driver></Driver>
+ </TargetDlls>
+ </DebugOption>
+ <Utilities>
+ <Flash1>
+ <UseTargetDll>1</UseTargetDll>
+ <UseExternalTool>0</UseExternalTool>
+ <RunIndependent>0</RunIndependent>
+ <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
+ <Capability>0</Capability>
+ <DriverSelection>-1</DriverSelection>
+ </Flash1>
+ <Flash2>BIN\UL2CM3.DLL</Flash2>
+ <Flash3></Flash3>
+ <Flash4></Flash4>
+ </Utilities>
+ <TargetArmAds>
+ <ArmAdsMisc>
+ <GenerateListings>0</GenerateListings>
+ <asHll>1</asHll>
+ <asAsm>1</asAsm>
+ <asMacX>1</asMacX>
+ <asSyms>1</asSyms>
+ <asFals>1</asFals>
+ <asDbgD>1</asDbgD>
+ <asForm>1</asForm>
+ <ldLst>0</ldLst>
+ <ldmm>1</ldmm>
+ <ldXref>1</ldXref>
+ <BigEnd>0</BigEnd>
+ <AdsALst>1</AdsALst>
+ <AdsACrf>1</AdsACrf>
+ <AdsANop>0</AdsANop>
+ <AdsANot>0</AdsANot>
+ <AdsLLst>1</AdsLLst>
+ <AdsLmap>1</AdsLmap>
+ <AdsLcgr>1</AdsLcgr>
+ <AdsLsym>1</AdsLsym>
+ <AdsLszi>1</AdsLszi>
+ <AdsLtoi>1</AdsLtoi>
+ <AdsLsun>1</AdsLsun>
+ <AdsLven>1</AdsLven>
+ <AdsLsxf>1</AdsLsxf>
+ <RvctClst>0</RvctClst>
+ <GenPPlst>0</GenPPlst>
+ <AdsCpuType>"Cortex-M3"</AdsCpuType>
+ <RvctDeviceName></RvctDeviceName>
+ <mOS>0</mOS>
+ <uocRom>0</uocRom>
+ <uocRam>0</uocRam>
+ <hadIROM>1</hadIROM>
+ <hadIRAM>1</hadIRAM>
+ <hadXRAM>0</hadXRAM>
+ <uocXRam>0</uocXRam>
+ <RvdsVP>0</RvdsVP>
+ <hadIRAM2>1</hadIRAM2>
+ <hadIROM2>0</hadIROM2>
+ <StupSel>8</StupSel>
+ <useUlib>0</useUlib>
+ <EndSel>0</EndSel>
+ <uLtcg>0</uLtcg>
+ <RoSelD>3</RoSelD>
+ <RwSelD>3</RwSelD>
+ <CodeSel>0</CodeSel>
+ <OptFeed>0</OptFeed>
+ <NoZi1>0</NoZi1>
+ <NoZi2>0</NoZi2>
+ <NoZi3>0</NoZi3>
+ <NoZi4>0</NoZi4>
+ <NoZi5>0</NoZi5>
+ <Ro1Chk>0</Ro1Chk>
+ <Ro2Chk>0</Ro2Chk>
+ <Ro3Chk>0</Ro3Chk>
+ <Ir1Chk>1</Ir1Chk>
+ <Ir2Chk>0</Ir2Chk>
+ <Ra1Chk>0</Ra1Chk>
+ <Ra2Chk>0</Ra2Chk>
+ <Ra3Chk>0</Ra3Chk>
+ <Im1Chk>1</Im1Chk>
+ <Im2Chk>0</Im2Chk>
+ <OnChipMemories>
+ <Ocm1>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm1>
+ <Ocm2>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm2>
+ <Ocm3>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm3>
+ <Ocm4>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm4>
+ <Ocm5>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm5>
+ <Ocm6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </Ocm6>
+ <IRAM>
+ <Type>0</Type>
+ <StartAddress>0x10000000</StartAddress>
+ <Size>0x10000</Size>
+ </IRAM>
+ <IROM>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </IROM>
+ <XRAM>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </XRAM>
+ <OCR_RVCT1>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT1>
+ <OCR_RVCT2>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT2>
+ <OCR_RVCT3>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT3>
+ <OCR_RVCT4>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x80000</Size>
+ </OCR_RVCT4>
+ <OCR_RVCT5>
+ <Type>1</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT5>
+ <OCR_RVCT6>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT6>
+ <OCR_RVCT7>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT7>
+ <OCR_RVCT8>
+ <Type>0</Type>
+ <StartAddress>0x0</StartAddress>
+ <Size>0x0</Size>
+ </OCR_RVCT8>
+ <OCR_RVCT9>
+ <Type>0</Type>
+ <StartAddress>0x10000000</StartAddress>
+ <Size>0x10000</Size>
+ </OCR_RVCT9>
+ <OCR_RVCT10>
+ <Type>0</Type>
+ <StartAddress>0x20000000</StartAddress>
+ <Size>0x8000</Size>
+ </OCR_RVCT10>
+ </OnChipMemories>
+ <RvctStartVector></RvctStartVector>
+ </ArmAdsMisc>
+ <Cads>
+ <interw>1</interw>
+ <Optim>1</Optim>
+ <oTime>0</oTime>
+ <SplitLS>0</SplitLS>
+ <OneElfS>0</OneElfS>
+ <Strict>0</Strict>
+ <EnumInt>0</EnumInt>
+ <PlainCh>0</PlainCh>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <wLevel>2</wLevel>
+ <uThumb>0</uThumb>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath>..\Template</IncludePath>
+ </VariousControls>
+ </Cads>
+ <Aads>
+ <interw>1</interw>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <thumb>0</thumb>
+ <SplitLS>0</SplitLS>
+ <SwStkChk>0</SwStkChk>
+ <NoWarn>0</NoWarn>
+ <uSurpInc>0</uSurpInc>
+ <VariousControls>
+ <MiscControls></MiscControls>
+ <Define></Define>
+ <Undefine></Undefine>
+ <IncludePath></IncludePath>
+ </VariousControls>
+ </Aads>
+ <LDads>
+ <umfTarg>1</umfTarg>
+ <Ropi>0</Ropi>
+ <Rwpi>0</Rwpi>
+ <noStLib>0</noStLib>
+ <RepFail>1</RepFail>
+ <useFile>0</useFile>
+ <TextAddressRange>0x00000000</TextAddressRange>
+ <DataAddressRange>0x10000000</DataAddressRange>
+ <ScatterFile></ScatterFile>
+ <IncludeLibs></IncludeLibs>
+ <IncludeLibsPath></IncludeLibsPath>
+ <Misc></Misc>
+ <LinkerInputFile></LinkerInputFile>
+ <DisabledWarnings></DisabledWarnings>
+ </LDads>
+ </TargetArmAds>
+ </TargetOption>
+ <Groups>
+ <Group>
+ <GroupName>Source Group 1</GroupName>
+ <Files>
+ <File>
+ <FileName>startup_LPC177x_8x.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\startup_LPC177x_8x.s</FilePath>
+ </File>
+ <File>
+ <FileName>system_LPC177x_8x.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\system_LPC177x_8x.c</FilePath>
+ </File>
+ <File>
+ <FileName>os_sample.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\os_sample.c</FilePath>
+ </File>
+ <File>
+ <FileName>os_sample1.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\os_sample1.c</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>CPP</GroupName>
+ <Files>
+ <File>
+ <FileName>Mutex.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Mutex.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>RtosTimer.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\RtosTimer.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>Semaphore.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Semaphore.cpp</FilePath>
+ </File>
+ <File>
+ <FileName>Thread.cpp</FileName>
+ <FileType>8</FileType>
+ <FilePath>.\CPP\Thread.cpp</FilePath>
+ </File>
+ </Files>
+ </Group>
+ <Group>
+ <GroupName>Documentation</GroupName>
+ <Files>
+ <File>
+ <FileName>cmsis_os.txt</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\src\cmsis_os.txt</FilePath>
+ </File>
+ <File>
+ <FileName>doxygen_rtos.bat</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\doxygen_rtos.bat</FilePath>
+ </File>
+ <File>
+ <FileName>index.html</FileName>
+ <FileType>5</FileType>
+ <FilePath>..\..\DoxyGen\RTOS\html\index.html</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+
+</Project>
diff --git a/CMSIS/RTOS/Template/my_objects.h b/CMSIS/RTOS/Template/my_objects.h
new file mode 100644
index 0000000..d99810c
--- /dev/null
+++ b/CMSIS/RTOS/Template/my_objects.h
@@ -0,0 +1,15 @@
+#include "cmsis_os.h" // CMSIS RTOS header file
+
+extern void thread_sample (void const *argument); // prototype
+
+typedef struct a {
+ char y[100];
+} a_element;
+
+osThreadDef (thread_sample, osPriorityBelowNormal, 2, 100);
+
+osPoolDef(MyPool, 10, struct a);
+osMessageQDef(MyMessage, 10, a_element *);
+osMailQDef(MyMail, 10, a_element);
+
+
diff --git a/CMSIS/RTOS/Template/os_sample.c b/CMSIS/RTOS/Template/os_sample.c
new file mode 100644
index 0000000..a6d0767
--- /dev/null
+++ b/CMSIS/RTOS/Template/os_sample.c
@@ -0,0 +1,74 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 30. November 2011
+ * $Revision: V0.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: os_sample.c
+ *
+ * Description: This file shows the usage of the CMSIS-RTOS API.
+ *
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * -------------------------------------------------------------------- */
+
+
+#include "my_objects.h" // Define CMSIS OS Objects
+
+// dummy functions since there is no OS today
+
+/// Add a thread to ActiveThreads and set it to state READY
+osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument) { return osOK; }
+
+/// Terminate execution of a thread and remove it from ActiveThreads
+osStatus osThreadTerminate (osThreadId thread_id) { return osOK; }
+
+/// Change prority of an existing thread
+osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority) { return osOK; }
+
+/// Get current prority of an existing thread
+osPriority osThreadGetPriority (osThreadId thread_id) { return osPriorityNormal; }
+
+osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id) { return NULL; }
+
+osThreadId osThreadGetId (void) { return 0; }
+
+
+osStatus status;
+osThreadId thread_sample1;
+osThreadId thread_sample2;
+
+osMessageQDef(TcpMessageQ0, 10, a_element *);
+osMessageQDef(TcpMessageQ1, 10, a_element *);
+osMessageQDef(TcpMessageQ2, 10, a_element *);
+osMessageQDef(TcpMessageQ3, 10, a_element *);
+
+const osMessageQDef_t *TcpMessageQDef[4]
+#if 1
+ = {
+ osMessageQ(TcpMessageQ0),
+ osMessageQ(TcpMessageQ1),
+ osMessageQ(TcpMessageQ2),
+ osMessageQ(TcpMessageQ3),
+}
+#endif
+;
+
+osMessageQId TcpMessageQ[4];
+
+void CreateMessageQueues (void) {
+ uint32_t i;
+
+ for (i = 0; i < 4; i++) {
+ TcpMessageQ[i] = osMessageCreate (TcpMessageQDef[i], NULL);
+ }
+}
+
+
+int main (void) {
+ thread_sample1 = osThreadCreate (osThread (thread_sample), NULL);
+ thread_sample2 = osThreadCreate (osThread (thread_sample), NULL);
+}
+
diff --git a/CMSIS/RTOS/Template/os_sample1.c b/CMSIS/RTOS/Template/os_sample1.c
new file mode 100644
index 0000000..c78912c
--- /dev/null
+++ b/CMSIS/RTOS/Template/os_sample1.c
@@ -0,0 +1,34 @@
+/* ----------------------------------------------------------------------
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * $Date: 30. November 2011
+ * $Revision: V0.02
+ *
+ * Project: CMSIS-RTOS API
+ * Title: os_sample1.c
+ *
+ * Description: This file shows the usage of the CMSIS-RTOS API.
+ *
+ * Version 0.02
+ * Initial Proposal Phase
+ * -------------------------------------------------------------------- */
+
+
+#define osObjectsExternal
+#include "my_objects.h" // Reference CMSIS OS Objects
+
+
+void thread_sample (void const *argument) {
+ osThreadId my_thread;
+ osPriority my_priority;
+ int i = 1000;
+
+ my_thread = osThreadGetId();
+ my_priority = osThreadGetPriority (my_thread); // Get priority of own thread
+ while (i > 0) {
+ osThreadSetPriority (my_thread, osPriorityAboveNormal);
+ i--;
+ }
+ osThreadSetPriority (my_thread, my_priority);
+ osThreadTerminate (my_thread); // terminate own thread
+}
diff --git a/CMSIS/RTOS/Template/startup_LPC177x_8x.s b/CMSIS/RTOS/Template/startup_LPC177x_8x.s
new file mode 100644
index 0000000..536adce
--- /dev/null
+++ b/CMSIS/RTOS/Template/startup_LPC177x_8x.s
@@ -0,0 +1,301 @@
+;/*****************************************************************************
+; * @file: startup_LPC177x_8x.s
+; * @purpose: CMSIS Cortex-M3 Core Device Startup File
+; * for the NXP LPC177x_8x Device Series
+; * @version: V1.20
+; * @date: 07. October 2010
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; * Copyright (C) 2010 ARM Limited. All rights reserved.
+; * ARM Limited (ARM) is supplying this software for use with Cortex-M3
+; * processor based microcontrollers. This file can be freely distributed
+; * within development tools that are supporting such ARM based processors.
+; *
+; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000200
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WDT_IRQHandler ; 16: Watchdog Timer
+ DCD TIMER0_IRQHandler ; 17: Timer0
+ DCD TIMER1_IRQHandler ; 18: Timer1
+ DCD TIMER2_IRQHandler ; 19: Timer2
+ DCD TIMER3_IRQHandler ; 20: Timer3
+ DCD UART0_IRQHandler ; 21: UART0
+ DCD UART1_IRQHandler ; 22: UART1
+ DCD UART2_IRQHandler ; 23: UART2
+ DCD UART3_IRQHandler ; 24: UART3
+ DCD PWM1_IRQHandler ; 25: PWM1
+ DCD I2C0_IRQHandler ; 26: I2C0
+ DCD I2C1_IRQHandler ; 27: I2C1
+ DCD I2C2_IRQHandler ; 28: I2C2
+ DCD SPIFI_IRQHandler ; 29: SPIFI
+ DCD SSP0_IRQHandler ; 30: SSP0
+ DCD SSP1_IRQHandler ; 31: SSP1
+ DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
+ DCD RTC_IRQHandler ; 33: Real Time Clock
+ DCD EINT0_IRQHandler ; 34: External Interrupt 0
+ DCD EINT1_IRQHandler ; 35: External Interrupt 1
+ DCD EINT2_IRQHandler ; 36: External Interrupt 2
+ DCD EINT3_IRQHandler ; 37: External Interrupt 3
+ DCD ADC_IRQHandler ; 38: A/D Converter
+ DCD BOD_IRQHandler ; 39: Brown-Out Detect
+ DCD USB_IRQHandler ; 40: USB
+ DCD CAN_IRQHandler ; 41: CAN
+ DCD DMA_IRQHandler ; 42: General Purpose DMA
+ DCD I2S_IRQHandler ; 43: I2S
+ DCD ENET_IRQHandler ; 44: Ethernet
+ DCD MCI_IRQHandler ; 45: SD/MMC card I/F
+ DCD MCPWM_IRQHandler ; 46: Motor Control PWM
+ DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
+ DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
+ DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
+ DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup
+ DCD UART4_IRQHandler ; 51: UART4
+ DCD SSP2_IRQHandler ; 52: SSP2
+ DCD LCD_IRQHandler ; 53: LCD
+ DCD GPIO_IRQHandler ; 54: GPIO
+ DCD PWM0_IRQHandler ; 55: PWM0
+ DCD EEPROM_IRQHandler ; 56: EEPROM
+
+
+ IF :LNOT::DEF:NO_CRP
+ AREA |.ARM.__at_0x02FC|, CODE, READONLY
+CRP_Key DCD 0xFFFFFFFF
+ ENDIF
+
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT PWM1_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT PLL0_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT EINT0_IRQHandler [WEAK]
+ EXPORT EINT1_IRQHandler [WEAK]
+ EXPORT EINT2_IRQHandler [WEAK]
+ EXPORT EINT3_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT BOD_IRQHandler [WEAK]
+ EXPORT USB_IRQHandler [WEAK]
+ EXPORT CAN_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT I2S_IRQHandler [WEAK]
+ EXPORT ENET_IRQHandler [WEAK]
+ EXPORT MCI_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+ EXPORT PLL1_IRQHandler [WEAK]
+ EXPORT USBActivity_IRQHandler [WEAK]
+ EXPORT CANActivity_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT SSP2_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT GPIO_IRQHandler [WEAK]
+ EXPORT PWM0_IRQHandler [WEAK]
+ EXPORT EEPROM_IRQHandler [WEAK]
+
+WDT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+PWM1_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPIFI_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+PLL0_IRQHandler
+RTC_IRQHandler
+EINT0_IRQHandler
+EINT1_IRQHandler
+EINT2_IRQHandler
+EINT3_IRQHandler
+ADC_IRQHandler
+BOD_IRQHandler
+USB_IRQHandler
+CAN_IRQHandler
+DMA_IRQHandler
+I2S_IRQHandler
+ENET_IRQHandler
+MCI_IRQHandler
+MCPWM_IRQHandler
+QEI_IRQHandler
+PLL1_IRQHandler
+USBActivity_IRQHandler
+CANActivity_IRQHandler
+UART4_IRQHandler
+SSP2_IRQHandler
+LCD_IRQHandler
+GPIO_IRQHandler
+PWM0_IRQHandler
+EEPROM_IRQHandler
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/CMSIS/RTOS/Template/system_LPC177x_8x.c b/CMSIS/RTOS/Template/system_LPC177x_8x.c
new file mode 100644
index 0000000..ca9e2ff
--- /dev/null
+++ b/CMSIS/RTOS/Template/system_LPC177x_8x.c
@@ -0,0 +1,455 @@
+/***********************************************************************//**
+ * @file system_LPC177x_8x.c
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
+ * for the NXP LPC177x_8x Device Series
+ * @version V1.11
+ * @date 10. November. 2010
+ * @author NXP MCU SW Application Team
+ **************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+ **********************************************************************/
+
+
+#include <stdint.h>
+#include "LPC177x_8x.h"
+#include "system_LPC177x_8x.h"
+
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+/*--------------------- Clock Configuration ----------------------------------
+//
+// <e> Clock Configuration
+// <h> System Controls and Status Register (SCS)
+// <o1.0> EMC_SHIFT: EMC Shift enable
+// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
+// <1=> Static CS addresses start at LSB 0 regardless of memory width
+// <o1.1> EMC_RESET: EMC Reset disable
+// <0=> EMC will be reset by any chip reset
+// <1=> Portions of EMC will only be reset by POR or BOR
+// <o1.2> EMC_BURST: EMC Burst disable
+// <o1.3> MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
+// <0=> SD_PWR is active low
+// <1=> SD_PWR is active high
+// <o1.4> OSCRANGE: Main Oscillator Range Select
+// <0=> 1 MHz to 20 MHz
+// <1=> 15 MHz to 25 MHz
+// <o1.5> OSCEN: Main Oscillator enable
+// </h>
+//
+// <h> Clock Source Select Register (CLKSRCSEL)
+// <o2.0> CLKSRC: sysclk and PLL0 clock source selection
+// <0=> Internal RC oscillator
+// <1=> Main oscillator
+// </h>
+//
+// <e3> PLL0 Configuration (Main PLL)
+// <h> PLL0 Configuration Register (PLL0CFG)
+// <i> PLL out clock = (F_cco / (2 * P))
+// <i> F_cco = (F_in * M * 2 * P)
+// <i> F_in must be in the range of 1 MHz to 25 MHz
+// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+// <o4.0..4> MSEL: PLL Multiplier Selection
+// <i> M Value
+// <1-32><#-1>
+// <o4.5..6> PSEL: PLL Divider Selection
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </h>
+// </e>
+//
+// <e5> PLL1 Configuration (Alt PLL)
+// <h> PLL1 Configuration Register (PLL1CFG)
+// <i> PLL out clock = (F_cco / (2 * P))
+// <i> F_cco = (F_in * M * 2 * P)
+// <i> F_in must be in the range of 1 MHz to 25 MHz
+// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
+// <o6.0..4> MSEL: PLL Multiplier Selection
+// <i> M Value
+// <1-32><#-1>
+// <o6.5..6> PSEL: PLL Divider Selection
+// <i> P Value
+// <0=> 1
+// <1=> 2
+// <2=> 4
+// <3=> 8
+// </h>
+// </e>
+//
+// <h> CPU Clock Selection Register (CCLKSEL)
+// <o7.0..4> CCLKDIV: CPU clock (CCLK) divider
+// <i> 0: The divider is turned off. No clock will be provided to the CPU
+// <i> n: The input clock is divided by n to produce the CPU clock
+// <0-31>
+// <o7.8> CCLKSEL: CPU clock divider input clock selection
+// <0=> sysclk clock
+// <1=> PLL0 clock
+// </h>
+//
+// <h> USB Clock Selection Register (USBCLKSEL)
+// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
+// <0=> USB clock off
+// <4=> PLL0 / 4 (PLL0 must be 192Mhz)
+// <6=> PLL0 / 6 (PLL0 must be 288Mhz)
+// <o8.8..9> USBSEL: USB clock divider input clock selection
+// <i> When CPU clock is selected, the USB can be accessed
+// <i> by software but cannot perform USB functions
+// <0=> CPU clock
+// <1=> PLL0 clock
+// <2=> PLL1 clock
+// </h>
+//
+// <h> EMC Clock Selection Register (EMCCLKSEL)
+// <o9.0> EMCDIV: EMC clock selection
+// <0=> CPU clock
+// <1=> CPU clock / 2
+// </h>
+//
+// <h> Peripheral Clock Selection Register (PCLKSEL)
+// <o10.0..4> PCLKDIV: APB Peripheral clock divider
+// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
+// <i> n: The input clock is divided by n to produce the APB peripheral clock
+// <0-31>
+// </h>
+//
+// <h> Power Control for Peripherals Register (PCONP)
+// <o11.0> PCLCD: LCD controller power/clock enable
+// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
+// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
+// <o11.3> PCUART0: UART 0 power/clock enable
+// <o11.4> PCUART1: UART 1 power/clock enable
+// <o11.5> PCPWM0: PWM0 power/clock enable
+// <o11.6> PCPWM1: PWM1 power/clock enable
+// <o11.7> PCI2C0: I2C 0 interface power/clock enable
+// <o11.8> PCUART4: UART 4 power/clock enable
+// <o11.9> PCRTC: RTC and Event Recorder power/clock enable
+// <o11.10> PCSSP1: SSP 1 interface power/clock enable
+// <o11.11> PCEMC: External Memory Controller power/clock enable
+// <o11.12> PCADC: A/D converter power/clock enable
+// <o11.13> PCCAN1: CAN controller 1 power/clock enable
+// <o11.14> PCCAN2: CAN controller 2 power/clock enable
+// <o11.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
+// <o11.17> PCMCPWM: Motor Control PWM power/clock enable
+// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
+// <o11.19> PCI2C1: I2C 1 interface power/clock enable
+// <o11.20> PCSSP2: SSP 2 interface power/clock enable
+// <o11.21> PCSSP0: SSP 0 interface power/clock enable
+// <o11.22> PCTIM2: Timer 2 power/clock enable
+// <o11.23> PCTIM3: Timer 3 power/clock enable
+// <o11.24> PCUART2: UART 2 power/clock enable
+// <o11.25> PCUART3: UART 3 power/clock enable
+// <o11.26> PCI2C2: I2C 2 interface power/clock enable
+// <o11.27> PCI2S: I2S interface power/clock enable
+// <o11.28> PCSDC: SD Card interface power/clock enable
+// <o11.29> PCGPDMA: GPDMA function power/clock enable
+// <o11.30> PCENET: Ethernet block power/clock enable
+// <o11.31> PCUSB: USB interface power/clock enable
+// </h>
+//
+// <h> Clock Output Configuration Register (CLKOUTCFG)
+// <o12.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
+// <0=> CPU clock
+// <1=> Main Oscillator
+// <2=> Internal RC Oscillator
+// <3=> USB clock
+// <4=> RTC Oscillator
+// <5=> unused
+// <6=> Watchdog Oscillator
+// <o12.4..7> CLKOUTDIV: Output Clock Divider
+// <1-16><#-1>
+// <o12.8> CLKOUT_EN: CLKOUT enable
+// </h>
+//
+// </e>
+*/
+#define CLOCK_SETUP 1
+#define SCS_Val 0x00000021
+#define CLKSRCSEL_Val 0x00000001
+#define PLL0_SETUP 1
+#define PLL0CFG_Val 0x00000009
+#define PLL1_SETUP 1
+#define PLL1CFG_Val 0x00000023
+#define CCLKSEL_Val (0x00000001|(1<<8))
+#define USBCLK_SETUP 1
+#define USBCLKSEL_Val (0x00000001|(0x02<<8))
+#define EMCCLKSEL_Val 0x00000001
+#define PCLKSEL_Val 0x00000002
+#define PCONP_Val 0x042887DE
+#define CLKOUTCFG_Val 0x00000100
+
+
+/*--------------------- Flash Accelerator Configuration ----------------------
+//
+// <e> Flash Accelerator Configuration
+// <o1.12..15> FLASHTIM: Flash Access Time
+// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
+// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
+// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
+// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
+// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
+// <5=> 6 CPU clocks (for any CPU clock)
+// </e>
+*/
+#define FLASH_SETUP 1
+#define FLASHCFG_Val 0x00005000
+
+/*----------------------------------------------------------------------------
+ Check the register settings
+ *----------------------------------------------------------------------------*/
+#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
+#define CHECK_RSVD(val, mask) (val & mask)
+
+/* Clock Configuration -------------------------------------------------------*/
+#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
+ #error "SCS: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
+ #error "CLKSRCSEL: Value out of range!"
+#endif
+
+#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
+ #error "PLL0CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
+ #error "PLL1CFG: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
+ #error "CCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
+ #error "USBCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
+ #error "EMCCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
+ #error "PCLKSEL: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
+ #error "PCONP: Invalid values of reserved bits!"
+#endif
+
+#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
+ #error "CLKOUTCFG: Invalid values of reserved bits!"
+#endif
+
+/* Flash Accelerator Configuration -------------------------------------------*/
+#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
+ #warning "FLASHCFG: Invalid values of reserved bits!"
+#endif
+
+
+/*----------------------------------------------------------------------------
+ DEFINES
+ *----------------------------------------------------------------------------*/
+/* pll_out_clk = F_cco / (2 × P)
+ F_cco = pll_in_clk × M × 2 × P */
+#define __M ((PLL0CFG_Val & 0x1F) + 1)
+#define __PLL0_CLK(__F_IN) (__F_IN * __M)
+#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
+#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
+#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
+
+/* Determine core clock frequency according to settings */
+#if (CLOCK_SETUP) /* Clock Setup */
+
+ #if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
+ #error "Main Oscillator is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
+ #error "Main PLL is selected as clock source but is not enabled!"
+ #endif
+
+ #if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
+ #define __PER_CLK (IRC_OSC/ __PCLK_DIV)
+ #define __EMC_CLK (IRC_OSC/ __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
+ #define __PER_CLK (OSC_CLK/ __PCLK_DIV)
+ #define __EMC_CLK (OSC_CLK/ __ECLK_DIV)
+ #endif
+ #else /* cclk = pll_clk */
+ #if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
+ #define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
+ #define __EMC_CLK (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
+ #else /* sysclk = osc_clk */
+ #define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
+ #define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
+ #define __EMC_CLK (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
+ #endif
+ #endif
+
+#else
+ #define __CORE_CLK (IRC_OSC)
+ #define __PER_CLK (IRC_OSC)
+ #define __EMC_CLK (IRC_OSC)
+#endif
+
+/*----------------------------------------------------------------------------
+ Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
+uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
+uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
+uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
+ be updated after call SystemCoreClockUpdate, should be 48MHz*/
+
+
+/*----------------------------------------------------------------------------
+ Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
+{
+ /* Determine clock frequency according to clock register values */
+ if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ else { /* cclk = pll_clk */
+ if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
+ SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ else { /* sysclk = osc_clk */
+ if ((LPC_SC->SCS & 0x40) == 0) {
+ SystemCoreClock = 0; /* this should never happen! */
+ PeripheralClock = 0;
+ EMCClock = 0;
+ }
+ else {
+ SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
+ PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
+ EMCClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
+ }
+ }
+ }
+ }
+ /* ---update USBClock------------------*/
+ if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
+ {
+ switch (LPC_SC->USBCLKSEL & 0x1F)
+ {
+ case 0:
+ USBClock = 0; //no clock will be provided to the USB subsystem
+ break;
+ case 4:
+ case 6:
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+ else //pll_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
+ break;
+ default:
+ USBClock = 0; /* this should never happen! */
+ }
+ }
+ else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
+ {
+ if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
+ USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
+ else //pll1_clk_in = irc_clk
+ USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
+ }
+ else
+ USBClock = 0; /* this should never happen! */
+}
+
+ /* Determine clock frequency according to clock register values */
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System.
+ */
+void SystemInit (void)
+{
+#if (CLOCK_SETUP) /* Clock Setup */
+ LPC_SC->SCS = SCS_Val;
+ if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
+ while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
+ }
+
+ LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
+
+#if (PLL0_SETUP)
+ LPC_SC->PLL0CFG = PLL0CFG_Val;
+ LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
+ LPC_SC->PLL0FEED = 0xAA;
+ LPC_SC->PLL0FEED = 0x55;
+ while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
+#endif
+
+#if (PLL1_SETUP)
+ LPC_SC->PLL1CFG = PLL1CFG_Val;
+ LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
+ LPC_SC->PLL1FEED = 0xAA;
+ LPC_SC->PLL1FEED = 0x55;
+ while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
+#endif
+
+ LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
+ LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
+ LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
+ LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
+ LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
+ LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
+#endif
+
+#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
+ LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
+#endif
+#ifdef __RAM_MODE__
+ SCB->VTOR = 0x10000000 & 0x3FFFFF80;
+#else
+ SCB->VTOR = 0x00000000 & 0x3FFFFF80;
+#endif
+}