Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | // |
| 3 | // Copyright (c) 2018 BayLibre, SAS. |
| 4 | // Author: Jerome Brunet <jbrunet@baylibre.com> |
| 5 | |
| 6 | /* This driver implements the frontend playback DAI of AXG based SoCs */ |
| 7 | |
| 8 | #include <linux/clk.h> |
| 9 | #include <linux/regmap.h> |
| 10 | #include <linux/module.h> |
| 11 | #include <linux/of_platform.h> |
| 12 | #include <sound/soc.h> |
| 13 | #include <sound/soc-dai.h> |
| 14 | |
| 15 | #include "axg-fifo.h" |
| 16 | |
| 17 | #define CTRL0_FRDDR_PP_MODE BIT(30) |
| 18 | |
| 19 | static int axg_frddr_dai_startup(struct snd_pcm_substream *substream, |
| 20 | struct snd_soc_dai *dai) |
| 21 | { |
| 22 | struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); |
| 23 | unsigned int fifo_depth, fifo_threshold; |
| 24 | int ret; |
| 25 | |
| 26 | /* Enable pclk to access registers and clock the fifo ip */ |
| 27 | ret = clk_prepare_enable(fifo->pclk); |
| 28 | if (ret) |
| 29 | return ret; |
| 30 | |
| 31 | /* Apply single buffer mode to the interface */ |
| 32 | regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_FRDDR_PP_MODE, 0); |
| 33 | |
| 34 | /* |
| 35 | * TODO: We could adapt the fifo depth and the fifo threshold |
| 36 | * depending on the expected memory throughput and lantencies |
| 37 | * For now, we'll just use the same values as the vendor kernel |
| 38 | * Depth and threshold are zero based. |
| 39 | */ |
| 40 | fifo_depth = AXG_FIFO_MIN_CNT - 1; |
| 41 | fifo_threshold = (AXG_FIFO_MIN_CNT / 2) - 1; |
| 42 | regmap_update_bits(fifo->map, FIFO_CTRL1, |
| 43 | CTRL1_FRDDR_DEPTH_MASK | CTRL1_THRESHOLD_MASK, |
| 44 | CTRL1_FRDDR_DEPTH(fifo_depth) | |
| 45 | CTRL1_THRESHOLD(fifo_threshold)); |
| 46 | |
| 47 | return 0; |
| 48 | } |
| 49 | |
| 50 | static void axg_frddr_dai_shutdown(struct snd_pcm_substream *substream, |
| 51 | struct snd_soc_dai *dai) |
| 52 | { |
| 53 | struct axg_fifo *fifo = snd_soc_dai_get_drvdata(dai); |
| 54 | |
| 55 | clk_disable_unprepare(fifo->pclk); |
| 56 | } |
| 57 | |
| 58 | static int axg_frddr_pcm_new(struct snd_soc_pcm_runtime *rtd, |
| 59 | struct snd_soc_dai *dai) |
| 60 | { |
| 61 | return axg_fifo_pcm_new(rtd, SNDRV_PCM_STREAM_PLAYBACK); |
| 62 | } |
| 63 | |
| 64 | static const struct snd_soc_dai_ops axg_frddr_ops = { |
| 65 | .startup = axg_frddr_dai_startup, |
| 66 | .shutdown = axg_frddr_dai_shutdown, |
| 67 | }; |
| 68 | |
| 69 | static struct snd_soc_dai_driver axg_frddr_dai_drv = { |
| 70 | .name = "FRDDR", |
| 71 | .playback = { |
| 72 | .stream_name = "Playback", |
| 73 | .channels_min = 1, |
| 74 | .channels_max = AXG_FIFO_CH_MAX, |
| 75 | .rates = AXG_FIFO_RATES, |
| 76 | .formats = AXG_FIFO_FORMATS, |
| 77 | }, |
| 78 | .ops = &axg_frddr_ops, |
| 79 | .pcm_new = axg_frddr_pcm_new, |
| 80 | }; |
| 81 | |
| 82 | static const char * const axg_frddr_sel_texts[] = { |
| 83 | "OUT 0", "OUT 1", "OUT 2", "OUT 3" |
| 84 | }; |
| 85 | |
| 86 | static SOC_ENUM_SINGLE_DECL(axg_frddr_sel_enum, FIFO_CTRL0, CTRL0_SEL_SHIFT, |
| 87 | axg_frddr_sel_texts); |
| 88 | |
| 89 | static const struct snd_kcontrol_new axg_frddr_out_demux = |
| 90 | SOC_DAPM_ENUM("Output Sink", axg_frddr_sel_enum); |
| 91 | |
| 92 | static const struct snd_soc_dapm_widget axg_frddr_dapm_widgets[] = { |
| 93 | SND_SOC_DAPM_DEMUX("SINK SEL", SND_SOC_NOPM, 0, 0, |
| 94 | &axg_frddr_out_demux), |
| 95 | SND_SOC_DAPM_AIF_OUT("OUT 0", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 96 | SND_SOC_DAPM_AIF_OUT("OUT 1", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 97 | SND_SOC_DAPM_AIF_OUT("OUT 2", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 98 | SND_SOC_DAPM_AIF_OUT("OUT 3", NULL, 0, SND_SOC_NOPM, 0, 0), |
| 99 | }; |
| 100 | |
| 101 | static const struct snd_soc_dapm_route axg_frddr_dapm_routes[] = { |
| 102 | { "SINK SEL", NULL, "Playback" }, |
| 103 | { "OUT 0", "OUT 0", "SINK SEL" }, |
| 104 | { "OUT 1", "OUT 1", "SINK SEL" }, |
| 105 | { "OUT 2", "OUT 2", "SINK SEL" }, |
| 106 | { "OUT 3", "OUT 3", "SINK SEL" }, |
| 107 | }; |
| 108 | |
| 109 | static const struct snd_soc_component_driver axg_frddr_component_drv = { |
| 110 | .dapm_widgets = axg_frddr_dapm_widgets, |
| 111 | .num_dapm_widgets = ARRAY_SIZE(axg_frddr_dapm_widgets), |
| 112 | .dapm_routes = axg_frddr_dapm_routes, |
| 113 | .num_dapm_routes = ARRAY_SIZE(axg_frddr_dapm_routes), |
| 114 | .ops = &axg_fifo_pcm_ops |
| 115 | }; |
| 116 | |
| 117 | static const struct axg_fifo_match_data axg_frddr_match_data = { |
| 118 | .component_drv = &axg_frddr_component_drv, |
| 119 | .dai_drv = &axg_frddr_dai_drv |
| 120 | }; |
| 121 | |
| 122 | static const struct of_device_id axg_frddr_of_match[] = { |
| 123 | { |
| 124 | .compatible = "amlogic,axg-frddr", |
| 125 | .data = &axg_frddr_match_data, |
| 126 | }, {} |
| 127 | }; |
| 128 | MODULE_DEVICE_TABLE(of, axg_frddr_of_match); |
| 129 | |
| 130 | static struct platform_driver axg_frddr_pdrv = { |
| 131 | .probe = axg_fifo_probe, |
| 132 | .driver = { |
| 133 | .name = "axg-frddr", |
| 134 | .of_match_table = axg_frddr_of_match, |
| 135 | }, |
| 136 | }; |
| 137 | module_platform_driver(axg_frddr_pdrv); |
| 138 | |
| 139 | MODULE_DESCRIPTION("Amlogic AXG playback fifo driver"); |
| 140 | MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); |
| 141 | MODULE_LICENSE("GPL v2"); |