| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * |
| 3 | * Intel Management Engine Interface (Intel MEI) Linux driver |
| 4 | * Copyright (c) 2003-2012, Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | |
| 18 | |
| 19 | #ifndef _MEI_INTERFACE_H_ |
| 20 | #define _MEI_INTERFACE_H_ |
| 21 | |
| 22 | #include <linux/irqreturn.h> |
| 23 | #include <linux/pci.h> |
| 24 | #include <linux/mei.h> |
| 25 | |
| 26 | #include "mei_dev.h" |
| 27 | #include "client.h" |
| 28 | |
| 29 | /* |
| 30 | * mei_cfg - mei device configuration |
| 31 | * |
| 32 | * @fw_status: FW status |
| 33 | * @quirk_probe: device exclusion quirk |
| 34 | * @dma_size: device DMA buffers size |
| 35 | */ |
| 36 | struct mei_cfg { |
| 37 | const struct mei_fw_status fw_status; |
| 38 | bool (*quirk_probe)(struct pci_dev *pdev); |
| 39 | size_t dma_size[DMA_DSCR_NUM]; |
| 40 | }; |
| 41 | |
| 42 | |
| 43 | #define MEI_PCI_DEVICE(dev, cfg) \ |
| 44 | .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \ |
| 45 | .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ |
| 46 | .driver_data = (kernel_ulong_t)(cfg), |
| 47 | |
| 48 | #define MEI_ME_RPM_TIMEOUT 500 /* ms */ |
| 49 | |
| 50 | /** |
| 51 | * struct mei_me_hw - me hw specific data |
| 52 | * |
| 53 | * @cfg: per device generation config and ops |
| 54 | * @mem_addr: io memory address |
| 55 | * @pg_state: power gating state |
| 56 | * @d0i3_supported: di03 support |
| 57 | * @hbuf_depth: depth of hardware host/write buffer in slots |
| 58 | */ |
| 59 | struct mei_me_hw { |
| 60 | const struct mei_cfg *cfg; |
| 61 | void __iomem *mem_addr; |
| 62 | enum mei_pg_state pg_state; |
| 63 | bool d0i3_supported; |
| 64 | u8 hbuf_depth; |
| 65 | }; |
| 66 | |
| 67 | #define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw) |
| 68 | |
| 69 | /** |
| 70 | * enum mei_cfg_idx - indices to platform specific configurations. |
| 71 | * |
| 72 | * Note: has to be synchronized with mei_cfg_list[] |
| 73 | * |
| 74 | * @MEI_ME_UNDEF_CFG: Lower sentinel. |
| 75 | * @MEI_ME_ICH_CFG: I/O Controller Hub legacy devices. |
| 76 | * @MEI_ME_ICH10_CFG: I/O Controller Hub platforms Gen10 |
| 77 | * @MEI_ME_PCH_CFG: Platform Controller Hub platforms (Up to Gen8). |
| 78 | * @MEI_ME_PCH_CPT_PBG_CFG:Platform Controller Hub workstations |
| 79 | * with quirk for Node Manager exclusion. |
| 80 | * @MEI_ME_PCH8_CFG: Platform Controller Hub Gen8 and newer |
| 81 | * client platforms. |
| 82 | * @MEI_ME_PCH8_SPS_CFG: Platform Controller Hub Gen8 and newer |
| 83 | * servers platforms with quirk for |
| 84 | * SPS firmware exclusion. |
| 85 | * @MEI_ME_PCH12_CFG: Platform Controller Hub Gen12 and newer |
| 86 | * @MEI_ME_NUM_CFG: Upper Sentinel. |
| 87 | */ |
| 88 | enum mei_cfg_idx { |
| 89 | MEI_ME_UNDEF_CFG, |
| 90 | MEI_ME_ICH_CFG, |
| 91 | MEI_ME_ICH10_CFG, |
| 92 | MEI_ME_PCH_CFG, |
| 93 | MEI_ME_PCH_CPT_PBG_CFG, |
| 94 | MEI_ME_PCH8_CFG, |
| 95 | MEI_ME_PCH8_SPS_CFG, |
| 96 | MEI_ME_PCH12_CFG, |
| 97 | MEI_ME_NUM_CFG, |
| 98 | }; |
| 99 | |
| 100 | const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx); |
| 101 | |
| 102 | struct mei_device *mei_me_dev_init(struct pci_dev *pdev, |
| 103 | const struct mei_cfg *cfg); |
| 104 | |
| 105 | int mei_me_pg_enter_sync(struct mei_device *dev); |
| 106 | int mei_me_pg_exit_sync(struct mei_device *dev); |
| 107 | |
| 108 | irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id); |
| 109 | irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id); |
| 110 | |
| 111 | #endif /* _MEI_INTERFACE_H_ */ |