| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #ifndef __ASM_SH_PCI_H |
| 3 | #define __ASM_SH_PCI_H |
| 4 | |
| 5 | #ifdef __KERNEL__ |
| 6 | |
| 7 | /* Can be used to override the logic in pci_scan_bus for skipping |
| 8 | already-configured bus numbers - to be used for buggy BIOSes |
| 9 | or architectures with incomplete PCI setup by the loader */ |
| 10 | |
| 11 | #define pcibios_assign_all_busses() 1 |
| 12 | |
| 13 | /* |
| 14 | * A board can define one or more PCI channels that represent built-in (or |
| 15 | * external) PCI controllers. |
| 16 | */ |
| 17 | struct pci_channel { |
| 18 | struct pci_channel *next; |
| 19 | struct pci_bus *bus; |
| 20 | |
| 21 | struct pci_ops *pci_ops; |
| 22 | |
| 23 | struct resource *resources; |
| 24 | unsigned int nr_resources; |
| 25 | |
| 26 | unsigned long io_offset; |
| 27 | unsigned long mem_offset; |
| 28 | |
| 29 | unsigned long reg_base; |
| 30 | unsigned long io_map_base; |
| 31 | |
| 32 | unsigned int index; |
| 33 | unsigned int need_domain_info; |
| 34 | |
| 35 | /* Optional error handling */ |
| 36 | struct timer_list err_timer, serr_timer; |
| 37 | unsigned int err_irq, serr_irq; |
| 38 | }; |
| 39 | |
| 40 | /* arch/sh/drivers/pci/pci.c */ |
| 41 | extern raw_spinlock_t pci_config_lock; |
| 42 | |
| 43 | extern int register_pci_controller(struct pci_channel *hose); |
| 44 | extern void pcibios_report_status(unsigned int status_mask, int warn); |
| 45 | |
| 46 | /* arch/sh/drivers/pci/common.c */ |
| 47 | extern int early_read_config_byte(struct pci_channel *hose, int top_bus, |
| 48 | int bus, int devfn, int offset, u8 *value); |
| 49 | extern int early_read_config_word(struct pci_channel *hose, int top_bus, |
| 50 | int bus, int devfn, int offset, u16 *value); |
| 51 | extern int early_read_config_dword(struct pci_channel *hose, int top_bus, |
| 52 | int bus, int devfn, int offset, u32 *value); |
| 53 | extern int early_write_config_byte(struct pci_channel *hose, int top_bus, |
| 54 | int bus, int devfn, int offset, u8 value); |
| 55 | extern int early_write_config_word(struct pci_channel *hose, int top_bus, |
| 56 | int bus, int devfn, int offset, u16 value); |
| 57 | extern int early_write_config_dword(struct pci_channel *hose, int top_bus, |
| 58 | int bus, int devfn, int offset, u32 value); |
| 59 | extern void pcibios_enable_timers(struct pci_channel *hose); |
| 60 | extern unsigned int pcibios_handle_status_errors(unsigned long addr, |
| 61 | unsigned int status, struct pci_channel *hose); |
| 62 | extern int pci_is_66mhz_capable(struct pci_channel *hose, |
| 63 | int top_bus, int current_bus); |
| 64 | |
| 65 | extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM; |
| 66 | |
| 67 | #define HAVE_PCI_MMAP |
| 68 | #define ARCH_GENERIC_PCI_MMAP_RESOURCE |
| 69 | |
| 70 | /* Dynamic DMA mapping stuff. |
| 71 | * SuperH has everything mapped statically like x86. |
| 72 | */ |
| 73 | |
| 74 | #ifdef CONFIG_PCI |
| 75 | /* |
| 76 | * None of the SH PCI controllers support MWI, it is always treated as a |
| 77 | * direct memory write. |
| 78 | */ |
| 79 | #define PCI_DISABLE_MWI |
| 80 | #endif |
| 81 | |
| 82 | /* Board-specific fixup routines. */ |
| 83 | int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin); |
| 84 | |
| 85 | #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index |
| 86 | |
| 87 | static inline int pci_proc_domain(struct pci_bus *bus) |
| 88 | { |
| 89 | struct pci_channel *hose = bus->sysdata; |
| 90 | return hose->need_domain_info; |
| 91 | } |
| 92 | |
| 93 | /* Chances are this interrupt is wired PC-style ... */ |
| 94 | static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel) |
| 95 | { |
| 96 | return channel ? 15 : 14; |
| 97 | } |
| 98 | |
| 99 | #endif /* __KERNEL__ */ |
| 100 | #endif /* __ASM_SH_PCI_H */ |
| 101 | |