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review.trustedfirmware.org / hafnium / third_party / linux / b4b6d4a02fa8aa8187d426b508fb7f3b69df0dcc / . / arch / arm64 / net / bpf_jit.h
blob: 783de51a6c4e5b33725d4904be6b09011dd48605 [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame^]1/*
2 * BPF JIT compiler for ARM64
3 *
4 * Copyright (C) 2014-2016 Zi Shen Lim <zlim.lnx@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef _BPF_JIT_H
19#define _BPF_JIT_H
20
21#include <asm/insn.h>
22
23/* 5-bit Register Operand */
24#define A64_R(x) AARCH64_INSN_REG_##x
25#define A64_FP AARCH64_INSN_REG_FP
26#define A64_LR AARCH64_INSN_REG_LR
27#define A64_ZR AARCH64_INSN_REG_ZR
28#define A64_SP AARCH64_INSN_REG_SP
29
30#define A64_VARIANT(sf) \
31 ((sf) ? AARCH64_INSN_VARIANT_64BIT : AARCH64_INSN_VARIANT_32BIT)
32
33/* Compare & branch (immediate) */
34#define A64_COMP_BRANCH(sf, Rt, offset, type) \
35 aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
36 AARCH64_INSN_BRANCH_COMP_##type)
37#define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)
38#define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO)
39
40/* Conditional branch (immediate) */
41#define A64_COND_BRANCH(cond, offset) \
42 aarch64_insn_gen_cond_branch_imm(0, offset, cond)
43#define A64_COND_EQ AARCH64_INSN_COND_EQ /* == */
44#define A64_COND_NE AARCH64_INSN_COND_NE /* != */
45#define A64_COND_CS AARCH64_INSN_COND_CS /* unsigned >= */
46#define A64_COND_HI AARCH64_INSN_COND_HI /* unsigned > */
47#define A64_COND_LS AARCH64_INSN_COND_LS /* unsigned <= */
48#define A64_COND_CC AARCH64_INSN_COND_CC /* unsigned < */
49#define A64_COND_GE AARCH64_INSN_COND_GE /* signed >= */
50#define A64_COND_GT AARCH64_INSN_COND_GT /* signed > */
51#define A64_COND_LE AARCH64_INSN_COND_LE /* signed <= */
52#define A64_COND_LT AARCH64_INSN_COND_LT /* signed < */
53#define A64_B_(cond, imm19) A64_COND_BRANCH(cond, (imm19) << 2)
54
55/* Unconditional branch (immediate) */
56#define A64_BRANCH(offset, type) aarch64_insn_gen_branch_imm(0, offset, \
57 AARCH64_INSN_BRANCH_##type)
58#define A64_B(imm26) A64_BRANCH((imm26) << 2, NOLINK)
59#define A64_BL(imm26) A64_BRANCH((imm26) << 2, LINK)
60
61/* Unconditional branch (register) */
62#define A64_BR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_NOLINK)
63#define A64_BLR(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_LINK)
64#define A64_RET(Rn) aarch64_insn_gen_branch_reg(Rn, AARCH64_INSN_BRANCH_RETURN)
65
66/* Load/store register (register offset) */
67#define A64_LS_REG(Rt, Rn, Rm, size, type) \
68 aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
69 AARCH64_INSN_SIZE_##size, \
70 AARCH64_INSN_LDST_##type##_REG_OFFSET)
71#define A64_STRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, STORE)
72#define A64_LDRB(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 8, LOAD)
73#define A64_STRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, STORE)
74#define A64_LDRH(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 16, LOAD)
75#define A64_STR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, STORE)
76#define A64_LDR32(Wt, Xn, Xm) A64_LS_REG(Wt, Xn, Xm, 32, LOAD)
77#define A64_STR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, STORE)
78#define A64_LDR64(Xt, Xn, Xm) A64_LS_REG(Xt, Xn, Xm, 64, LOAD)
79
80/* Load/store register pair */
81#define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \
82 aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
83 AARCH64_INSN_VARIANT_64BIT, \
84 AARCH64_INSN_LDST_##ls##_PAIR_##type)
85/* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
86#define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)
87/* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
88#define A64_POP(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)
89
90/* Load/store exclusive */
91#define A64_SIZE(sf) \
92 ((sf) ? AARCH64_INSN_SIZE_64 : AARCH64_INSN_SIZE_32)
93#define A64_LSX(sf, Rt, Rn, Rs, type) \
94 aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
95 AARCH64_INSN_LDST_##type)
96/* Rt = [Rn]; (atomic) */
97#define A64_LDXR(sf, Rt, Rn) \
98 A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
99/* [Rn] = Rt; (atomic) Rs = [state] */
100#define A64_STXR(sf, Rt, Rn, Rs) \
101 A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
102
103/* Prefetch */
104#define A64_PRFM(Rn, type, target, policy) \
105 aarch64_insn_gen_prefetch(Rn, AARCH64_INSN_PRFM_TYPE_##type, \
106 AARCH64_INSN_PRFM_TARGET_##target, \
107 AARCH64_INSN_PRFM_POLICY_##policy)
108
109/* Add/subtract (immediate) */
110#define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \
111 aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
112 A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
113/* Rd = Rn OP imm12 */
114#define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD)
115#define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB)
116/* Rd = Rn */
117#define A64_MOV(sf, Rd, Rn) A64_ADD_I(sf, Rd, Rn, 0)
118
119/* Bitfield move */
120#define A64_BITFIELD(sf, Rd, Rn, immr, imms, type) \
121 aarch64_insn_gen_bitfield(Rd, Rn, immr, imms, \
122 A64_VARIANT(sf), AARCH64_INSN_BITFIELD_MOVE_##type)
123/* Signed, with sign replication to left and zeros to right */
124#define A64_SBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, SIGNED)
125/* Unsigned, with zeros to left and right */
126#define A64_UBFM(sf, Rd, Rn, ir, is) A64_BITFIELD(sf, Rd, Rn, ir, is, UNSIGNED)
127
128/* Rd = Rn << shift */
129#define A64_LSL(sf, Rd, Rn, shift) ({ \
130 int sz = (sf) ? 64 : 32; \
131 A64_UBFM(sf, Rd, Rn, (unsigned)-(shift) % sz, sz - 1 - (shift)); \
132})
133/* Rd = Rn >> shift */
134#define A64_LSR(sf, Rd, Rn, shift) A64_UBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
135/* Rd = Rn >> shift; signed */
136#define A64_ASR(sf, Rd, Rn, shift) A64_SBFM(sf, Rd, Rn, shift, (sf) ? 63 : 31)
137
138/* Zero extend */
139#define A64_UXTH(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 15)
140#define A64_UXTW(sf, Rd, Rn) A64_UBFM(sf, Rd, Rn, 0, 31)
141
142/* Move wide (immediate) */
143#define A64_MOVEW(sf, Rd, imm16, shift, type) \
144 aarch64_insn_gen_movewide(Rd, imm16, shift, \
145 A64_VARIANT(sf), AARCH64_INSN_MOVEWIDE_##type)
146/* Rd = Zeros (for MOVZ);
147 * Rd |= imm16 << shift (where shift is {0, 16, 32, 48});
148 * Rd = ~Rd; (for MOVN); */
149#define A64_MOVN(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, INVERSE)
150#define A64_MOVZ(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, ZERO)
151#define A64_MOVK(sf, Rd, imm16, shift) A64_MOVEW(sf, Rd, imm16, shift, KEEP)
152
153/* Add/subtract (shifted register) */
154#define A64_ADDSUB_SREG(sf, Rd, Rn, Rm, type) \
155 aarch64_insn_gen_add_sub_shifted_reg(Rd, Rn, Rm, 0, \
156 A64_VARIANT(sf), AARCH64_INSN_ADSB_##type)
157/* Rd = Rn OP Rm */
158#define A64_ADD(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, ADD)
159#define A64_SUB(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB)
160#define A64_SUBS(sf, Rd, Rn, Rm) A64_ADDSUB_SREG(sf, Rd, Rn, Rm, SUB_SETFLAGS)
161/* Rd = -Rm */
162#define A64_NEG(sf, Rd, Rm) A64_SUB(sf, Rd, A64_ZR, Rm)
163/* Rn - Rm; set condition flags */
164#define A64_CMP(sf, Rn, Rm) A64_SUBS(sf, A64_ZR, Rn, Rm)
165
166/* Data-processing (1 source) */
167#define A64_DATA1(sf, Rd, Rn, type) aarch64_insn_gen_data1(Rd, Rn, \
168 A64_VARIANT(sf), AARCH64_INSN_DATA1_##type)
169/* Rd = BSWAPx(Rn) */
170#define A64_REV16(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_16)
171#define A64_REV32(sf, Rd, Rn) A64_DATA1(sf, Rd, Rn, REVERSE_32)
172#define A64_REV64(Rd, Rn) A64_DATA1(1, Rd, Rn, REVERSE_64)
173
174/* Data-processing (2 source) */
175/* Rd = Rn OP Rm */
176#define A64_DATA2(sf, Rd, Rn, Rm, type) aarch64_insn_gen_data2(Rd, Rn, Rm, \
177 A64_VARIANT(sf), AARCH64_INSN_DATA2_##type)
178#define A64_UDIV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, UDIV)
179#define A64_LSLV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSLV)
180#define A64_LSRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, LSRV)
181#define A64_ASRV(sf, Rd, Rn, Rm) A64_DATA2(sf, Rd, Rn, Rm, ASRV)
182
183/* Data-processing (3 source) */
184/* Rd = Ra + Rn * Rm */
185#define A64_MADD(sf, Rd, Ra, Rn, Rm) aarch64_insn_gen_data3(Rd, Ra, Rn, Rm, \
186 A64_VARIANT(sf), AARCH64_INSN_DATA3_MADD)
187/* Rd = Rn * Rm */
188#define A64_MUL(sf, Rd, Rn, Rm) A64_MADD(sf, Rd, A64_ZR, Rn, Rm)
189
190/* Logical (shifted register) */
191#define A64_LOGIC_SREG(sf, Rd, Rn, Rm, type) \
192 aarch64_insn_gen_logical_shifted_reg(Rd, Rn, Rm, 0, \
193 A64_VARIANT(sf), AARCH64_INSN_LOGIC_##type)
194/* Rd = Rn OP Rm */
195#define A64_AND(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND)
196#define A64_ORR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, ORR)
197#define A64_EOR(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, EOR)
198#define A64_ANDS(sf, Rd, Rn, Rm) A64_LOGIC_SREG(sf, Rd, Rn, Rm, AND_SETFLAGS)
199/* Rn & Rm; set condition flags */
200#define A64_TST(sf, Rn, Rm) A64_ANDS(sf, A64_ZR, Rn, Rm)
201
202#endif /* _BPF_JIT_H */