| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 1991,1992,1995 Linus Torvalds |
| 4 | * Copyright (c) 1994 Alan Modra |
| 5 | * Copyright (c) 1995 Markus Kuhn |
| 6 | * Copyright (c) 1996 Ingo Molnar |
| 7 | * Copyright (c) 1998 Andrea Arcangeli |
| 8 | * Copyright (c) 2002,2006 Vojtech Pavlik |
| 9 | * Copyright (c) 2003 Andi Kleen |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | #include <linux/clockchips.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/i8253.h> |
| 17 | #include <linux/time.h> |
| 18 | #include <linux/export.h> |
| 19 | |
| 20 | #include <asm/vsyscall.h> |
| 21 | #include <asm/x86_init.h> |
| 22 | #include <asm/i8259.h> |
| 23 | #include <asm/timer.h> |
| 24 | #include <asm/hpet.h> |
| 25 | #include <asm/time.h> |
| 26 | |
| 27 | #ifdef CONFIG_X86_64 |
| 28 | __visible volatile unsigned long jiffies __cacheline_aligned_in_smp = INITIAL_JIFFIES; |
| 29 | #endif |
| 30 | |
| 31 | unsigned long profile_pc(struct pt_regs *regs) |
| 32 | { |
| 33 | unsigned long pc = instruction_pointer(regs); |
| 34 | |
| 35 | if (!user_mode(regs) && in_lock_functions(pc)) { |
| 36 | #ifdef CONFIG_FRAME_POINTER |
| 37 | return *(unsigned long *)(regs->bp + sizeof(long)); |
| 38 | #else |
| 39 | unsigned long *sp = |
| 40 | (unsigned long *)kernel_stack_pointer(regs); |
| 41 | /* |
| 42 | * Return address is either directly at stack pointer |
| 43 | * or above a saved flags. Eflags has bits 22-31 zero, |
| 44 | * kernel addresses don't. |
| 45 | */ |
| 46 | if (sp[0] >> 22) |
| 47 | return sp[0]; |
| 48 | if (sp[1] >> 22) |
| 49 | return sp[1]; |
| 50 | #endif |
| 51 | } |
| 52 | return pc; |
| 53 | } |
| 54 | EXPORT_SYMBOL(profile_pc); |
| 55 | |
| 56 | /* |
| 57 | * Default timer interrupt handler for PIT/HPET |
| 58 | */ |
| 59 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
| 60 | { |
| 61 | global_clock_event->event_handler(global_clock_event); |
| 62 | return IRQ_HANDLED; |
| 63 | } |
| 64 | |
| 65 | static struct irqaction irq0 = { |
| 66 | .handler = timer_interrupt, |
| 67 | .flags = IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER, |
| 68 | .name = "timer" |
| 69 | }; |
| 70 | |
| 71 | static void __init setup_default_timer_irq(void) |
| 72 | { |
| 73 | /* |
| 74 | * Unconditionally register the legacy timer; even without legacy |
| 75 | * PIC/PIT we need this for the HPET0 in legacy replacement mode. |
| 76 | */ |
| 77 | if (setup_irq(0, &irq0)) |
| 78 | pr_info("Failed to register legacy timer interrupt\n"); |
| 79 | } |
| 80 | |
| 81 | /* Default timer init function */ |
| 82 | void __init hpet_time_init(void) |
| 83 | { |
| 84 | if (!hpet_enable()) |
| 85 | setup_pit_timer(); |
| 86 | setup_default_timer_irq(); |
| 87 | } |
| 88 | |
| 89 | static __init void x86_late_time_init(void) |
| 90 | { |
| 91 | x86_init.timers.timer_init(); |
| 92 | /* |
| 93 | * After PIT/HPET timers init, select and setup |
| 94 | * the final interrupt mode for delivering IRQs. |
| 95 | */ |
| 96 | x86_init.irqs.intr_mode_init(); |
| 97 | tsc_init(); |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * Initialize TSC and delay the periodic timer init to |
| 102 | * late x86_late_time_init() so ioremap works. |
| 103 | */ |
| 104 | void __init time_init(void) |
| 105 | { |
| 106 | late_time_init = x86_late_time_init; |
| 107 | } |