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review.trustedfirmware.org / hafnium / third_party / linux / 157378f43faad830e4aa3815bde5fa9f9a9f5be6 / . / drivers / mmc / host / renesas_sdhi.h
blob: cb962c7883dcd05a537b129aabca21aa2330c985 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * Renesas Mobile SDHI
4 *
5 * Copyright (C) 2017 Horms Solutions Ltd., Simon Horman
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]6 * Copyright (C) 2017-19 Renesas Electronics Corporation
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]7 */
8
9#ifndef RENESAS_SDHI_H
10#define RENESAS_SDHI_H
11
12#include <linux/platform_device.h>
13#include "tmio_mmc.h"
14
15struct renesas_sdhi_scc {
16 unsigned long clk_rate; /* clock rate for SDR104 */
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]17 u32 tap; /* sampling clock position for SDR104/HS400 (8 TAP) */
18 u32 tap_hs400_4tap; /* sampling clock position for HS400 (4 TAP) */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]19};
20
21struct renesas_sdhi_of_data {
22 unsigned long tmio_flags;
23 u32 tmio_ocr_mask;
24 unsigned long capabilities;
25 unsigned long capabilities2;
26 enum dma_slave_buswidth dma_buswidth;
27 dma_addr_t dma_rx_offset;
28 unsigned int bus_shift;
29 int scc_offset;
30 struct renesas_sdhi_scc *taps;
31 int taps_num;
32 unsigned int max_blk_count;
33 unsigned short max_segs;
34};
35
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]36#define SDHI_CALIB_TABLE_MAX 32
37
38struct renesas_sdhi_quirks {
39 bool hs400_disabled;
40 bool hs400_4taps;
41 u32 hs400_bad_taps;
42 const u8 (*hs400_calib_table)[SDHI_CALIB_TABLE_MAX];
43};
44
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]45struct tmio_mmc_dma {
46 enum dma_slave_buswidth dma_buswidth;
47 bool (*filter)(struct dma_chan *chan, void *arg);
48 void (*enable)(struct tmio_mmc_host *host, bool enable);
49 struct completion dma_dataend;
50 struct tasklet_struct dma_complete;
51};
52
53struct renesas_sdhi {
54 struct clk *clk;
55 struct clk *clk_cd;
56 struct tmio_mmc_data mmc_data;
57 struct tmio_mmc_dma dma_priv;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]58 const struct renesas_sdhi_quirks *quirks;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]59 struct pinctrl *pinctrl;
60 struct pinctrl_state *pins_default, *pins_uhs;
61 void __iomem *scc_ctl;
62 u32 scc_tappos;
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]63 u32 scc_tappos_hs400;
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]64 const u8 *adjust_hs400_calib_table;
65 bool needs_adjust_hs400;
66
67 /* Tuning values: 1 for success, 0 for failure */
68 DECLARE_BITMAP(taps, BITS_PER_LONG);
69 /* Sampling data comparison: 1 for match, 0 for mismatch */
70 DECLARE_BITMAP(smpcmp, BITS_PER_LONG);
71 unsigned int tap_num;
72 unsigned int tap_set;
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]73};
74
75#define host_to_priv(host) \
76 container_of((host)->pdata, struct renesas_sdhi, mmc_data)
77
78int renesas_sdhi_probe(struct platform_device *pdev,
79 const struct tmio_mmc_dma_ops *dma_ops);
80int renesas_sdhi_remove(struct platform_device *pdev);
81#endif