TrustedFirmware Git Browser
Code Review Sign In
review.trustedfirmware.org / hafnium / third_party / linux / 157378f43faad830e4aa3815bde5fa9f9a9f5be6 / . / arch / powerpc / kernel / vdso32 / cacheflush.S
blob: 3440ddf21c8b43fa9a5f8a9514a5e63c4cc2d549 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-or-later */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * vDSO provided cache flush routines
4 *
5 * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org),
6 * IBM Corp.
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]7 */
8#include <asm/processor.h>
9#include <asm/ppc_asm.h>
10#include <asm/vdso.h>
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]11#include <asm/vdso_datapage.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]12#include <asm/asm-offsets.h>
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]13#include <asm/cache.h>
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]14
15 .text
16
17/*
18 * Default "generic" version of __kernel_sync_dicache.
19 *
20 * void __kernel_sync_dicache(unsigned long start, unsigned long end)
21 *
22 * Flushes the data cache & invalidate the instruction cache for the
23 * provided range [start, end[
24 */
25V_FUNCTION_BEGIN(__kernel_sync_dicache)
26 .cfi_startproc
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]27#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]28 mflr r12
29 .cfi_register lr,r12
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]30 get_datapage r10, r0
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]31 mtlr r12
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]32#endif
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]33
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]34#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]35 lwz r7,CFG_DCACHE_BLOCKSZ(r10)
36 addi r5,r7,-1
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]37#else
38 li r5, L1_CACHE_BYTES - 1
39#endif
40 andc r6,r3,r5 /* round low to line bdy */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]41 subf r8,r6,r4 /* compute length */
42 add r8,r8,r5 /* ensure we get enough */
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]43#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]44 lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
45 srw. r8,r8,r9 /* compute line count */
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]46#else
47 srwi. r8, r8, L1_CACHE_SHIFT
48 mr r7, r6
49#endif
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]50 crclr cr0*4+so
51 beqlr /* nothing to do? */
52 mtctr r8
531: dcbst 0,r6
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]54#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]55 add r6,r6,r7
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]56#else
57 addi r6, r6, L1_CACHE_BYTES
58#endif
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]59 bdnz 1b
60 sync
61
62/* Now invalidate the instruction cache */
63
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]64#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]65 lwz r7,CFG_ICACHE_BLOCKSZ(r10)
66 addi r5,r7,-1
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]67 andc r6,r3,r5 /* round low to line bdy */
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]68 subf r8,r6,r4 /* compute length */
69 add r8,r8,r5
70 lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
71 srw. r8,r8,r9 /* compute line count */
72 crclr cr0*4+so
73 beqlr /* nothing to do? */
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]74#endif
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]75 mtctr r8
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]76#ifdef CONFIG_PPC64
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]772: icbi 0,r6
78 add r6,r6,r7
Olivier Deprez157378f2022-04-04 15:47:50 +0200[diff] [blame^]79#else
802: icbi 0, r7
81 addi r7, r7, L1_CACHE_BYTES
82#endif
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]83 bdnz 2b
84 isync
85 li r3,0
86 blr
87 .cfi_endproc
88V_FUNCTION_END(__kernel_sync_dicache)
89
90
91/*
92 * POWER5 version of __kernel_sync_dicache
93 */
94V_FUNCTION_BEGIN(__kernel_sync_dicache_p5)
95 .cfi_startproc
96 crclr cr0*4+so
97 sync
98 isync
99 li r3,0
100 blr
101 .cfi_endproc
102V_FUNCTION_END(__kernel_sync_dicache_p5)
103