| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| 2 | /* |
| 3 | * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| 4 | */ |
| 5 | |
| 6 | /* |
| 7 | * VScom OnRISC |
| 8 | * http://www.vscom.de |
| 9 | */ |
| 10 | |
| 11 | /dts-v1/; |
| 12 | |
| 13 | #include "am335x-baltos.dtsi" |
| 14 | #include "am335x-baltos-leds.dtsi" |
| 15 | |
| 16 | / { |
| 17 | model = "NetCom Plus"; |
| 18 | }; |
| 19 | |
| 20 | &am33xx_pinmux { |
| 21 | uart1_pins: pinmux_uart1_pins { |
| 22 | pinctrl-single,pins = < |
| 23 | AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0) /* RX */ |
| 24 | AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0) /* TX */ |
| 25 | AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0) /* CTS */ |
| 26 | AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */ |
| 27 | AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ |
| 28 | AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ |
| 29 | AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ |
| 30 | AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ |
| 31 | >; |
| 32 | }; |
| 33 | |
| 34 | uart2_pins: pinmux_uart2_pins { |
| 35 | pinctrl-single,pins = < |
| 36 | AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* RX */ |
| 37 | AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* TX */ |
| 38 | AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* CTS */ |
| 39 | AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */ |
| 40 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* DTR */ |
| 41 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DSR */ |
| 42 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* DCD */ |
| 43 | AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* RI */ |
| 44 | >; |
| 45 | }; |
| 46 | }; |
| 47 | |
| 48 | &usb0_phy { |
| 49 | status = "okay"; |
| 50 | }; |
| 51 | |
| 52 | &usb0 { |
| 53 | status = "okay"; |
| 54 | dr_mode = "host"; |
| 55 | }; |
| 56 | |
| 57 | &uart1 { |
| 58 | pinctrl-names = "default"; |
| 59 | pinctrl-0 = <&uart1_pins>; |
| 60 | dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; |
| 61 | dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; |
| 62 | dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; |
| 63 | rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; |
| 64 | |
| 65 | status = "okay"; |
| 66 | }; |
| 67 | |
| 68 | &uart2 { |
| 69 | pinctrl-names = "default"; |
| 70 | pinctrl-0 = <&uart2_pins>; |
| 71 | dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; |
| 72 | dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; |
| 73 | dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; |
| 74 | rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; |
| 75 | |
| 76 | status = "okay"; |
| 77 | }; |
| 78 | |
| 79 | &davinci_mdio { |
| 80 | phy0: ethernet-phy@0 { |
| 81 | reg = <1>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | &cpsw_emac0 { |
| 86 | phy-mode = "rmii"; |
| 87 | dual_emac_res_vlan = <1>; |
| 88 | phy-handle = <&phy0>; |
| 89 | }; |
| 90 | |
| 91 | &cpsw_emac1 { |
| 92 | phy-mode = "rgmii-id"; |
| 93 | dual_emac_res_vlan = <2>; |
| 94 | phy-handle = <&phy1>; |
| 95 | }; |