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review.trustedfirmware.org / hafnium / third_party / linux / 0f672f6c0b52b7b0700b0915c72b540721af4465 / . / sound / soc / sof / intel / hda.h
blob: 23e430d3e056881853cc193e549ede0334b624da [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/*
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * Copyright(c) 2017 Intel Corporation. All rights reserved.
7 *
8 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 */
10
11#ifndef __SOF_INTEL_HDA_H
12#define __SOF_INTEL_HDA_H
13
14#include <sound/hda_codec.h>
15#include <sound/hdaudio_ext.h>
16#include "shim.h"
17
18/* PCI registers */
19#define PCI_TCSEL 0x44
20#define PCI_PGCTL PCI_TCSEL
21#define PCI_CGCTL 0x48
22
23/* PCI_PGCTL bits */
24#define PCI_PGCTL_ADSPPGD BIT(2)
25#define PCI_PGCTL_LSRMD_MASK BIT(4)
26
27/* PCI_CGCTL bits */
28#define PCI_CGCTL_MISCBDCGE_MASK BIT(6)
29#define PCI_CGCTL_ADSPDCGE BIT(1)
30
31/* Legacy HDA registers and bits used - widths are variable */
32#define SOF_HDA_GCAP 0x0
33#define SOF_HDA_GCTL 0x8
34/* accept unsol. response enable */
35#define SOF_HDA_GCTL_UNSOL BIT(8)
36#define SOF_HDA_LLCH 0x14
37#define SOF_HDA_INTCTL 0x20
38#define SOF_HDA_INTSTS 0x24
39#define SOF_HDA_WAKESTS 0x0E
40#define SOF_HDA_WAKESTS_INT_MASK ((1 << 8) - 1)
41#define SOF_HDA_RIRBSTS 0x5d
42
43/* SOF_HDA_GCTL register bist */
44#define SOF_HDA_GCTL_RESET BIT(0)
45
46/* SOF_HDA_INCTL and SOF_HDA_INTSTS regs */
47#define SOF_HDA_INT_GLOBAL_EN BIT(31)
48#define SOF_HDA_INT_CTRL_EN BIT(30)
49#define SOF_HDA_INT_ALL_STREAM 0xff
50
51#define SOF_HDA_MAX_CAPS 10
52#define SOF_HDA_CAP_ID_OFF 16
53#define SOF_HDA_CAP_ID_MASK GENMASK(SOF_HDA_CAP_ID_OFF + 11,\
54 SOF_HDA_CAP_ID_OFF)
55#define SOF_HDA_CAP_NEXT_MASK 0xFFFF
56
57#define SOF_HDA_GTS_CAP_ID 0x1
58#define SOF_HDA_ML_CAP_ID 0x2
59
60#define SOF_HDA_PP_CAP_ID 0x3
61#define SOF_HDA_REG_PP_PPCH 0x10
62#define SOF_HDA_REG_PP_PPCTL 0x04
63#define SOF_HDA_REG_PP_PPSTS 0x08
64#define SOF_HDA_PPCTL_PIE BIT(31)
65#define SOF_HDA_PPCTL_GPROCEN BIT(30)
66
67/* DPIB entry size: 8 Bytes = 2 DWords */
68#define SOF_HDA_DPIB_ENTRY_SIZE 0x8
69
70#define SOF_HDA_SPIB_CAP_ID 0x4
71#define SOF_HDA_DRSM_CAP_ID 0x5
72
73#define SOF_HDA_SPIB_BASE 0x08
74#define SOF_HDA_SPIB_INTERVAL 0x08
75#define SOF_HDA_SPIB_SPIB 0x00
76#define SOF_HDA_SPIB_MAXFIFO 0x04
77
78#define SOF_HDA_PPHC_BASE 0x10
79#define SOF_HDA_PPHC_INTERVAL 0x10
80
81#define SOF_HDA_PPLC_BASE 0x10
82#define SOF_HDA_PPLC_MULTI 0x10
83#define SOF_HDA_PPLC_INTERVAL 0x10
84
85#define SOF_HDA_DRSM_BASE 0x08
86#define SOF_HDA_DRSM_INTERVAL 0x08
87
88/* Descriptor error interrupt */
89#define SOF_HDA_CL_DMA_SD_INT_DESC_ERR 0x10
90
91/* FIFO error interrupt */
92#define SOF_HDA_CL_DMA_SD_INT_FIFO_ERR 0x08
93
94/* Buffer completion interrupt */
95#define SOF_HDA_CL_DMA_SD_INT_COMPLETE 0x04
96
97#define SOF_HDA_CL_DMA_SD_INT_MASK \
98 (SOF_HDA_CL_DMA_SD_INT_DESC_ERR | \
99 SOF_HDA_CL_DMA_SD_INT_FIFO_ERR | \
100 SOF_HDA_CL_DMA_SD_INT_COMPLETE)
101#define SOF_HDA_SD_CTL_DMA_START 0x02 /* Stream DMA start bit */
102
103/* Intel HD Audio Code Loader DMA Registers */
104#define SOF_HDA_ADSP_LOADER_BASE 0x80
105#define SOF_HDA_ADSP_DPLBASE 0x70
106#define SOF_HDA_ADSP_DPUBASE 0x74
107#define SOF_HDA_ADSP_DPLBASE_ENABLE 0x01
108
109/* Stream Registers */
110#define SOF_HDA_ADSP_REG_CL_SD_CTL 0x00
111#define SOF_HDA_ADSP_REG_CL_SD_STS 0x03
112#define SOF_HDA_ADSP_REG_CL_SD_LPIB 0x04
113#define SOF_HDA_ADSP_REG_CL_SD_CBL 0x08
114#define SOF_HDA_ADSP_REG_CL_SD_LVI 0x0C
115#define SOF_HDA_ADSP_REG_CL_SD_FIFOW 0x0E
116#define SOF_HDA_ADSP_REG_CL_SD_FIFOSIZE 0x10
117#define SOF_HDA_ADSP_REG_CL_SD_FORMAT 0x12
118#define SOF_HDA_ADSP_REG_CL_SD_FIFOL 0x14
119#define SOF_HDA_ADSP_REG_CL_SD_BDLPL 0x18
120#define SOF_HDA_ADSP_REG_CL_SD_BDLPU 0x1C
121#define SOF_HDA_ADSP_SD_ENTRY_SIZE 0x20
122
123/* CL: Software Position Based FIFO Capability Registers */
124#define SOF_DSP_REG_CL_SPBFIFO \
125 (SOF_HDA_ADSP_LOADER_BASE + 0x20)
126#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCH 0x0
127#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL 0x4
128#define SOF_HDA_ADSP_REG_CL_SPBFIFO_SPIB 0x8
129#define SOF_HDA_ADSP_REG_CL_SPBFIFO_MAXFIFOS 0xc
130
131/* Stream Number */
132#define SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT 20
133#define SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK \
134 GENMASK(SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT + 3,\
135 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT)
136
137#define HDA_DSP_HDA_BAR 0
138#define HDA_DSP_PP_BAR 1
139#define HDA_DSP_SPIB_BAR 2
140#define HDA_DSP_DRSM_BAR 3
141#define HDA_DSP_BAR 4
142
143#define SRAM_WINDOW_OFFSET(x) (0x80000 + (x) * 0x20000)
144
145#define HDA_DSP_MBOX_OFFSET SRAM_WINDOW_OFFSET(0)
146
147#define HDA_DSP_PANIC_OFFSET(x) \
148 (((x) & 0xFFFFFF) + HDA_DSP_MBOX_OFFSET)
149
150/* SRAM window 0 FW "registers" */
151#define HDA_DSP_SRAM_REG_ROM_STATUS (HDA_DSP_MBOX_OFFSET + 0x0)
152#define HDA_DSP_SRAM_REG_ROM_ERROR (HDA_DSP_MBOX_OFFSET + 0x4)
153/* FW and ROM share offset 4 */
154#define HDA_DSP_SRAM_REG_FW_STATUS (HDA_DSP_MBOX_OFFSET + 0x4)
155#define HDA_DSP_SRAM_REG_FW_TRACEP (HDA_DSP_MBOX_OFFSET + 0x8)
156#define HDA_DSP_SRAM_REG_FW_END (HDA_DSP_MBOX_OFFSET + 0xc)
157
158#define HDA_DSP_MBOX_UPLINK_OFFSET 0x81000
159
160#define HDA_DSP_STREAM_RESET_TIMEOUT 300
161/*
162 * Timeout in us, for setting the stream RUN bit, during
163 * start/stop the stream. The timeout expires if new RUN bit
164 * value cannot be read back within the specified time.
165 */
166#define HDA_DSP_STREAM_RUN_TIMEOUT 300
167#define HDA_DSP_CL_TRIGGER_TIMEOUT 300
168
169#define HDA_DSP_SPIB_ENABLE 1
170#define HDA_DSP_SPIB_DISABLE 0
171
172#define SOF_HDA_MAX_BUFFER_SIZE (32 * PAGE_SIZE)
173
174#define HDA_DSP_STACK_DUMP_SIZE 32
175
176/* ROM status/error values */
177#define HDA_DSP_ROM_STS_MASK GENMASK(23, 0)
178#define HDA_DSP_ROM_INIT 0x1
179#define HDA_DSP_ROM_FW_MANIFEST_LOADED 0x3
180#define HDA_DSP_ROM_FW_FW_LOADED 0x4
181#define HDA_DSP_ROM_FW_ENTERED 0x5
182#define HDA_DSP_ROM_RFW_START 0xf
183#define HDA_DSP_ROM_CSE_ERROR 40
184#define HDA_DSP_ROM_CSE_WRONG_RESPONSE 41
185#define HDA_DSP_ROM_IMR_TO_SMALL 42
186#define HDA_DSP_ROM_BASE_FW_NOT_FOUND 43
187#define HDA_DSP_ROM_CSE_VALIDATION_FAILED 44
188#define HDA_DSP_ROM_IPC_FATAL_ERROR 45
189#define HDA_DSP_ROM_L2_CACHE_ERROR 46
190#define HDA_DSP_ROM_LOAD_OFFSET_TO_SMALL 47
191#define HDA_DSP_ROM_API_PTR_INVALID 50
192#define HDA_DSP_ROM_BASEFW_INCOMPAT 51
193#define HDA_DSP_ROM_UNHANDLED_INTERRUPT 0xBEE00000
194#define HDA_DSP_ROM_MEMORY_HOLE_ECC 0xECC00000
195#define HDA_DSP_ROM_KERNEL_EXCEPTION 0xCAFE0000
196#define HDA_DSP_ROM_USER_EXCEPTION 0xBEEF0000
197#define HDA_DSP_ROM_UNEXPECTED_RESET 0xDECAF000
198#define HDA_DSP_ROM_NULL_FW_ENTRY 0x4c4c4e55
199#define HDA_DSP_IPC_PURGE_FW 0x01004000
200
201/* various timeout values */
202#define HDA_DSP_PU_TIMEOUT 50
203#define HDA_DSP_PD_TIMEOUT 50
204#define HDA_DSP_RESET_TIMEOUT_US 50000
205#define HDA_DSP_BASEFW_TIMEOUT_US 3000000
206#define HDA_DSP_INIT_TIMEOUT_US 500000
207#define HDA_DSP_CTRL_RESET_TIMEOUT 100
208#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
209#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
210
211#define HDA_DSP_ADSPIC_IPC 1
212#define HDA_DSP_ADSPIS_IPC 1
213
214/* Intel HD Audio General DSP Registers */
215#define HDA_DSP_GEN_BASE 0x0
216#define HDA_DSP_REG_ADSPCS (HDA_DSP_GEN_BASE + 0x04)
217#define HDA_DSP_REG_ADSPIC (HDA_DSP_GEN_BASE + 0x08)
218#define HDA_DSP_REG_ADSPIS (HDA_DSP_GEN_BASE + 0x0C)
219#define HDA_DSP_REG_ADSPIC2 (HDA_DSP_GEN_BASE + 0x10)
220#define HDA_DSP_REG_ADSPIS2 (HDA_DSP_GEN_BASE + 0x14)
221
222/* Intel HD Audio Inter-Processor Communication Registers */
223#define HDA_DSP_IPC_BASE 0x40
224#define HDA_DSP_REG_HIPCT (HDA_DSP_IPC_BASE + 0x00)
225#define HDA_DSP_REG_HIPCTE (HDA_DSP_IPC_BASE + 0x04)
226#define HDA_DSP_REG_HIPCI (HDA_DSP_IPC_BASE + 0x08)
227#define HDA_DSP_REG_HIPCIE (HDA_DSP_IPC_BASE + 0x0C)
228#define HDA_DSP_REG_HIPCCTL (HDA_DSP_IPC_BASE + 0x10)
229
230/* Intel Vendor Specific Registers */
231#define HDA_VS_INTEL_EM2 0x1030
232#define HDA_VS_INTEL_EM2_L1SEN BIT(13)
233
234/* HIPCI */
235#define HDA_DSP_REG_HIPCI_BUSY BIT(31)
236#define HDA_DSP_REG_HIPCI_MSG_MASK 0x7FFFFFFF
237
238/* HIPCIE */
239#define HDA_DSP_REG_HIPCIE_DONE BIT(30)
240#define HDA_DSP_REG_HIPCIE_MSG_MASK 0x3FFFFFFF
241
242/* HIPCCTL */
243#define HDA_DSP_REG_HIPCCTL_DONE BIT(1)
244#define HDA_DSP_REG_HIPCCTL_BUSY BIT(0)
245
246/* HIPCT */
247#define HDA_DSP_REG_HIPCT_BUSY BIT(31)
248#define HDA_DSP_REG_HIPCT_MSG_MASK 0x7FFFFFFF
249
250/* HIPCTE */
251#define HDA_DSP_REG_HIPCTE_MSG_MASK 0x3FFFFFFF
252
253#define HDA_DSP_ADSPIC_CL_DMA 0x2
254#define HDA_DSP_ADSPIS_CL_DMA 0x2
255
256/* Delay before scheduling D0i3 entry */
257#define BXT_D0I3_DELAY 5000
258
259#define FW_CL_STREAM_NUMBER 0x1
260
261/* ADSPCS - Audio DSP Control & Status */
262
263/*
264 * Core Reset - asserted high
265 * CRST Mask for a given core mask pattern, cm
266 */
267#define HDA_DSP_ADSPCS_CRST_SHIFT 0
268#define HDA_DSP_ADSPCS_CRST_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CRST_SHIFT)
269
270/*
271 * Core run/stall - when set to '1' core is stalled
272 * CSTALL Mask for a given core mask pattern, cm
273 */
274#define HDA_DSP_ADSPCS_CSTALL_SHIFT 8
275#define HDA_DSP_ADSPCS_CSTALL_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CSTALL_SHIFT)
276
277/*
278 * Set Power Active - when set to '1' turn cores on
279 * SPA Mask for a given core mask pattern, cm
280 */
281#define HDA_DSP_ADSPCS_SPA_SHIFT 16
282#define HDA_DSP_ADSPCS_SPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_SPA_SHIFT)
283
284/*
285 * Current Power Active - power status of cores, set by hardware
286 * CPA Mask for a given core mask pattern, cm
287 */
288#define HDA_DSP_ADSPCS_CPA_SHIFT 24
289#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
290
291/* Mask for a given core index, c = 0.. number of supported cores - 1 */
292#define HDA_DSP_CORE_MASK(c) BIT(c)
293
294/*
295 * Mask for a given number of cores
296 * nc = number of supported cores
297 */
298#define SOF_DSP_CORES_MASK(nc) GENMASK(((nc) - 1), 0)
299
300/* Intel HD Audio Inter-Processor Communication Registers for Cannonlake*/
301#define CNL_DSP_IPC_BASE 0xc0
302#define CNL_DSP_REG_HIPCTDR (CNL_DSP_IPC_BASE + 0x00)
303#define CNL_DSP_REG_HIPCTDA (CNL_DSP_IPC_BASE + 0x04)
304#define CNL_DSP_REG_HIPCTDD (CNL_DSP_IPC_BASE + 0x08)
305#define CNL_DSP_REG_HIPCIDR (CNL_DSP_IPC_BASE + 0x10)
306#define CNL_DSP_REG_HIPCIDA (CNL_DSP_IPC_BASE + 0x14)
307#define CNL_DSP_REG_HIPCCTL (CNL_DSP_IPC_BASE + 0x28)
308
309/* HIPCI */
310#define CNL_DSP_REG_HIPCIDR_BUSY BIT(31)
311#define CNL_DSP_REG_HIPCIDR_MSG_MASK 0x7FFFFFFF
312
313/* HIPCIE */
314#define CNL_DSP_REG_HIPCIDA_DONE BIT(31)
315#define CNL_DSP_REG_HIPCIDA_MSG_MASK 0x7FFFFFFF
316
317/* HIPCCTL */
318#define CNL_DSP_REG_HIPCCTL_DONE BIT(1)
319#define CNL_DSP_REG_HIPCCTL_BUSY BIT(0)
320
321/* HIPCT */
322#define CNL_DSP_REG_HIPCTDR_BUSY BIT(31)
323#define CNL_DSP_REG_HIPCTDR_MSG_MASK 0x7FFFFFFF
324
325/* HIPCTDA */
326#define CNL_DSP_REG_HIPCTDA_DONE BIT(31)
327#define CNL_DSP_REG_HIPCTDA_MSG_MASK 0x7FFFFFFF
328
329/* HIPCTDD */
330#define CNL_DSP_REG_HIPCTDD_MSG_MASK 0x7FFFFFFF
331
332/* BDL */
333#define HDA_DSP_BDL_SIZE 4096
334#define HDA_DSP_MAX_BDL_ENTRIES \
335 (HDA_DSP_BDL_SIZE / sizeof(struct sof_intel_dsp_bdl))
336
337/* Number of DAIs */
338#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
339#define SOF_SKL_NUM_DAIS 14
340#else
341#define SOF_SKL_NUM_DAIS 8
342#endif
343
344/* Intel HD Audio SRAM Window 0*/
345#define HDA_ADSP_SRAM0_BASE_SKL 0x8000
346
347/* Firmware status window */
348#define HDA_ADSP_FW_STATUS_SKL HDA_ADSP_SRAM0_BASE_SKL
349#define HDA_ADSP_ERROR_CODE_SKL (HDA_ADSP_FW_STATUS_SKL + 0x4)
350
351/* Host Device Memory Space */
352#define APL_SSP_BASE_OFFSET 0x2000
353#define CNL_SSP_BASE_OFFSET 0x10000
354
355/* Host Device Memory Size of a Single SSP */
356#define SSP_DEV_MEM_SIZE 0x1000
357
358/* SSP Count of the Platform */
359#define APL_SSP_COUNT 6
360#define CNL_SSP_COUNT 3
361#define ICL_SSP_COUNT 6
362
363/* SSP Registers */
364#define SSP_SSC1_OFFSET 0x4
365#define SSP_SET_SCLK_SLAVE BIT(25)
366#define SSP_SET_SFRM_SLAVE BIT(24)
367#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
368
369#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
370
371struct sof_intel_dsp_bdl {
372 __le32 addr_l;
373 __le32 addr_h;
374 __le32 size;
375 __le32 ioc;
376} __attribute((packed));
377
378#define SOF_HDA_PLAYBACK_STREAMS 16
379#define SOF_HDA_CAPTURE_STREAMS 16
380#define SOF_HDA_PLAYBACK 0
381#define SOF_HDA_CAPTURE 1
382
383/* represents DSP HDA controller frontend - i.e. host facing control */
384struct sof_intel_hda_dev {
385
386 struct hda_bus hbus;
387
388 /* hw config */
389 const struct sof_intel_dsp_desc *desc;
390
391 /* trace */
392 struct hdac_ext_stream *dtrace_stream;
393
394 /* if position update IPC needed */
395 u32 no_ipc_position;
396
397 /* the maximum number of streams (playback + capture) supported */
398 u32 stream_max;
399
400 int irq;
401
402 /* DMIC device */
403 struct platform_device *dmic_dev;
404};
405
406static inline struct hdac_bus *sof_to_bus(struct snd_sof_dev *s)
407{
408 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
409
410 return &hda->hbus.core;
411}
412
413static inline struct hda_bus *sof_to_hbus(struct snd_sof_dev *s)
414{
415 struct sof_intel_hda_dev *hda = s->pdata->hw_pdata;
416
417 return &hda->hbus;
418}
419
420struct sof_intel_hda_stream {
421 struct snd_sof_dev *sdev;
422 struct hdac_ext_stream hda_stream;
423 struct sof_intel_stream stream;
424 int host_reserved; /* reserve host DMA channel */
425};
426
427#define hstream_to_sof_hda_stream(hstream) \
428 container_of(hstream, struct sof_intel_hda_stream, hda_stream)
429
430#define bus_to_sof_hda(bus) \
431 container_of(bus, struct sof_intel_hda_dev, hbus.core)
432
433#define SOF_STREAM_SD_OFFSET(s) \
434 (SOF_HDA_ADSP_SD_ENTRY_SIZE * ((s)->index) \
435 + SOF_HDA_ADSP_LOADER_BASE)
436
437/*
438 * DSP Core services.
439 */
440int hda_dsp_probe(struct snd_sof_dev *sdev);
441int hda_dsp_remove(struct snd_sof_dev *sdev);
442int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev,
443 unsigned int core_mask);
444int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev,
445 unsigned int core_mask);
446int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask);
447int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask);
448int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask);
449int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask);
450int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask);
451bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
452 unsigned int core_mask);
453int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
454 unsigned int core_mask);
455void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev);
456void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev);
457
458int hda_dsp_suspend(struct snd_sof_dev *sdev);
459int hda_dsp_resume(struct snd_sof_dev *sdev);
460int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev);
461int hda_dsp_runtime_resume(struct snd_sof_dev *sdev);
462int hda_dsp_runtime_idle(struct snd_sof_dev *sdev);
463int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev);
464void hda_dsp_dump_skl(struct snd_sof_dev *sdev, u32 flags);
465void hda_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
466void hda_ipc_dump(struct snd_sof_dev *sdev);
467void hda_ipc_irq_dump(struct snd_sof_dev *sdev);
468
469/*
470 * DSP PCM Operations.
471 */
472int hda_dsp_pcm_open(struct snd_sof_dev *sdev,
473 struct snd_pcm_substream *substream);
474int hda_dsp_pcm_close(struct snd_sof_dev *sdev,
475 struct snd_pcm_substream *substream);
476int hda_dsp_pcm_hw_params(struct snd_sof_dev *sdev,
477 struct snd_pcm_substream *substream,
478 struct snd_pcm_hw_params *params,
479 struct sof_ipc_stream_params *ipc_params);
480int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
481 struct snd_pcm_substream *substream);
482int hda_dsp_pcm_trigger(struct snd_sof_dev *sdev,
483 struct snd_pcm_substream *substream, int cmd);
484snd_pcm_uframes_t hda_dsp_pcm_pointer(struct snd_sof_dev *sdev,
485 struct snd_pcm_substream *substream);
486
487/*
488 * DSP Stream Operations.
489 */
490
491int hda_dsp_stream_init(struct snd_sof_dev *sdev);
492void hda_dsp_stream_free(struct snd_sof_dev *sdev);
493int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
494 struct hdac_ext_stream *stream,
495 struct snd_dma_buffer *dmab,
496 struct snd_pcm_hw_params *params);
497int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
498 struct hdac_ext_stream *stream, int cmd);
499irqreturn_t hda_dsp_stream_interrupt(int irq, void *context);
500irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context);
501int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
502 struct snd_dma_buffer *dmab,
503 struct hdac_stream *stream);
504
505struct hdac_ext_stream *
506 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction);
507int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag);
508int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
509 struct hdac_ext_stream *stream,
510 int enable, u32 size);
511
512void hda_ipc_msg_data(struct snd_sof_dev *sdev,
513 struct snd_pcm_substream *substream,
514 void *p, size_t sz);
515int hda_ipc_pcm_params(struct snd_sof_dev *sdev,
516 struct snd_pcm_substream *substream,
517 const struct sof_ipc_pcm_params_reply *reply);
518
519/*
520 * DSP IPC Operations.
521 */
522int hda_dsp_ipc_send_msg(struct snd_sof_dev *sdev,
523 struct snd_sof_ipc_msg *msg);
524void hda_dsp_ipc_get_reply(struct snd_sof_dev *sdev);
525int hda_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
526int hda_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
527
528irqreturn_t hda_dsp_ipc_irq_handler(int irq, void *context);
529irqreturn_t hda_dsp_ipc_irq_thread(int irq, void *context);
530int hda_dsp_ipc_cmd_done(struct snd_sof_dev *sdev, int dir);
531
532/*
533 * DSP Code loader.
534 */
535int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev);
536int hda_dsp_cl_boot_firmware_skl(struct snd_sof_dev *sdev);
537
538/* pre and post fw run ops */
539int hda_dsp_pre_fw_run(struct snd_sof_dev *sdev);
540int hda_dsp_post_fw_run(struct snd_sof_dev *sdev);
541
542/*
543 * HDA Controller Operations.
544 */
545int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev);
546void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable);
547void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable);
548int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset);
549void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable);
550int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable);
551int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset);
552void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev);
553/*
554 * HDA bus operations.
555 */
556void sof_hda_bus_init(struct hdac_bus *bus, struct device *dev);
557
558#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
559/*
560 * HDA Codec operations.
561 */
562int hda_codec_probe_bus(struct snd_sof_dev *sdev);
563void hda_codec_jack_wake_enable(struct snd_sof_dev *sdev);
564void hda_codec_jack_check(struct snd_sof_dev *sdev);
565
566#endif /* CONFIG_SND_SOC_SOF_HDA */
567
568#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA) && IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)
569
570void hda_codec_i915_get(struct snd_sof_dev *sdev);
571void hda_codec_i915_put(struct snd_sof_dev *sdev);
572int hda_codec_i915_init(struct snd_sof_dev *sdev);
573int hda_codec_i915_exit(struct snd_sof_dev *sdev);
574
575#else
576
577static inline void hda_codec_i915_get(struct snd_sof_dev *sdev) { }
578static inline void hda_codec_i915_put(struct snd_sof_dev *sdev) { }
579static inline int hda_codec_i915_init(struct snd_sof_dev *sdev) { return 0; }
580static inline int hda_codec_i915_exit(struct snd_sof_dev *sdev) { return 0; }
581
582#endif /* CONFIG_SND_SOC_SOF_HDA && CONFIG_SND_SOC_HDAC_HDMI */
583
584/*
585 * Trace Control.
586 */
587int hda_dsp_trace_init(struct snd_sof_dev *sdev, u32 *stream_tag);
588int hda_dsp_trace_release(struct snd_sof_dev *sdev);
589int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
590
591/* common dai driver */
592extern struct snd_soc_dai_driver skl_dai[];
593
594/*
595 * Platform Specific HW abstraction Ops.
596 */
597extern const struct snd_sof_dsp_ops sof_apl_ops;
598extern const struct snd_sof_dsp_ops sof_cnl_ops;
599extern const struct snd_sof_dsp_ops sof_skl_ops;
600
601extern const struct sof_intel_dsp_desc apl_chip_info;
602extern const struct sof_intel_dsp_desc cnl_chip_info;
603extern const struct sof_intel_dsp_desc skl_chip_info;
604extern const struct sof_intel_dsp_desc icl_chip_info;
605extern const struct sof_intel_dsp_desc tgl_chip_info;
606extern const struct sof_intel_dsp_desc ehl_chip_info;
607
608#endif