David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs |
| 4 | * |
| 5 | * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> |
| 6 | * |
| 7 | * This driver has been based on the spi-gpio.c: |
| 8 | * Copyright (C) 2006,2008 David Brownell |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/module.h> |
| 13 | #include <linux/delay.h> |
| 14 | #include <linux/spinlock.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/spi/spi.h> |
| 18 | #include <linux/spi/spi_bitbang.h> |
| 19 | #include <linux/bitops.h> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 20 | #include <linux/clk.h> |
| 21 | #include <linux/err.h> |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 22 | #include <linux/platform_data/spi-ath79.h> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 23 | |
| 24 | #define DRV_NAME "ath79-spi" |
| 25 | |
| 26 | #define ATH79_SPI_RRW_DELAY_FACTOR 12000 |
| 27 | #define MHZ (1000 * 1000) |
| 28 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 29 | #define AR71XX_SPI_REG_FS 0x00 /* Function Select */ |
| 30 | #define AR71XX_SPI_REG_CTRL 0x04 /* SPI Control */ |
| 31 | #define AR71XX_SPI_REG_IOC 0x08 /* SPI I/O Control */ |
| 32 | #define AR71XX_SPI_REG_RDS 0x0c /* Read Data Shift */ |
| 33 | |
| 34 | #define AR71XX_SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ |
| 35 | |
| 36 | #define AR71XX_SPI_IOC_DO BIT(0) /* Data Out pin */ |
| 37 | #define AR71XX_SPI_IOC_CLK BIT(8) /* CLK pin */ |
| 38 | #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n)) |
| 39 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 40 | struct ath79_spi { |
| 41 | struct spi_bitbang bitbang; |
| 42 | u32 ioc_base; |
| 43 | u32 reg_ctrl; |
| 44 | void __iomem *base; |
| 45 | struct clk *clk; |
| 46 | unsigned int rrw_delay; |
| 47 | }; |
| 48 | |
| 49 | static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned int reg) |
| 50 | { |
| 51 | return ioread32(sp->base + reg); |
| 52 | } |
| 53 | |
| 54 | static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned int reg, u32 val) |
| 55 | { |
| 56 | iowrite32(val, sp->base + reg); |
| 57 | } |
| 58 | |
| 59 | static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi) |
| 60 | { |
| 61 | return spi_master_get_devdata(spi->master); |
| 62 | } |
| 63 | |
| 64 | static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned int nsecs) |
| 65 | { |
| 66 | if (nsecs > sp->rrw_delay) |
| 67 | ndelay(nsecs - sp->rrw_delay); |
| 68 | } |
| 69 | |
| 70 | static void ath79_spi_chipselect(struct spi_device *spi, int is_active) |
| 71 | { |
| 72 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); |
| 73 | int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 74 | u32 cs_bit = AR71XX_SPI_IOC_CS(spi->chip_select); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 75 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 76 | if (cs_high) |
| 77 | sp->ioc_base |= cs_bit; |
| 78 | else |
| 79 | sp->ioc_base &= ~cs_bit; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 80 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 81 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 82 | } |
| 83 | |
| 84 | static void ath79_spi_enable(struct ath79_spi *sp) |
| 85 | { |
| 86 | /* enable GPIO mode */ |
| 87 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO); |
| 88 | |
| 89 | /* save CTRL register */ |
| 90 | sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL); |
| 91 | sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC); |
| 92 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 93 | /* clear clk and mosi in the base state */ |
| 94 | sp->ioc_base &= ~(AR71XX_SPI_IOC_DO | AR71XX_SPI_IOC_CLK); |
| 95 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 96 | /* TODO: setup speed? */ |
| 97 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43); |
| 98 | } |
| 99 | |
| 100 | static void ath79_spi_disable(struct ath79_spi *sp) |
| 101 | { |
| 102 | /* restore CTRL register */ |
| 103 | ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl); |
| 104 | /* disable GPIO mode */ |
| 105 | ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0); |
| 106 | } |
| 107 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 108 | static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned int nsecs, |
| 109 | u32 word, u8 bits, unsigned flags) |
| 110 | { |
| 111 | struct ath79_spi *sp = ath79_spidev_to_sp(spi); |
| 112 | u32 ioc = sp->ioc_base; |
| 113 | |
| 114 | /* clock starts at inactive polarity */ |
| 115 | for (word <<= (32 - bits); likely(bits); bits--) { |
| 116 | u32 out; |
| 117 | |
| 118 | if (word & (1 << 31)) |
| 119 | out = ioc | AR71XX_SPI_IOC_DO; |
| 120 | else |
| 121 | out = ioc & ~AR71XX_SPI_IOC_DO; |
| 122 | |
| 123 | /* setup MSB (to slave) on trailing edge */ |
| 124 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); |
| 125 | ath79_spi_delay(sp, nsecs); |
| 126 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK); |
| 127 | ath79_spi_delay(sp, nsecs); |
| 128 | if (bits == 1) |
| 129 | ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out); |
| 130 | |
| 131 | word <<= 1; |
| 132 | } |
| 133 | |
| 134 | return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS); |
| 135 | } |
| 136 | |
| 137 | static int ath79_spi_probe(struct platform_device *pdev) |
| 138 | { |
| 139 | struct spi_master *master; |
| 140 | struct ath79_spi *sp; |
| 141 | struct ath79_spi_platform_data *pdata; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 142 | unsigned long rate; |
| 143 | int ret; |
| 144 | |
| 145 | master = spi_alloc_master(&pdev->dev, sizeof(*sp)); |
| 146 | if (master == NULL) { |
| 147 | dev_err(&pdev->dev, "failed to allocate spi master\n"); |
| 148 | return -ENOMEM; |
| 149 | } |
| 150 | |
| 151 | sp = spi_master_get_devdata(master); |
| 152 | master->dev.of_node = pdev->dev.of_node; |
| 153 | platform_set_drvdata(pdev, sp); |
| 154 | |
| 155 | pdata = dev_get_platdata(&pdev->dev); |
| 156 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 157 | master->use_gpio_descriptors = true; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 158 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 159 | master->setup = spi_bitbang_setup; |
| 160 | master->cleanup = spi_bitbang_cleanup; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 161 | if (pdata) { |
| 162 | master->bus_num = pdata->bus_num; |
| 163 | master->num_chipselect = pdata->num_chipselect; |
| 164 | } |
| 165 | |
| 166 | sp->bitbang.master = master; |
| 167 | sp->bitbang.chipselect = ath79_spi_chipselect; |
| 168 | sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 169 | sp->bitbang.flags = SPI_CS_HIGH; |
| 170 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 171 | sp->base = devm_platform_ioremap_resource(pdev, 0); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 172 | if (IS_ERR(sp->base)) { |
| 173 | ret = PTR_ERR(sp->base); |
| 174 | goto err_put_master; |
| 175 | } |
| 176 | |
| 177 | sp->clk = devm_clk_get(&pdev->dev, "ahb"); |
| 178 | if (IS_ERR(sp->clk)) { |
| 179 | ret = PTR_ERR(sp->clk); |
| 180 | goto err_put_master; |
| 181 | } |
| 182 | |
| 183 | ret = clk_prepare_enable(sp->clk); |
| 184 | if (ret) |
| 185 | goto err_put_master; |
| 186 | |
| 187 | rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ); |
| 188 | if (!rate) { |
| 189 | ret = -EINVAL; |
| 190 | goto err_clk_disable; |
| 191 | } |
| 192 | |
| 193 | sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate; |
| 194 | dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n", |
| 195 | sp->rrw_delay); |
| 196 | |
| 197 | ath79_spi_enable(sp); |
| 198 | ret = spi_bitbang_start(&sp->bitbang); |
| 199 | if (ret) |
| 200 | goto err_disable; |
| 201 | |
| 202 | return 0; |
| 203 | |
| 204 | err_disable: |
| 205 | ath79_spi_disable(sp); |
| 206 | err_clk_disable: |
| 207 | clk_disable_unprepare(sp->clk); |
| 208 | err_put_master: |
| 209 | spi_master_put(sp->bitbang.master); |
| 210 | |
| 211 | return ret; |
| 212 | } |
| 213 | |
| 214 | static int ath79_spi_remove(struct platform_device *pdev) |
| 215 | { |
| 216 | struct ath79_spi *sp = platform_get_drvdata(pdev); |
| 217 | |
| 218 | spi_bitbang_stop(&sp->bitbang); |
| 219 | ath79_spi_disable(sp); |
| 220 | clk_disable_unprepare(sp->clk); |
| 221 | spi_master_put(sp->bitbang.master); |
| 222 | |
| 223 | return 0; |
| 224 | } |
| 225 | |
| 226 | static void ath79_spi_shutdown(struct platform_device *pdev) |
| 227 | { |
| 228 | ath79_spi_remove(pdev); |
| 229 | } |
| 230 | |
| 231 | static const struct of_device_id ath79_spi_of_match[] = { |
| 232 | { .compatible = "qca,ar7100-spi", }, |
| 233 | { }, |
| 234 | }; |
| 235 | MODULE_DEVICE_TABLE(of, ath79_spi_of_match); |
| 236 | |
| 237 | static struct platform_driver ath79_spi_driver = { |
| 238 | .probe = ath79_spi_probe, |
| 239 | .remove = ath79_spi_remove, |
| 240 | .shutdown = ath79_spi_shutdown, |
| 241 | .driver = { |
| 242 | .name = DRV_NAME, |
| 243 | .of_match_table = ath79_spi_of_match, |
| 244 | }, |
| 245 | }; |
| 246 | module_platform_driver(ath79_spi_driver); |
| 247 | |
| 248 | MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X"); |
| 249 | MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>"); |
| 250 | MODULE_LICENSE("GPL v2"); |
| 251 | MODULE_ALIAS("platform:" DRV_NAME); |