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review.trustedfirmware.org / hafnium / third_party / linux.git / b4b6d4a02fa8aa8187d426b508fb7f3b69df0dcc / . / drivers / net / ethernet / realtek / r8169.c
blob: 4930e0375c1d5a94c23a0d574eef65979194ae00 [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame^]1/*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/ethtool.h>
19#include <linux/phy.h>
20#include <linux/if_vlan.h>
21#include <linux/crc32.h>
22#include <linux/in.h>
23#include <linux/io.h>
24#include <linux/ip.h>
25#include <linux/tcp.h>
26#include <linux/interrupt.h>
27#include <linux/dma-mapping.h>
28#include <linux/pm_runtime.h>
29#include <linux/firmware.h>
30#include <linux/prefetch.h>
31#include <linux/ipv6.h>
32#include <net/ip6_checksum.h>
33
34#define MODULENAME "r8169"
35
36#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
37#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
38#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
39#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
40#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
41#define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
42#define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
44#define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
45#define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
46#define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
47#define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
48#define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
49#define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
50#define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
51#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
52#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
53#define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
54#define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
55
56#define R8169_MSG_DEFAULT \
57 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
58
59#define TX_SLOTS_AVAIL(tp) \
60 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
61
62/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
63#define TX_FRAGS_READY_FOR(tp,nr_frags) \
64 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
65
66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
68static const int multicast_filter_limit = 32;
69
70#define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_RX_BUF_SIZE (SZ_16K - 1)
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
77#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80#define RTL8169_TX_TIMEOUT (6*HZ)
81
82/* write/read MMIO register */
83#define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
84#define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
85#define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
86#define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
87#define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
88#define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
89
90enum mac_version {
91 RTL_GIGA_MAC_VER_01 = 0,
92 RTL_GIGA_MAC_VER_02,
93 RTL_GIGA_MAC_VER_03,
94 RTL_GIGA_MAC_VER_04,
95 RTL_GIGA_MAC_VER_05,
96 RTL_GIGA_MAC_VER_06,
97 RTL_GIGA_MAC_VER_07,
98 RTL_GIGA_MAC_VER_08,
99 RTL_GIGA_MAC_VER_09,
100 RTL_GIGA_MAC_VER_10,
101 RTL_GIGA_MAC_VER_11,
102 RTL_GIGA_MAC_VER_12,
103 RTL_GIGA_MAC_VER_13,
104 RTL_GIGA_MAC_VER_14,
105 RTL_GIGA_MAC_VER_15,
106 RTL_GIGA_MAC_VER_16,
107 RTL_GIGA_MAC_VER_17,
108 RTL_GIGA_MAC_VER_18,
109 RTL_GIGA_MAC_VER_19,
110 RTL_GIGA_MAC_VER_20,
111 RTL_GIGA_MAC_VER_21,
112 RTL_GIGA_MAC_VER_22,
113 RTL_GIGA_MAC_VER_23,
114 RTL_GIGA_MAC_VER_24,
115 RTL_GIGA_MAC_VER_25,
116 RTL_GIGA_MAC_VER_26,
117 RTL_GIGA_MAC_VER_27,
118 RTL_GIGA_MAC_VER_28,
119 RTL_GIGA_MAC_VER_29,
120 RTL_GIGA_MAC_VER_30,
121 RTL_GIGA_MAC_VER_31,
122 RTL_GIGA_MAC_VER_32,
123 RTL_GIGA_MAC_VER_33,
124 RTL_GIGA_MAC_VER_34,
125 RTL_GIGA_MAC_VER_35,
126 RTL_GIGA_MAC_VER_36,
127 RTL_GIGA_MAC_VER_37,
128 RTL_GIGA_MAC_VER_38,
129 RTL_GIGA_MAC_VER_39,
130 RTL_GIGA_MAC_VER_40,
131 RTL_GIGA_MAC_VER_41,
132 RTL_GIGA_MAC_VER_42,
133 RTL_GIGA_MAC_VER_43,
134 RTL_GIGA_MAC_VER_44,
135 RTL_GIGA_MAC_VER_45,
136 RTL_GIGA_MAC_VER_46,
137 RTL_GIGA_MAC_VER_47,
138 RTL_GIGA_MAC_VER_48,
139 RTL_GIGA_MAC_VER_49,
140 RTL_GIGA_MAC_VER_50,
141 RTL_GIGA_MAC_VER_51,
142 RTL_GIGA_MAC_NONE = 0xff,
143};
144
145#define JUMBO_1K ETH_DATA_LEN
146#define JUMBO_4K (4*1024 - ETH_HLEN - 2)
147#define JUMBO_6K (6*1024 - ETH_HLEN - 2)
148#define JUMBO_7K (7*1024 - ETH_HLEN - 2)
149#define JUMBO_9K (9*1024 - ETH_HLEN - 2)
150
151static const struct {
152 const char *name;
153 const char *fw_name;
154} rtl_chip_infos[] = {
155 /* PCI devices. */
156 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
157 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
158 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
159 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
160 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
161 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
162 /* PCI-E devices. */
163 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
164 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
166 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
167 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
168 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
170 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
171 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
172 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
173 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
174 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
175 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
176 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
179 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
180 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
181 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
182 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
183 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
184 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
186 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
187 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
188 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
189 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
190 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
191 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
192 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
193 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
194 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
195 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
196 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
197 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
198 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
199 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
200 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
201 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
202 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
203 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
204 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
205 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
206 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
207 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
208};
209
210enum cfg_version {
211 RTL_CFG_0 = 0x00,
212 RTL_CFG_1,
213 RTL_CFG_2
214};
215
216static const struct pci_device_id rtl8169_pci_tbl[] = {
217 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
218 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
219 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
222 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
224 { PCI_VENDOR_ID_DLINK, 0x4300,
225 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
226 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
227 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
228 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
229 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
230 { PCI_VENDOR_ID_LINKSYS, 0x1032,
231 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
232 { 0x0001, 0x8168,
233 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
234 {0,},
235};
236
237MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
238
239static int use_dac = -1;
240static struct {
241 u32 msg_enable;
242} debug = { -1 };
243
244enum rtl_registers {
245 MAC0 = 0, /* Ethernet hardware address. */
246 MAC4 = 4,
247 MAR0 = 8, /* Multicast filter. */
248 CounterAddrLow = 0x10,
249 CounterAddrHigh = 0x14,
250 TxDescStartAddrLow = 0x20,
251 TxDescStartAddrHigh = 0x24,
252 TxHDescStartAddrLow = 0x28,
253 TxHDescStartAddrHigh = 0x2c,
254 FLASH = 0x30,
255 ERSR = 0x36,
256 ChipCmd = 0x37,
257 TxPoll = 0x38,
258 IntrMask = 0x3c,
259 IntrStatus = 0x3e,
260
261 TxConfig = 0x40,
262#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
263#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
264
265 RxConfig = 0x44,
266#define RX128_INT_EN (1 << 15) /* 8111c and later */
267#define RX_MULTI_EN (1 << 14) /* 8111c only */
268#define RXCFG_FIFO_SHIFT 13
269 /* No threshold before first PCI xfer */
270#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
271#define RX_EARLY_OFF (1 << 11)
272#define RXCFG_DMA_SHIFT 8
273 /* Unlimited maximum PCI burst. */
274#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
275
276 RxMissed = 0x4c,
277 Cfg9346 = 0x50,
278 Config0 = 0x51,
279 Config1 = 0x52,
280 Config2 = 0x53,
281#define PME_SIGNAL (1 << 5) /* 8168c and later */
282
283 Config3 = 0x54,
284 Config4 = 0x55,
285 Config5 = 0x56,
286 MultiIntr = 0x5c,
287 PHYAR = 0x60,
288 PHYstatus = 0x6c,
289 RxMaxSize = 0xda,
290 CPlusCmd = 0xe0,
291 IntrMitigate = 0xe2,
292
293#define RTL_COALESCE_MASK 0x0f
294#define RTL_COALESCE_SHIFT 4
295#define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
296#define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
297
298 RxDescAddrLow = 0xe4,
299 RxDescAddrHigh = 0xe8,
300 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
301
302#define NoEarlyTx 0x3f /* Max value : no early transmit. */
303
304 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
305
306#define TxPacketMax (8064 >> 7)
307#define EarlySize 0x27
308
309 FuncEvent = 0xf0,
310 FuncEventMask = 0xf4,
311 FuncPresetState = 0xf8,
312 IBCR0 = 0xf8,
313 IBCR2 = 0xf9,
314 IBIMR0 = 0xfa,
315 IBISR0 = 0xfb,
316 FuncForceEvent = 0xfc,
317};
318
319enum rtl8168_8101_registers {
320 CSIDR = 0x64,
321 CSIAR = 0x68,
322#define CSIAR_FLAG 0x80000000
323#define CSIAR_WRITE_CMD 0x80000000
324#define CSIAR_BYTE_ENABLE 0x0000f000
325#define CSIAR_ADDR_MASK 0x00000fff
326 PMCH = 0x6f,
327 EPHYAR = 0x80,
328#define EPHYAR_FLAG 0x80000000
329#define EPHYAR_WRITE_CMD 0x80000000
330#define EPHYAR_REG_MASK 0x1f
331#define EPHYAR_REG_SHIFT 16
332#define EPHYAR_DATA_MASK 0xffff
333 DLLPR = 0xd0,
334#define PFM_EN (1 << 6)
335#define TX_10M_PS_EN (1 << 7)
336 DBG_REG = 0xd1,
337#define FIX_NAK_1 (1 << 4)
338#define FIX_NAK_2 (1 << 3)
339 TWSI = 0xd2,
340 MCU = 0xd3,
341#define NOW_IS_OOB (1 << 7)
342#define TX_EMPTY (1 << 5)
343#define RX_EMPTY (1 << 4)
344#define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
345#define EN_NDP (1 << 3)
346#define EN_OOB_RESET (1 << 2)
347#define LINK_LIST_RDY (1 << 1)
348 EFUSEAR = 0xdc,
349#define EFUSEAR_FLAG 0x80000000
350#define EFUSEAR_WRITE_CMD 0x80000000
351#define EFUSEAR_READ_CMD 0x00000000
352#define EFUSEAR_REG_MASK 0x03ff
353#define EFUSEAR_REG_SHIFT 8
354#define EFUSEAR_DATA_MASK 0xff
355 MISC_1 = 0xf2,
356#define PFM_D3COLD_EN (1 << 6)
357};
358
359enum rtl8168_registers {
360 LED_FREQ = 0x1a,
361 EEE_LED = 0x1b,
362 ERIDR = 0x70,
363 ERIAR = 0x74,
364#define ERIAR_FLAG 0x80000000
365#define ERIAR_WRITE_CMD 0x80000000
366#define ERIAR_READ_CMD 0x00000000
367#define ERIAR_ADDR_BYTE_ALIGN 4
368#define ERIAR_TYPE_SHIFT 16
369#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
370#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
371#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
372#define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
373#define ERIAR_MASK_SHIFT 12
374#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
375#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
377#define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
378#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
379 EPHY_RXER_NUM = 0x7c,
380 OCPDR = 0xb0, /* OCP GPHY access */
381#define OCPDR_WRITE_CMD 0x80000000
382#define OCPDR_READ_CMD 0x00000000
383#define OCPDR_REG_MASK 0x7f
384#define OCPDR_GPHY_REG_SHIFT 16
385#define OCPDR_DATA_MASK 0xffff
386 OCPAR = 0xb4,
387#define OCPAR_FLAG 0x80000000
388#define OCPAR_GPHY_WRITE_CMD 0x8000f060
389#define OCPAR_GPHY_READ_CMD 0x0000f060
390 GPHY_OCP = 0xb8,
391 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
392 MISC = 0xf0, /* 8168e only. */
393#define TXPLA_RST (1 << 29)
394#define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
395#define PWM_EN (1 << 22)
396#define RXDV_GATED_EN (1 << 19)
397#define EARLY_TALLY_EN (1 << 16)
398};
399
400enum rtl_register_content {
401 /* InterruptStatusBits */
402 SYSErr = 0x8000,
403 PCSTimeout = 0x4000,
404 SWInt = 0x0100,
405 TxDescUnavail = 0x0080,
406 RxFIFOOver = 0x0040,
407 LinkChg = 0x0020,
408 RxOverflow = 0x0010,
409 TxErr = 0x0008,
410 TxOK = 0x0004,
411 RxErr = 0x0002,
412 RxOK = 0x0001,
413
414 /* RxStatusDesc */
415 RxBOVF = (1 << 24),
416 RxFOVF = (1 << 23),
417 RxRWT = (1 << 22),
418 RxRES = (1 << 21),
419 RxRUNT = (1 << 20),
420 RxCRC = (1 << 19),
421
422 /* ChipCmdBits */
423 StopReq = 0x80,
424 CmdReset = 0x10,
425 CmdRxEnb = 0x08,
426 CmdTxEnb = 0x04,
427 RxBufEmpty = 0x01,
428
429 /* TXPoll register p.5 */
430 HPQ = 0x80, /* Poll cmd on the high prio queue */
431 NPQ = 0x40, /* Poll cmd on the low prio queue */
432 FSWInt = 0x01, /* Forced software interrupt */
433
434 /* Cfg9346Bits */
435 Cfg9346_Lock = 0x00,
436 Cfg9346_Unlock = 0xc0,
437
438 /* rx_mode_bits */
439 AcceptErr = 0x20,
440 AcceptRunt = 0x10,
441 AcceptBroadcast = 0x08,
442 AcceptMulticast = 0x04,
443 AcceptMyPhys = 0x02,
444 AcceptAllPhys = 0x01,
445#define RX_CONFIG_ACCEPT_MASK 0x3f
446
447 /* TxConfigBits */
448 TxInterFrameGapShift = 24,
449 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
450
451 /* Config1 register p.24 */
452 LEDS1 = (1 << 7),
453 LEDS0 = (1 << 6),
454 Speed_down = (1 << 4),
455 MEMMAP = (1 << 3),
456 IOMAP = (1 << 2),
457 VPD = (1 << 1),
458 PMEnable = (1 << 0), /* Power Management Enable */
459
460 /* Config2 register p. 25 */
461 ClkReqEn = (1 << 7), /* Clock Request Enable */
462 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
463 PCI_Clock_66MHz = 0x01,
464 PCI_Clock_33MHz = 0x00,
465
466 /* Config3 register p.25 */
467 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
468 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
469 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
470 Rdy_to_L23 = (1 << 1), /* L23 Enable */
471 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
472
473 /* Config4 register */
474 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
475
476 /* Config5 register p.27 */
477 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
478 MWF = (1 << 5), /* Accept Multicast wakeup frame */
479 UWF = (1 << 4), /* Accept Unicast wakeup frame */
480 Spi_en = (1 << 3),
481 LanWake = (1 << 1), /* LanWake enable/disable */
482 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
483 ASPM_en = (1 << 0), /* ASPM enable */
484
485 /* CPlusCmd p.31 */
486 EnableBist = (1 << 15), // 8168 8101
487 Mac_dbgo_oe = (1 << 14), // 8168 8101
488 Normal_mode = (1 << 13), // unused
489 Force_half_dup = (1 << 12), // 8168 8101
490 Force_rxflow_en = (1 << 11), // 8168 8101
491 Force_txflow_en = (1 << 10), // 8168 8101
492 Cxpl_dbg_sel = (1 << 9), // 8168 8101
493 ASF = (1 << 8), // 8168 8101
494 PktCntrDisable = (1 << 7), // 8168 8101
495 Mac_dbgo_sel = 0x001c, // 8168
496 RxVlan = (1 << 6),
497 RxChkSum = (1 << 5),
498 PCIDAC = (1 << 4),
499 PCIMulRW = (1 << 3),
500#define INTT_MASK GENMASK(1, 0)
501 INTT_0 = 0x0000, // 8168
502 INTT_1 = 0x0001, // 8168
503 INTT_2 = 0x0002, // 8168
504 INTT_3 = 0x0003, // 8168
505
506 /* rtl8169_PHYstatus */
507 TBI_Enable = 0x80,
508 TxFlowCtrl = 0x40,
509 RxFlowCtrl = 0x20,
510 _1000bpsF = 0x10,
511 _100bps = 0x08,
512 _10bps = 0x04,
513 LinkStatus = 0x02,
514 FullDup = 0x01,
515
516 /* _TBICSRBit */
517 TBILinkOK = 0x02000000,
518
519 /* ResetCounterCommand */
520 CounterReset = 0x1,
521
522 /* DumpCounterCommand */
523 CounterDump = 0x8,
524
525 /* magic enable v2 */
526 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
527};
528
529enum rtl_desc_bit {
530 /* First doubleword. */
531 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
532 RingEnd = (1 << 30), /* End of descriptor ring */
533 FirstFrag = (1 << 29), /* First segment of a packet */
534 LastFrag = (1 << 28), /* Final segment of a packet */
535};
536
537/* Generic case. */
538enum rtl_tx_desc_bit {
539 /* First doubleword. */
540 TD_LSO = (1 << 27), /* Large Send Offload */
541#define TD_MSS_MAX 0x07ffu /* MSS value */
542
543 /* Second doubleword. */
544 TxVlanTag = (1 << 17), /* Add VLAN tag */
545};
546
547/* 8169, 8168b and 810x except 8102e. */
548enum rtl_tx_desc_bit_0 {
549 /* First doubleword. */
550#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
551 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
552 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
553 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
554};
555
556/* 8102e, 8168c and beyond. */
557enum rtl_tx_desc_bit_1 {
558 /* First doubleword. */
559 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
560 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
561#define GTTCPHO_SHIFT 18
562#define GTTCPHO_MAX 0x7fU
563
564 /* Second doubleword. */
565#define TCPHO_SHIFT 18
566#define TCPHO_MAX 0x3ffU
567#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
568 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
569 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
570 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
571 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
572};
573
574enum rtl_rx_desc_bit {
575 /* Rx private */
576 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
577 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
578
579#define RxProtoUDP (PID1)
580#define RxProtoTCP (PID0)
581#define RxProtoIP (PID1 | PID0)
582#define RxProtoMask RxProtoIP
583
584 IPFail = (1 << 16), /* IP checksum failed */
585 UDPFail = (1 << 15), /* UDP/IP checksum failed */
586 TCPFail = (1 << 14), /* TCP/IP checksum failed */
587 RxVlanTag = (1 << 16), /* VLAN tag available */
588};
589
590#define RsvdMask 0x3fffc000
591#define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
592
593struct TxDesc {
594 __le32 opts1;
595 __le32 opts2;
596 __le64 addr;
597};
598
599struct RxDesc {
600 __le32 opts1;
601 __le32 opts2;
602 __le64 addr;
603};
604
605struct ring_info {
606 struct sk_buff *skb;
607 u32 len;
608 u8 __pad[sizeof(void *) - sizeof(u32)];
609};
610
611struct rtl8169_counters {
612 __le64 tx_packets;
613 __le64 rx_packets;
614 __le64 tx_errors;
615 __le32 rx_errors;
616 __le16 rx_missed;
617 __le16 align_errors;
618 __le32 tx_one_collision;
619 __le32 tx_multi_collision;
620 __le64 rx_unicast;
621 __le64 rx_broadcast;
622 __le32 rx_multicast;
623 __le16 tx_aborted;
624 __le16 tx_underun;
625};
626
627struct rtl8169_tc_offsets {
628 bool inited;
629 __le64 tx_errors;
630 __le32 tx_multi_collision;
631 __le16 tx_aborted;
632};
633
634enum rtl_flag {
635 RTL_FLAG_TASK_ENABLED = 0,
636 RTL_FLAG_TASK_SLOW_PENDING,
637 RTL_FLAG_TASK_RESET_PENDING,
638 RTL_FLAG_MAX
639};
640
641struct rtl8169_stats {
642 u64 packets;
643 u64 bytes;
644 struct u64_stats_sync syncp;
645};
646
647struct rtl8169_private {
648 void __iomem *mmio_addr; /* memory map physical address */
649 struct pci_dev *pci_dev;
650 struct net_device *dev;
651 struct napi_struct napi;
652 u32 msg_enable;
653 u16 mac_version;
654 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
655 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
656 u32 dirty_tx;
657 struct rtl8169_stats rx_stats;
658 struct rtl8169_stats tx_stats;
659 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
660 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
661 dma_addr_t TxPhyAddr;
662 dma_addr_t RxPhyAddr;
663 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
664 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
665 u16 cp_cmd;
666
667 u16 event_slow;
668 const struct rtl_coalesce_info *coalesce_info;
669 struct clk *clk;
670
671 struct mdio_ops {
672 void (*write)(struct rtl8169_private *, int, int);
673 int (*read)(struct rtl8169_private *, int);
674 } mdio_ops;
675
676 struct jumbo_ops {
677 void (*enable)(struct rtl8169_private *);
678 void (*disable)(struct rtl8169_private *);
679 } jumbo_ops;
680
681 void (*hw_start)(struct rtl8169_private *tp);
682 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
683
684 struct {
685 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
686 struct mutex mutex;
687 struct work_struct work;
688 } wk;
689
690 unsigned supports_gmii:1;
691 struct mii_bus *mii_bus;
692 dma_addr_t counters_phys_addr;
693 struct rtl8169_counters *counters;
694 struct rtl8169_tc_offsets tc_offset;
695 u32 saved_wolopts;
696
697 struct rtl_fw {
698 const struct firmware *fw;
699
700#define RTL_VER_SIZE 32
701
702 char version[RTL_VER_SIZE];
703
704 struct rtl_fw_phy_action {
705 __le32 *code;
706 size_t size;
707 } phy_action;
708 } *rtl_fw;
709#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
710
711 u32 ocp_base;
712};
713
714MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
715MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
716module_param(use_dac, int, 0);
717MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
718module_param_named(debug, debug.msg_enable, int, 0);
719MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
720MODULE_LICENSE("GPL");
721MODULE_FIRMWARE(FIRMWARE_8168D_1);
722MODULE_FIRMWARE(FIRMWARE_8168D_2);
723MODULE_FIRMWARE(FIRMWARE_8168E_1);
724MODULE_FIRMWARE(FIRMWARE_8168E_2);
725MODULE_FIRMWARE(FIRMWARE_8168E_3);
726MODULE_FIRMWARE(FIRMWARE_8105E_1);
727MODULE_FIRMWARE(FIRMWARE_8168F_1);
728MODULE_FIRMWARE(FIRMWARE_8168F_2);
729MODULE_FIRMWARE(FIRMWARE_8402_1);
730MODULE_FIRMWARE(FIRMWARE_8411_1);
731MODULE_FIRMWARE(FIRMWARE_8411_2);
732MODULE_FIRMWARE(FIRMWARE_8106E_1);
733MODULE_FIRMWARE(FIRMWARE_8106E_2);
734MODULE_FIRMWARE(FIRMWARE_8168G_2);
735MODULE_FIRMWARE(FIRMWARE_8168G_3);
736MODULE_FIRMWARE(FIRMWARE_8168H_1);
737MODULE_FIRMWARE(FIRMWARE_8168H_2);
738MODULE_FIRMWARE(FIRMWARE_8107E_1);
739MODULE_FIRMWARE(FIRMWARE_8107E_2);
740
741static inline struct device *tp_to_dev(struct rtl8169_private *tp)
742{
743 return &tp->pci_dev->dev;
744}
745
746static void rtl_lock_work(struct rtl8169_private *tp)
747{
748 mutex_lock(&tp->wk.mutex);
749}
750
751static void rtl_unlock_work(struct rtl8169_private *tp)
752{
753 mutex_unlock(&tp->wk.mutex);
754}
755
756static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
757{
758 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
759 PCI_EXP_DEVCTL_READRQ, force);
760}
761
762struct rtl_cond {
763 bool (*check)(struct rtl8169_private *);
764 const char *msg;
765};
766
767static void rtl_udelay(unsigned int d)
768{
769 udelay(d);
770}
771
772static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
773 void (*delay)(unsigned int), unsigned int d, int n,
774 bool high)
775{
776 int i;
777
778 for (i = 0; i < n; i++) {
779 delay(d);
780 if (c->check(tp) == high)
781 return true;
782 }
783 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
784 c->msg, !high, n, d);
785 return false;
786}
787
788static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
789 const struct rtl_cond *c,
790 unsigned int d, int n)
791{
792 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
793}
794
795static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
796 const struct rtl_cond *c,
797 unsigned int d, int n)
798{
799 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
800}
801
802static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
803 const struct rtl_cond *c,
804 unsigned int d, int n)
805{
806 return rtl_loop_wait(tp, c, msleep, d, n, true);
807}
808
809static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
810 const struct rtl_cond *c,
811 unsigned int d, int n)
812{
813 return rtl_loop_wait(tp, c, msleep, d, n, false);
814}
815
816#define DECLARE_RTL_COND(name) \
817static bool name ## _check(struct rtl8169_private *); \
818 \
819static const struct rtl_cond name = { \
820 .check = name ## _check, \
821 .msg = #name \
822}; \
823 \
824static bool name ## _check(struct rtl8169_private *tp)
825
826static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
827{
828 if (reg & 0xffff0001) {
829 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
830 return true;
831 }
832 return false;
833}
834
835DECLARE_RTL_COND(rtl_ocp_gphy_cond)
836{
837 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
838}
839
840static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
841{
842 if (rtl_ocp_reg_failure(tp, reg))
843 return;
844
845 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
846
847 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
848}
849
850static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
851{
852 if (rtl_ocp_reg_failure(tp, reg))
853 return 0;
854
855 RTL_W32(tp, GPHY_OCP, reg << 15);
856
857 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
858 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
859}
860
861static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
862{
863 if (rtl_ocp_reg_failure(tp, reg))
864 return;
865
866 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
867}
868
869static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
870{
871 if (rtl_ocp_reg_failure(tp, reg))
872 return 0;
873
874 RTL_W32(tp, OCPDR, reg << 15);
875
876 return RTL_R32(tp, OCPDR);
877}
878
879#define OCP_STD_PHY_BASE 0xa400
880
881static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
882{
883 if (reg == 0x1f) {
884 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
885 return;
886 }
887
888 if (tp->ocp_base != OCP_STD_PHY_BASE)
889 reg -= 0x10;
890
891 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
892}
893
894static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
895{
896 if (tp->ocp_base != OCP_STD_PHY_BASE)
897 reg -= 0x10;
898
899 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
900}
901
902static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
903{
904 if (reg == 0x1f) {
905 tp->ocp_base = value << 4;
906 return;
907 }
908
909 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
910}
911
912static int mac_mcu_read(struct rtl8169_private *tp, int reg)
913{
914 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
915}
916
917DECLARE_RTL_COND(rtl_phyar_cond)
918{
919 return RTL_R32(tp, PHYAR) & 0x80000000;
920}
921
922static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
923{
924 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
925
926 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
927 /*
928 * According to hardware specs a 20us delay is required after write
929 * complete indication, but before sending next command.
930 */
931 udelay(20);
932}
933
934static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
935{
936 int value;
937
938 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
939
940 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
941 RTL_R32(tp, PHYAR) & 0xffff : ~0;
942
943 /*
944 * According to hardware specs a 20us delay is required after read
945 * complete indication, but before sending next command.
946 */
947 udelay(20);
948
949 return value;
950}
951
952DECLARE_RTL_COND(rtl_ocpar_cond)
953{
954 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
955}
956
957static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
958{
959 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
960 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
961 RTL_W32(tp, EPHY_RXER_NUM, 0);
962
963 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
964}
965
966static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
967{
968 r8168dp_1_mdio_access(tp, reg,
969 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
970}
971
972static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
973{
974 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
975
976 mdelay(1);
977 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
978 RTL_W32(tp, EPHY_RXER_NUM, 0);
979
980 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
981 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
982}
983
984#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
985
986static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
987{
988 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
989}
990
991static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
992{
993 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
994}
995
996static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
997{
998 r8168dp_2_mdio_start(tp);
999
1000 r8169_mdio_write(tp, reg, value);
1001
1002 r8168dp_2_mdio_stop(tp);
1003}
1004
1005static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1006{
1007 int value;
1008
1009 r8168dp_2_mdio_start(tp);
1010
1011 value = r8169_mdio_read(tp, reg);
1012
1013 r8168dp_2_mdio_stop(tp);
1014
1015 return value;
1016}
1017
1018static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1019{
1020 tp->mdio_ops.write(tp, location, val);
1021}
1022
1023static int rtl_readphy(struct rtl8169_private *tp, int location)
1024{
1025 return tp->mdio_ops.read(tp, location);
1026}
1027
1028static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1029{
1030 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1031}
1032
1033static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1034{
1035 int val;
1036
1037 val = rtl_readphy(tp, reg_addr);
1038 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1039}
1040
1041DECLARE_RTL_COND(rtl_ephyar_cond)
1042{
1043 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1044}
1045
1046static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1047{
1048 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1049 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1050
1051 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1052
1053 udelay(10);
1054}
1055
1056static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1057{
1058 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1059
1060 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1061 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1062}
1063
1064DECLARE_RTL_COND(rtl_eriar_cond)
1065{
1066 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1067}
1068
1069static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1070 u32 val, int type)
1071{
1072 BUG_ON((addr & 3) || (mask == 0));
1073 RTL_W32(tp, ERIDR, val);
1074 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1075
1076 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1077}
1078
1079static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080{
1081 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1082
1083 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084 RTL_R32(tp, ERIDR) : ~0;
1085}
1086
1087static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1088 u32 m, int type)
1089{
1090 u32 val;
1091
1092 val = rtl_eri_read(tp, addr, type);
1093 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1094}
1095
1096static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1097{
1098 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1099 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1100 RTL_R32(tp, OCPDR) : ~0;
1101}
1102
1103static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1104{
1105 return rtl_eri_read(tp, reg, ERIAR_OOB);
1106}
1107
1108static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1109{
1110 switch (tp->mac_version) {
1111 case RTL_GIGA_MAC_VER_27:
1112 case RTL_GIGA_MAC_VER_28:
1113 case RTL_GIGA_MAC_VER_31:
1114 return r8168dp_ocp_read(tp, mask, reg);
1115 case RTL_GIGA_MAC_VER_49:
1116 case RTL_GIGA_MAC_VER_50:
1117 case RTL_GIGA_MAC_VER_51:
1118 return r8168ep_ocp_read(tp, mask, reg);
1119 default:
1120 BUG();
1121 return ~0;
1122 }
1123}
1124
1125static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1126 u32 data)
1127{
1128 RTL_W32(tp, OCPDR, data);
1129 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1130 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1131}
1132
1133static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 u32 data)
1135{
1136 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1137 data, ERIAR_OOB);
1138}
1139
1140static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1141{
1142 switch (tp->mac_version) {
1143 case RTL_GIGA_MAC_VER_27:
1144 case RTL_GIGA_MAC_VER_28:
1145 case RTL_GIGA_MAC_VER_31:
1146 r8168dp_ocp_write(tp, mask, reg, data);
1147 break;
1148 case RTL_GIGA_MAC_VER_49:
1149 case RTL_GIGA_MAC_VER_50:
1150 case RTL_GIGA_MAC_VER_51:
1151 r8168ep_ocp_write(tp, mask, reg, data);
1152 break;
1153 default:
1154 BUG();
1155 break;
1156 }
1157}
1158
1159static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1160{
1161 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1162
1163 ocp_write(tp, 0x1, 0x30, 0x00000001);
1164}
1165
1166#define OOB_CMD_RESET 0x00
1167#define OOB_CMD_DRIVER_START 0x05
1168#define OOB_CMD_DRIVER_STOP 0x06
1169
1170static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1171{
1172 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1173}
1174
1175DECLARE_RTL_COND(rtl_ocp_read_cond)
1176{
1177 u16 reg;
1178
1179 reg = rtl8168_get_ocp_reg(tp);
1180
1181 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1182}
1183
1184DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1185{
1186 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1187}
1188
1189DECLARE_RTL_COND(rtl_ocp_tx_cond)
1190{
1191 return RTL_R8(tp, IBISR0) & 0x20;
1192}
1193
1194static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1195{
1196 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1197 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1198 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1199 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1200}
1201
1202static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1203{
1204 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1205 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1206}
1207
1208static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1209{
1210 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1211 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1212 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1213}
1214
1215static void rtl8168_driver_start(struct rtl8169_private *tp)
1216{
1217 switch (tp->mac_version) {
1218 case RTL_GIGA_MAC_VER_27:
1219 case RTL_GIGA_MAC_VER_28:
1220 case RTL_GIGA_MAC_VER_31:
1221 rtl8168dp_driver_start(tp);
1222 break;
1223 case RTL_GIGA_MAC_VER_49:
1224 case RTL_GIGA_MAC_VER_50:
1225 case RTL_GIGA_MAC_VER_51:
1226 rtl8168ep_driver_start(tp);
1227 break;
1228 default:
1229 BUG();
1230 break;
1231 }
1232}
1233
1234static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1235{
1236 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1237 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1238}
1239
1240static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1241{
1242 rtl8168ep_stop_cmac(tp);
1243 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1244 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1245 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1246}
1247
1248static void rtl8168_driver_stop(struct rtl8169_private *tp)
1249{
1250 switch (tp->mac_version) {
1251 case RTL_GIGA_MAC_VER_27:
1252 case RTL_GIGA_MAC_VER_28:
1253 case RTL_GIGA_MAC_VER_31:
1254 rtl8168dp_driver_stop(tp);
1255 break;
1256 case RTL_GIGA_MAC_VER_49:
1257 case RTL_GIGA_MAC_VER_50:
1258 case RTL_GIGA_MAC_VER_51:
1259 rtl8168ep_driver_stop(tp);
1260 break;
1261 default:
1262 BUG();
1263 break;
1264 }
1265}
1266
1267static bool r8168dp_check_dash(struct rtl8169_private *tp)
1268{
1269 u16 reg = rtl8168_get_ocp_reg(tp);
1270
1271 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1272}
1273
1274static bool r8168ep_check_dash(struct rtl8169_private *tp)
1275{
1276 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1277}
1278
1279static bool r8168_check_dash(struct rtl8169_private *tp)
1280{
1281 switch (tp->mac_version) {
1282 case RTL_GIGA_MAC_VER_27:
1283 case RTL_GIGA_MAC_VER_28:
1284 case RTL_GIGA_MAC_VER_31:
1285 return r8168dp_check_dash(tp);
1286 case RTL_GIGA_MAC_VER_49:
1287 case RTL_GIGA_MAC_VER_50:
1288 case RTL_GIGA_MAC_VER_51:
1289 return r8168ep_check_dash(tp);
1290 default:
1291 return false;
1292 }
1293}
1294
1295struct exgmac_reg {
1296 u16 addr;
1297 u16 mask;
1298 u32 val;
1299};
1300
1301static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1302 const struct exgmac_reg *r, int len)
1303{
1304 while (len-- > 0) {
1305 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1306 r++;
1307 }
1308}
1309
1310DECLARE_RTL_COND(rtl_efusear_cond)
1311{
1312 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1313}
1314
1315static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1316{
1317 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1318
1319 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1320 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1321}
1322
1323static u16 rtl_get_events(struct rtl8169_private *tp)
1324{
1325 return RTL_R16(tp, IntrStatus);
1326}
1327
1328static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1329{
1330 RTL_W16(tp, IntrStatus, bits);
1331 mmiowb();
1332}
1333
1334static void rtl_irq_disable(struct rtl8169_private *tp)
1335{
1336 RTL_W16(tp, IntrMask, 0);
1337 mmiowb();
1338}
1339
1340static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1341{
1342 RTL_W16(tp, IntrMask, bits);
1343}
1344
1345#define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1346#define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1347#define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1348
1349static void rtl_irq_enable_all(struct rtl8169_private *tp)
1350{
1351 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1352}
1353
1354static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1355{
1356 rtl_irq_disable(tp);
1357 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1358 RTL_R8(tp, ChipCmd);
1359}
1360
1361static void rtl_link_chg_patch(struct rtl8169_private *tp)
1362{
1363 struct net_device *dev = tp->dev;
1364 struct phy_device *phydev = dev->phydev;
1365
1366 if (!netif_running(dev))
1367 return;
1368
1369 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1370 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1371 if (phydev->speed == SPEED_1000) {
1372 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1373 ERIAR_EXGMAC);
1374 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1375 ERIAR_EXGMAC);
1376 } else if (phydev->speed == SPEED_100) {
1377 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1378 ERIAR_EXGMAC);
1379 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1380 ERIAR_EXGMAC);
1381 } else {
1382 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1383 ERIAR_EXGMAC);
1384 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1385 ERIAR_EXGMAC);
1386 }
1387 /* Reset packet filter */
1388 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1389 ERIAR_EXGMAC);
1390 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1391 ERIAR_EXGMAC);
1392 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1393 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1394 if (phydev->speed == SPEED_1000) {
1395 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1396 ERIAR_EXGMAC);
1397 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1398 ERIAR_EXGMAC);
1399 } else {
1400 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1401 ERIAR_EXGMAC);
1402 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1403 ERIAR_EXGMAC);
1404 }
1405 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1406 if (phydev->speed == SPEED_10) {
1407 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1408 ERIAR_EXGMAC);
1409 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1410 ERIAR_EXGMAC);
1411 } else {
1412 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1413 ERIAR_EXGMAC);
1414 }
1415 }
1416}
1417
1418#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1419
1420static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1421{
1422 u8 options;
1423 u32 wolopts = 0;
1424
1425 options = RTL_R8(tp, Config1);
1426 if (!(options & PMEnable))
1427 return 0;
1428
1429 options = RTL_R8(tp, Config3);
1430 if (options & LinkUp)
1431 wolopts |= WAKE_PHY;
1432 switch (tp->mac_version) {
1433 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1434 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1435 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1436 wolopts |= WAKE_MAGIC;
1437 break;
1438 default:
1439 if (options & MagicPacket)
1440 wolopts |= WAKE_MAGIC;
1441 break;
1442 }
1443
1444 options = RTL_R8(tp, Config5);
1445 if (options & UWF)
1446 wolopts |= WAKE_UCAST;
1447 if (options & BWF)
1448 wolopts |= WAKE_BCAST;
1449 if (options & MWF)
1450 wolopts |= WAKE_MCAST;
1451
1452 return wolopts;
1453}
1454
1455static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458
1459 rtl_lock_work(tp);
1460 wol->supported = WAKE_ANY;
1461 wol->wolopts = tp->saved_wolopts;
1462 rtl_unlock_work(tp);
1463}
1464
1465static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1466{
1467 unsigned int i, tmp;
1468 static const struct {
1469 u32 opt;
1470 u16 reg;
1471 u8 mask;
1472 } cfg[] = {
1473 { WAKE_PHY, Config3, LinkUp },
1474 { WAKE_UCAST, Config5, UWF },
1475 { WAKE_BCAST, Config5, BWF },
1476 { WAKE_MCAST, Config5, MWF },
1477 { WAKE_ANY, Config5, LanWake },
1478 { WAKE_MAGIC, Config3, MagicPacket }
1479 };
1480 u8 options;
1481
1482 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1483
1484 switch (tp->mac_version) {
1485 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1486 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1487 tmp = ARRAY_SIZE(cfg) - 1;
1488 if (wolopts & WAKE_MAGIC)
1489 rtl_w0w1_eri(tp,
1490 0x0dc,
1491 ERIAR_MASK_0100,
1492 MagicPacket_v2,
1493 0x0000,
1494 ERIAR_EXGMAC);
1495 else
1496 rtl_w0w1_eri(tp,
1497 0x0dc,
1498 ERIAR_MASK_0100,
1499 0x0000,
1500 MagicPacket_v2,
1501 ERIAR_EXGMAC);
1502 break;
1503 default:
1504 tmp = ARRAY_SIZE(cfg);
1505 break;
1506 }
1507
1508 for (i = 0; i < tmp; i++) {
1509 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1510 if (wolopts & cfg[i].opt)
1511 options |= cfg[i].mask;
1512 RTL_W8(tp, cfg[i].reg, options);
1513 }
1514
1515 switch (tp->mac_version) {
1516 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1517 options = RTL_R8(tp, Config1) & ~PMEnable;
1518 if (wolopts)
1519 options |= PMEnable;
1520 RTL_W8(tp, Config1, options);
1521 break;
1522 default:
1523 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1524 if (wolopts)
1525 options |= PME_SIGNAL;
1526 RTL_W8(tp, Config2, options);
1527 break;
1528 }
1529
1530 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1531}
1532
1533static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1534{
1535 struct rtl8169_private *tp = netdev_priv(dev);
1536 struct device *d = tp_to_dev(tp);
1537
1538 if (wol->wolopts & ~WAKE_ANY)
1539 return -EINVAL;
1540
1541 pm_runtime_get_noresume(d);
1542
1543 rtl_lock_work(tp);
1544
1545 tp->saved_wolopts = wol->wolopts;
1546
1547 if (pm_runtime_active(d))
1548 __rtl8169_set_wol(tp, tp->saved_wolopts);
1549
1550 rtl_unlock_work(tp);
1551
1552 device_set_wakeup_enable(d, tp->saved_wolopts);
1553
1554 pm_runtime_put_noidle(d);
1555
1556 return 0;
1557}
1558
1559static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1560{
1561 return rtl_chip_infos[tp->mac_version].fw_name;
1562}
1563
1564static void rtl8169_get_drvinfo(struct net_device *dev,
1565 struct ethtool_drvinfo *info)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 struct rtl_fw *rtl_fw = tp->rtl_fw;
1569
1570 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1571 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1572 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1573 if (!IS_ERR_OR_NULL(rtl_fw))
1574 strlcpy(info->fw_version, rtl_fw->version,
1575 sizeof(info->fw_version));
1576}
1577
1578static int rtl8169_get_regs_len(struct net_device *dev)
1579{
1580 return R8169_REGS_SIZE;
1581}
1582
1583static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1584 netdev_features_t features)
1585{
1586 struct rtl8169_private *tp = netdev_priv(dev);
1587
1588 if (dev->mtu > TD_MSS_MAX)
1589 features &= ~NETIF_F_ALL_TSO;
1590
1591 if (dev->mtu > JUMBO_1K &&
1592 tp->mac_version > RTL_GIGA_MAC_VER_06)
1593 features &= ~NETIF_F_IP_CSUM;
1594
1595 return features;
1596}
1597
1598static int rtl8169_set_features(struct net_device *dev,
1599 netdev_features_t features)
1600{
1601 struct rtl8169_private *tp = netdev_priv(dev);
1602 u32 rx_config;
1603
1604 rtl_lock_work(tp);
1605
1606 rx_config = RTL_R32(tp, RxConfig);
1607 if (features & NETIF_F_RXALL)
1608 rx_config |= (AcceptErr | AcceptRunt);
1609 else
1610 rx_config &= ~(AcceptErr | AcceptRunt);
1611
1612 RTL_W32(tp, RxConfig, rx_config);
1613
1614 if (features & NETIF_F_RXCSUM)
1615 tp->cp_cmd |= RxChkSum;
1616 else
1617 tp->cp_cmd &= ~RxChkSum;
1618
1619 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1620 tp->cp_cmd |= RxVlan;
1621 else
1622 tp->cp_cmd &= ~RxVlan;
1623
1624 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1625 RTL_R16(tp, CPlusCmd);
1626
1627 rtl_unlock_work(tp);
1628
1629 return 0;
1630}
1631
1632static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1633{
1634 return (skb_vlan_tag_present(skb)) ?
1635 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1636}
1637
1638static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1639{
1640 u32 opts2 = le32_to_cpu(desc->opts2);
1641
1642 if (opts2 & RxVlanTag)
1643 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1644}
1645
1646static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1647 void *p)
1648{
1649 struct rtl8169_private *tp = netdev_priv(dev);
1650 u32 __iomem *data = tp->mmio_addr;
1651 u32 *dw = p;
1652 int i;
1653
1654 rtl_lock_work(tp);
1655 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1656 memcpy_fromio(dw++, data++, 4);
1657 rtl_unlock_work(tp);
1658}
1659
1660static u32 rtl8169_get_msglevel(struct net_device *dev)
1661{
1662 struct rtl8169_private *tp = netdev_priv(dev);
1663
1664 return tp->msg_enable;
1665}
1666
1667static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1668{
1669 struct rtl8169_private *tp = netdev_priv(dev);
1670
1671 tp->msg_enable = value;
1672}
1673
1674static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1675 "tx_packets",
1676 "rx_packets",
1677 "tx_errors",
1678 "rx_errors",
1679 "rx_missed",
1680 "align_errors",
1681 "tx_single_collisions",
1682 "tx_multi_collisions",
1683 "unicast",
1684 "broadcast",
1685 "multicast",
1686 "tx_aborted",
1687 "tx_underrun",
1688};
1689
1690static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1691{
1692 switch (sset) {
1693 case ETH_SS_STATS:
1694 return ARRAY_SIZE(rtl8169_gstrings);
1695 default:
1696 return -EOPNOTSUPP;
1697 }
1698}
1699
1700DECLARE_RTL_COND(rtl_counters_cond)
1701{
1702 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1703}
1704
1705static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1706{
1707 dma_addr_t paddr = tp->counters_phys_addr;
1708 u32 cmd;
1709
1710 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1711 RTL_R32(tp, CounterAddrHigh);
1712 cmd = (u64)paddr & DMA_BIT_MASK(32);
1713 RTL_W32(tp, CounterAddrLow, cmd);
1714 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1715
1716 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1717}
1718
1719static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1720{
1721 /*
1722 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1723 * tally counters.
1724 */
1725 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1726 return true;
1727
1728 return rtl8169_do_counters(tp, CounterReset);
1729}
1730
1731static bool rtl8169_update_counters(struct rtl8169_private *tp)
1732{
1733 /*
1734 * Some chips are unable to dump tally counters when the receiver
1735 * is disabled.
1736 */
1737 if ((RTL_R8(tp, ChipCmd) & CmdRxEnb) == 0)
1738 return true;
1739
1740 return rtl8169_do_counters(tp, CounterDump);
1741}
1742
1743static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1744{
1745 struct rtl8169_counters *counters = tp->counters;
1746 bool ret = false;
1747
1748 /*
1749 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1750 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1751 * reset by a power cycle, while the counter values collected by the
1752 * driver are reset at every driver unload/load cycle.
1753 *
1754 * To make sure the HW values returned by @get_stats64 match the SW
1755 * values, we collect the initial values at first open(*) and use them
1756 * as offsets to normalize the values returned by @get_stats64.
1757 *
1758 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1759 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1760 * set at open time by rtl_hw_start.
1761 */
1762
1763 if (tp->tc_offset.inited)
1764 return true;
1765
1766 /* If both, reset and update fail, propagate to caller. */
1767 if (rtl8169_reset_counters(tp))
1768 ret = true;
1769
1770 if (rtl8169_update_counters(tp))
1771 ret = true;
1772
1773 tp->tc_offset.tx_errors = counters->tx_errors;
1774 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1775 tp->tc_offset.tx_aborted = counters->tx_aborted;
1776 tp->tc_offset.inited = true;
1777
1778 return ret;
1779}
1780
1781static void rtl8169_get_ethtool_stats(struct net_device *dev,
1782 struct ethtool_stats *stats, u64 *data)
1783{
1784 struct rtl8169_private *tp = netdev_priv(dev);
1785 struct device *d = tp_to_dev(tp);
1786 struct rtl8169_counters *counters = tp->counters;
1787
1788 ASSERT_RTNL();
1789
1790 pm_runtime_get_noresume(d);
1791
1792 if (pm_runtime_active(d))
1793 rtl8169_update_counters(tp);
1794
1795 pm_runtime_put_noidle(d);
1796
1797 data[0] = le64_to_cpu(counters->tx_packets);
1798 data[1] = le64_to_cpu(counters->rx_packets);
1799 data[2] = le64_to_cpu(counters->tx_errors);
1800 data[3] = le32_to_cpu(counters->rx_errors);
1801 data[4] = le16_to_cpu(counters->rx_missed);
1802 data[5] = le16_to_cpu(counters->align_errors);
1803 data[6] = le32_to_cpu(counters->tx_one_collision);
1804 data[7] = le32_to_cpu(counters->tx_multi_collision);
1805 data[8] = le64_to_cpu(counters->rx_unicast);
1806 data[9] = le64_to_cpu(counters->rx_broadcast);
1807 data[10] = le32_to_cpu(counters->rx_multicast);
1808 data[11] = le16_to_cpu(counters->tx_aborted);
1809 data[12] = le16_to_cpu(counters->tx_underun);
1810}
1811
1812static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1813{
1814 switch(stringset) {
1815 case ETH_SS_STATS:
1816 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1817 break;
1818 }
1819}
1820
1821/*
1822 * Interrupt coalescing
1823 *
1824 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1825 * > 8169, 8168 and 810x line of chipsets
1826 *
1827 * 8169, 8168, and 8136(810x) serial chipsets support it.
1828 *
1829 * > 2 - the Tx timer unit at gigabit speed
1830 *
1831 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1832 * (0xe0) bit 1 and bit 0.
1833 *
1834 * For 8169
1835 * bit[1:0] \ speed 1000M 100M 10M
1836 * 0 0 320ns 2.56us 40.96us
1837 * 0 1 2.56us 20.48us 327.7us
1838 * 1 0 5.12us 40.96us 655.4us
1839 * 1 1 10.24us 81.92us 1.31ms
1840 *
1841 * For the other
1842 * bit[1:0] \ speed 1000M 100M 10M
1843 * 0 0 5us 2.56us 40.96us
1844 * 0 1 40us 20.48us 327.7us
1845 * 1 0 80us 40.96us 655.4us
1846 * 1 1 160us 81.92us 1.31ms
1847 */
1848
1849/* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1850struct rtl_coalesce_scale {
1851 /* Rx / Tx */
1852 u32 nsecs[2];
1853};
1854
1855/* rx/tx scale factors for all CPlusCmd[0:1] cases */
1856struct rtl_coalesce_info {
1857 u32 speed;
1858 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1859};
1860
1861/* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1862#define rxtx_x1822(r, t) { \
1863 {{(r), (t)}}, \
1864 {{(r)*8, (t)*8}}, \
1865 {{(r)*8*2, (t)*8*2}}, \
1866 {{(r)*8*2*2, (t)*8*2*2}}, \
1867}
1868static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1869 /* speed delays: rx00 tx00 */
1870 { SPEED_10, rxtx_x1822(40960, 40960) },
1871 { SPEED_100, rxtx_x1822( 2560, 2560) },
1872 { SPEED_1000, rxtx_x1822( 320, 320) },
1873 { 0 },
1874};
1875
1876static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1877 /* speed delays: rx00 tx00 */
1878 { SPEED_10, rxtx_x1822(40960, 40960) },
1879 { SPEED_100, rxtx_x1822( 2560, 2560) },
1880 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1881 { 0 },
1882};
1883#undef rxtx_x1822
1884
1885/* get rx/tx scale vector corresponding to current speed */
1886static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1887{
1888 struct rtl8169_private *tp = netdev_priv(dev);
1889 struct ethtool_link_ksettings ecmd;
1890 const struct rtl_coalesce_info *ci;
1891 int rc;
1892
1893 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1894 if (rc < 0)
1895 return ERR_PTR(rc);
1896
1897 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1898 if (ecmd.base.speed == ci->speed) {
1899 return ci;
1900 }
1901 }
1902
1903 return ERR_PTR(-ELNRNG);
1904}
1905
1906static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1907{
1908 struct rtl8169_private *tp = netdev_priv(dev);
1909 const struct rtl_coalesce_info *ci;
1910 const struct rtl_coalesce_scale *scale;
1911 struct {
1912 u32 *max_frames;
1913 u32 *usecs;
1914 } coal_settings [] = {
1915 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1916 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1917 }, *p = coal_settings;
1918 int i;
1919 u16 w;
1920
1921 memset(ec, 0, sizeof(*ec));
1922
1923 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1924 ci = rtl_coalesce_info(dev);
1925 if (IS_ERR(ci))
1926 return PTR_ERR(ci);
1927
1928 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1929
1930 /* read IntrMitigate and adjust according to scale */
1931 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1932 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1933 w >>= RTL_COALESCE_SHIFT;
1934 *p->usecs = w & RTL_COALESCE_MASK;
1935 }
1936
1937 for (i = 0; i < 2; i++) {
1938 p = coal_settings + i;
1939 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1940
1941 /*
1942 * ethtool_coalesce says it is illegal to set both usecs and
1943 * max_frames to 0.
1944 */
1945 if (!*p->usecs && !*p->max_frames)
1946 *p->max_frames = 1;
1947 }
1948
1949 return 0;
1950}
1951
1952/* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1953static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1954 struct net_device *dev, u32 nsec, u16 *cp01)
1955{
1956 const struct rtl_coalesce_info *ci;
1957 u16 i;
1958
1959 ci = rtl_coalesce_info(dev);
1960 if (IS_ERR(ci))
1961 return ERR_CAST(ci);
1962
1963 for (i = 0; i < 4; i++) {
1964 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1965 ci->scalev[i].nsecs[1]);
1966 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1967 *cp01 = i;
1968 return &ci->scalev[i];
1969 }
1970 }
1971
1972 return ERR_PTR(-EINVAL);
1973}
1974
1975static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1976{
1977 struct rtl8169_private *tp = netdev_priv(dev);
1978 const struct rtl_coalesce_scale *scale;
1979 struct {
1980 u32 frames;
1981 u32 usecs;
1982 } coal_settings [] = {
1983 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1984 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1985 }, *p = coal_settings;
1986 u16 w = 0, cp01;
1987 int i;
1988
1989 scale = rtl_coalesce_choose_scale(dev,
1990 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1991 if (IS_ERR(scale))
1992 return PTR_ERR(scale);
1993
1994 for (i = 0; i < 2; i++, p++) {
1995 u32 units;
1996
1997 /*
1998 * accept max_frames=1 we returned in rtl_get_coalesce.
1999 * accept it not only when usecs=0 because of e.g. the following scenario:
2000 *
2001 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2002 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2003 * - then user does `ethtool -C eth0 rx-usecs 100`
2004 *
2005 * since ethtool sends to kernel whole ethtool_coalesce
2006 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2007 * we'll reject it below in `frames % 4 != 0`.
2008 */
2009 if (p->frames == 1) {
2010 p->frames = 0;
2011 }
2012
2013 units = p->usecs * 1000 / scale->nsecs[i];
2014 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2015 return -EINVAL;
2016
2017 w <<= RTL_COALESCE_SHIFT;
2018 w |= units;
2019 w <<= RTL_COALESCE_SHIFT;
2020 w |= p->frames >> 2;
2021 }
2022
2023 rtl_lock_work(tp);
2024
2025 RTL_W16(tp, IntrMitigate, swab16(w));
2026
2027 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2028 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2029 RTL_R16(tp, CPlusCmd);
2030
2031 rtl_unlock_work(tp);
2032
2033 return 0;
2034}
2035
2036static const struct ethtool_ops rtl8169_ethtool_ops = {
2037 .get_drvinfo = rtl8169_get_drvinfo,
2038 .get_regs_len = rtl8169_get_regs_len,
2039 .get_link = ethtool_op_get_link,
2040 .get_coalesce = rtl_get_coalesce,
2041 .set_coalesce = rtl_set_coalesce,
2042 .get_msglevel = rtl8169_get_msglevel,
2043 .set_msglevel = rtl8169_set_msglevel,
2044 .get_regs = rtl8169_get_regs,
2045 .get_wol = rtl8169_get_wol,
2046 .set_wol = rtl8169_set_wol,
2047 .get_strings = rtl8169_get_strings,
2048 .get_sset_count = rtl8169_get_sset_count,
2049 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2050 .get_ts_info = ethtool_op_get_ts_info,
2051 .nway_reset = phy_ethtool_nway_reset,
2052 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2053 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2054};
2055
2056static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2057 u8 default_version)
2058{
2059 /*
2060 * The driver currently handles the 8168Bf and the 8168Be identically
2061 * but they can be identified more specifically through the test below
2062 * if needed:
2063 *
2064 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2065 *
2066 * Same thing for the 8101Eb and the 8101Ec:
2067 *
2068 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2069 */
2070 static const struct rtl_mac_info {
2071 u32 mask;
2072 u32 val;
2073 int mac_version;
2074 } mac_info[] = {
2075 /* 8168EP family. */
2076 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2077 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2078 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2079
2080 /* 8168H family. */
2081 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2082 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2083
2084 /* 8168G family. */
2085 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2086 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2087 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2088 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2089
2090 /* 8168F family. */
2091 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2092 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2093 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2094
2095 /* 8168E family. */
2096 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2097 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2098 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2099
2100 /* 8168D family. */
2101 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2102 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2103
2104 /* 8168DP family. */
2105 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2106 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2107 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2108
2109 /* 8168C family. */
2110 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2111 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2112 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2113 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2114 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2115 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2116 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2117
2118 /* 8168B family. */
2119 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2120 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2121 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2122
2123 /* 8101 family. */
2124 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2125 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2126 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2127 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2128 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2129 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2130 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2131 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2132 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2133 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2134 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2135 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2136 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2138 /* FIXME: where did these entries come from ? -- FR */
2139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2141
2142 /* 8110 family. */
2143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2149
2150 /* Catch-all */
2151 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2152 };
2153 const struct rtl_mac_info *p = mac_info;
2154 u32 reg;
2155
2156 reg = RTL_R32(tp, TxConfig);
2157 while ((reg & p->mask) != p->val)
2158 p++;
2159 tp->mac_version = p->mac_version;
2160
2161 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2162 dev_notice(tp_to_dev(tp),
2163 "unknown MAC, using family default\n");
2164 tp->mac_version = default_version;
2165 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2166 tp->mac_version = tp->supports_gmii ?
2167 RTL_GIGA_MAC_VER_42 :
2168 RTL_GIGA_MAC_VER_43;
2169 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2170 tp->mac_version = tp->supports_gmii ?
2171 RTL_GIGA_MAC_VER_45 :
2172 RTL_GIGA_MAC_VER_47;
2173 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2174 tp->mac_version = tp->supports_gmii ?
2175 RTL_GIGA_MAC_VER_46 :
2176 RTL_GIGA_MAC_VER_48;
2177 }
2178}
2179
2180static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2181{
2182 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2183}
2184
2185struct phy_reg {
2186 u16 reg;
2187 u16 val;
2188};
2189
2190static void rtl_writephy_batch(struct rtl8169_private *tp,
2191 const struct phy_reg *regs, int len)
2192{
2193 while (len-- > 0) {
2194 rtl_writephy(tp, regs->reg, regs->val);
2195 regs++;
2196 }
2197}
2198
2199#define PHY_READ 0x00000000
2200#define PHY_DATA_OR 0x10000000
2201#define PHY_DATA_AND 0x20000000
2202#define PHY_BJMPN 0x30000000
2203#define PHY_MDIO_CHG 0x40000000
2204#define PHY_CLEAR_READCOUNT 0x70000000
2205#define PHY_WRITE 0x80000000
2206#define PHY_READCOUNT_EQ_SKIP 0x90000000
2207#define PHY_COMP_EQ_SKIPN 0xa0000000
2208#define PHY_COMP_NEQ_SKIPN 0xb0000000
2209#define PHY_WRITE_PREVIOUS 0xc0000000
2210#define PHY_SKIPN 0xd0000000
2211#define PHY_DELAY_MS 0xe0000000
2212
2213struct fw_info {
2214 u32 magic;
2215 char version[RTL_VER_SIZE];
2216 __le32 fw_start;
2217 __le32 fw_len;
2218 u8 chksum;
2219} __packed;
2220
2221#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2222
2223static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2224{
2225 const struct firmware *fw = rtl_fw->fw;
2226 struct fw_info *fw_info = (struct fw_info *)fw->data;
2227 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2228 char *version = rtl_fw->version;
2229 bool rc = false;
2230
2231 if (fw->size < FW_OPCODE_SIZE)
2232 goto out;
2233
2234 if (!fw_info->magic) {
2235 size_t i, size, start;
2236 u8 checksum = 0;
2237
2238 if (fw->size < sizeof(*fw_info))
2239 goto out;
2240
2241 for (i = 0; i < fw->size; i++)
2242 checksum += fw->data[i];
2243 if (checksum != 0)
2244 goto out;
2245
2246 start = le32_to_cpu(fw_info->fw_start);
2247 if (start > fw->size)
2248 goto out;
2249
2250 size = le32_to_cpu(fw_info->fw_len);
2251 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2252 goto out;
2253
2254 memcpy(version, fw_info->version, RTL_VER_SIZE);
2255
2256 pa->code = (__le32 *)(fw->data + start);
2257 pa->size = size;
2258 } else {
2259 if (fw->size % FW_OPCODE_SIZE)
2260 goto out;
2261
2262 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2263
2264 pa->code = (__le32 *)fw->data;
2265 pa->size = fw->size / FW_OPCODE_SIZE;
2266 }
2267 version[RTL_VER_SIZE - 1] = 0;
2268
2269 rc = true;
2270out:
2271 return rc;
2272}
2273
2274static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2275 struct rtl_fw_phy_action *pa)
2276{
2277 bool rc = false;
2278 size_t index;
2279
2280 for (index = 0; index < pa->size; index++) {
2281 u32 action = le32_to_cpu(pa->code[index]);
2282 u32 regno = (action & 0x0fff0000) >> 16;
2283
2284 switch(action & 0xf0000000) {
2285 case PHY_READ:
2286 case PHY_DATA_OR:
2287 case PHY_DATA_AND:
2288 case PHY_MDIO_CHG:
2289 case PHY_CLEAR_READCOUNT:
2290 case PHY_WRITE:
2291 case PHY_WRITE_PREVIOUS:
2292 case PHY_DELAY_MS:
2293 break;
2294
2295 case PHY_BJMPN:
2296 if (regno > index) {
2297 netif_err(tp, ifup, tp->dev,
2298 "Out of range of firmware\n");
2299 goto out;
2300 }
2301 break;
2302 case PHY_READCOUNT_EQ_SKIP:
2303 if (index + 2 >= pa->size) {
2304 netif_err(tp, ifup, tp->dev,
2305 "Out of range of firmware\n");
2306 goto out;
2307 }
2308 break;
2309 case PHY_COMP_EQ_SKIPN:
2310 case PHY_COMP_NEQ_SKIPN:
2311 case PHY_SKIPN:
2312 if (index + 1 + regno >= pa->size) {
2313 netif_err(tp, ifup, tp->dev,
2314 "Out of range of firmware\n");
2315 goto out;
2316 }
2317 break;
2318
2319 default:
2320 netif_err(tp, ifup, tp->dev,
2321 "Invalid action 0x%08x\n", action);
2322 goto out;
2323 }
2324 }
2325 rc = true;
2326out:
2327 return rc;
2328}
2329
2330static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2331{
2332 struct net_device *dev = tp->dev;
2333 int rc = -EINVAL;
2334
2335 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2336 netif_err(tp, ifup, dev, "invalid firmware\n");
2337 goto out;
2338 }
2339
2340 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2341 rc = 0;
2342out:
2343 return rc;
2344}
2345
2346static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2347{
2348 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2349 struct mdio_ops org, *ops = &tp->mdio_ops;
2350 u32 predata, count;
2351 size_t index;
2352
2353 predata = count = 0;
2354 org.write = ops->write;
2355 org.read = ops->read;
2356
2357 for (index = 0; index < pa->size; ) {
2358 u32 action = le32_to_cpu(pa->code[index]);
2359 u32 data = action & 0x0000ffff;
2360 u32 regno = (action & 0x0fff0000) >> 16;
2361
2362 if (!action)
2363 break;
2364
2365 switch(action & 0xf0000000) {
2366 case PHY_READ:
2367 predata = rtl_readphy(tp, regno);
2368 count++;
2369 index++;
2370 break;
2371 case PHY_DATA_OR:
2372 predata |= data;
2373 index++;
2374 break;
2375 case PHY_DATA_AND:
2376 predata &= data;
2377 index++;
2378 break;
2379 case PHY_BJMPN:
2380 index -= regno;
2381 break;
2382 case PHY_MDIO_CHG:
2383 if (data == 0) {
2384 ops->write = org.write;
2385 ops->read = org.read;
2386 } else if (data == 1) {
2387 ops->write = mac_mcu_write;
2388 ops->read = mac_mcu_read;
2389 }
2390
2391 index++;
2392 break;
2393 case PHY_CLEAR_READCOUNT:
2394 count = 0;
2395 index++;
2396 break;
2397 case PHY_WRITE:
2398 rtl_writephy(tp, regno, data);
2399 index++;
2400 break;
2401 case PHY_READCOUNT_EQ_SKIP:
2402 index += (count == data) ? 2 : 1;
2403 break;
2404 case PHY_COMP_EQ_SKIPN:
2405 if (predata == data)
2406 index += regno;
2407 index++;
2408 break;
2409 case PHY_COMP_NEQ_SKIPN:
2410 if (predata != data)
2411 index += regno;
2412 index++;
2413 break;
2414 case PHY_WRITE_PREVIOUS:
2415 rtl_writephy(tp, regno, predata);
2416 index++;
2417 break;
2418 case PHY_SKIPN:
2419 index += regno + 1;
2420 break;
2421 case PHY_DELAY_MS:
2422 mdelay(data);
2423 index++;
2424 break;
2425
2426 default:
2427 BUG();
2428 }
2429 }
2430
2431 ops->write = org.write;
2432 ops->read = org.read;
2433}
2434
2435static void rtl_release_firmware(struct rtl8169_private *tp)
2436{
2437 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2438 release_firmware(tp->rtl_fw->fw);
2439 kfree(tp->rtl_fw);
2440 }
2441 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2442}
2443
2444static void rtl_apply_firmware(struct rtl8169_private *tp)
2445{
2446 struct rtl_fw *rtl_fw = tp->rtl_fw;
2447
2448 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2449 if (!IS_ERR_OR_NULL(rtl_fw))
2450 rtl_phy_write_fw(tp, rtl_fw);
2451}
2452
2453static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2454{
2455 if (rtl_readphy(tp, reg) != val)
2456 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2457 else
2458 rtl_apply_firmware(tp);
2459}
2460
2461static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2462{
2463 static const struct phy_reg phy_reg_init[] = {
2464 { 0x1f, 0x0001 },
2465 { 0x06, 0x006e },
2466 { 0x08, 0x0708 },
2467 { 0x15, 0x4000 },
2468 { 0x18, 0x65c7 },
2469
2470 { 0x1f, 0x0001 },
2471 { 0x03, 0x00a1 },
2472 { 0x02, 0x0008 },
2473 { 0x01, 0x0120 },
2474 { 0x00, 0x1000 },
2475 { 0x04, 0x0800 },
2476 { 0x04, 0x0000 },
2477
2478 { 0x03, 0xff41 },
2479 { 0x02, 0xdf60 },
2480 { 0x01, 0x0140 },
2481 { 0x00, 0x0077 },
2482 { 0x04, 0x7800 },
2483 { 0x04, 0x7000 },
2484
2485 { 0x03, 0x802f },
2486 { 0x02, 0x4f02 },
2487 { 0x01, 0x0409 },
2488 { 0x00, 0xf0f9 },
2489 { 0x04, 0x9800 },
2490 { 0x04, 0x9000 },
2491
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0xff95 },
2495 { 0x00, 0xba00 },
2496 { 0x04, 0xa800 },
2497 { 0x04, 0xa000 },
2498
2499 { 0x03, 0xff41 },
2500 { 0x02, 0xdf20 },
2501 { 0x01, 0x0140 },
2502 { 0x00, 0x00bb },
2503 { 0x04, 0xb800 },
2504 { 0x04, 0xb000 },
2505
2506 { 0x03, 0xdf41 },
2507 { 0x02, 0xdc60 },
2508 { 0x01, 0x6340 },
2509 { 0x00, 0x007d },
2510 { 0x04, 0xd800 },
2511 { 0x04, 0xd000 },
2512
2513 { 0x03, 0xdf01 },
2514 { 0x02, 0xdf20 },
2515 { 0x01, 0x100a },
2516 { 0x00, 0xa0ff },
2517 { 0x04, 0xf800 },
2518 { 0x04, 0xf000 },
2519
2520 { 0x1f, 0x0000 },
2521 { 0x0b, 0x0000 },
2522 { 0x00, 0x9200 }
2523 };
2524
2525 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2526}
2527
2528static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2529{
2530 static const struct phy_reg phy_reg_init[] = {
2531 { 0x1f, 0x0002 },
2532 { 0x01, 0x90d0 },
2533 { 0x1f, 0x0000 }
2534 };
2535
2536 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2537}
2538
2539static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2540{
2541 struct pci_dev *pdev = tp->pci_dev;
2542
2543 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2544 (pdev->subsystem_device != 0xe000))
2545 return;
2546
2547 rtl_writephy(tp, 0x1f, 0x0001);
2548 rtl_writephy(tp, 0x10, 0xf01b);
2549 rtl_writephy(tp, 0x1f, 0x0000);
2550}
2551
2552static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2553{
2554 static const struct phy_reg phy_reg_init[] = {
2555 { 0x1f, 0x0001 },
2556 { 0x04, 0x0000 },
2557 { 0x03, 0x00a1 },
2558 { 0x02, 0x0008 },
2559 { 0x01, 0x0120 },
2560 { 0x00, 0x1000 },
2561 { 0x04, 0x0800 },
2562 { 0x04, 0x9000 },
2563 { 0x03, 0x802f },
2564 { 0x02, 0x4f02 },
2565 { 0x01, 0x0409 },
2566 { 0x00, 0xf099 },
2567 { 0x04, 0x9800 },
2568 { 0x04, 0xa000 },
2569 { 0x03, 0xdf01 },
2570 { 0x02, 0xdf20 },
2571 { 0x01, 0xff95 },
2572 { 0x00, 0xba00 },
2573 { 0x04, 0xa800 },
2574 { 0x04, 0xf000 },
2575 { 0x03, 0xdf01 },
2576 { 0x02, 0xdf20 },
2577 { 0x01, 0x101a },
2578 { 0x00, 0xa0ff },
2579 { 0x04, 0xf800 },
2580 { 0x04, 0x0000 },
2581 { 0x1f, 0x0000 },
2582
2583 { 0x1f, 0x0001 },
2584 { 0x10, 0xf41b },
2585 { 0x14, 0xfb54 },
2586 { 0x18, 0xf5c7 },
2587 { 0x1f, 0x0000 },
2588
2589 { 0x1f, 0x0001 },
2590 { 0x17, 0x0cc0 },
2591 { 0x1f, 0x0000 }
2592 };
2593
2594 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2595
2596 rtl8169scd_hw_phy_config_quirk(tp);
2597}
2598
2599static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2600{
2601 static const struct phy_reg phy_reg_init[] = {
2602 { 0x1f, 0x0001 },
2603 { 0x04, 0x0000 },
2604 { 0x03, 0x00a1 },
2605 { 0x02, 0x0008 },
2606 { 0x01, 0x0120 },
2607 { 0x00, 0x1000 },
2608 { 0x04, 0x0800 },
2609 { 0x04, 0x9000 },
2610 { 0x03, 0x802f },
2611 { 0x02, 0x4f02 },
2612 { 0x01, 0x0409 },
2613 { 0x00, 0xf099 },
2614 { 0x04, 0x9800 },
2615 { 0x04, 0xa000 },
2616 { 0x03, 0xdf01 },
2617 { 0x02, 0xdf20 },
2618 { 0x01, 0xff95 },
2619 { 0x00, 0xba00 },
2620 { 0x04, 0xa800 },
2621 { 0x04, 0xf000 },
2622 { 0x03, 0xdf01 },
2623 { 0x02, 0xdf20 },
2624 { 0x01, 0x101a },
2625 { 0x00, 0xa0ff },
2626 { 0x04, 0xf800 },
2627 { 0x04, 0x0000 },
2628 { 0x1f, 0x0000 },
2629
2630 { 0x1f, 0x0001 },
2631 { 0x0b, 0x8480 },
2632 { 0x1f, 0x0000 },
2633
2634 { 0x1f, 0x0001 },
2635 { 0x18, 0x67c7 },
2636 { 0x04, 0x2000 },
2637 { 0x03, 0x002f },
2638 { 0x02, 0x4360 },
2639 { 0x01, 0x0109 },
2640 { 0x00, 0x3022 },
2641 { 0x04, 0x2800 },
2642 { 0x1f, 0x0000 },
2643
2644 { 0x1f, 0x0001 },
2645 { 0x17, 0x0cc0 },
2646 { 0x1f, 0x0000 }
2647 };
2648
2649 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2650}
2651
2652static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2653{
2654 static const struct phy_reg phy_reg_init[] = {
2655 { 0x10, 0xf41b },
2656 { 0x1f, 0x0000 }
2657 };
2658
2659 rtl_writephy(tp, 0x1f, 0x0001);
2660 rtl_patchphy(tp, 0x16, 1 << 0);
2661
2662 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2663}
2664
2665static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2666{
2667 static const struct phy_reg phy_reg_init[] = {
2668 { 0x1f, 0x0001 },
2669 { 0x10, 0xf41b },
2670 { 0x1f, 0x0000 }
2671 };
2672
2673 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2674}
2675
2676static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2677{
2678 static const struct phy_reg phy_reg_init[] = {
2679 { 0x1f, 0x0000 },
2680 { 0x1d, 0x0f00 },
2681 { 0x1f, 0x0002 },
2682 { 0x0c, 0x1ec8 },
2683 { 0x1f, 0x0000 }
2684 };
2685
2686 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2687}
2688
2689static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2690{
2691 static const struct phy_reg phy_reg_init[] = {
2692 { 0x1f, 0x0001 },
2693 { 0x1d, 0x3d98 },
2694 { 0x1f, 0x0000 }
2695 };
2696
2697 rtl_writephy(tp, 0x1f, 0x0000);
2698 rtl_patchphy(tp, 0x14, 1 << 5);
2699 rtl_patchphy(tp, 0x0d, 1 << 5);
2700
2701 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2702}
2703
2704static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2705{
2706 static const struct phy_reg phy_reg_init[] = {
2707 { 0x1f, 0x0001 },
2708 { 0x12, 0x2300 },
2709 { 0x1f, 0x0002 },
2710 { 0x00, 0x88d4 },
2711 { 0x01, 0x82b1 },
2712 { 0x03, 0x7002 },
2713 { 0x08, 0x9e30 },
2714 { 0x09, 0x01f0 },
2715 { 0x0a, 0x5500 },
2716 { 0x0c, 0x00c8 },
2717 { 0x1f, 0x0003 },
2718 { 0x12, 0xc096 },
2719 { 0x16, 0x000a },
2720 { 0x1f, 0x0000 },
2721 { 0x1f, 0x0000 },
2722 { 0x09, 0x2000 },
2723 { 0x09, 0x0000 }
2724 };
2725
2726 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2727
2728 rtl_patchphy(tp, 0x14, 1 << 5);
2729 rtl_patchphy(tp, 0x0d, 1 << 5);
2730 rtl_writephy(tp, 0x1f, 0x0000);
2731}
2732
2733static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2734{
2735 static const struct phy_reg phy_reg_init[] = {
2736 { 0x1f, 0x0001 },
2737 { 0x12, 0x2300 },
2738 { 0x03, 0x802f },
2739 { 0x02, 0x4f02 },
2740 { 0x01, 0x0409 },
2741 { 0x00, 0xf099 },
2742 { 0x04, 0x9800 },
2743 { 0x04, 0x9000 },
2744 { 0x1d, 0x3d98 },
2745 { 0x1f, 0x0002 },
2746 { 0x0c, 0x7eb8 },
2747 { 0x06, 0x0761 },
2748 { 0x1f, 0x0003 },
2749 { 0x16, 0x0f0a },
2750 { 0x1f, 0x0000 }
2751 };
2752
2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2754
2755 rtl_patchphy(tp, 0x16, 1 << 0);
2756 rtl_patchphy(tp, 0x14, 1 << 5);
2757 rtl_patchphy(tp, 0x0d, 1 << 5);
2758 rtl_writephy(tp, 0x1f, 0x0000);
2759}
2760
2761static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2762{
2763 static const struct phy_reg phy_reg_init[] = {
2764 { 0x1f, 0x0001 },
2765 { 0x12, 0x2300 },
2766 { 0x1d, 0x3d98 },
2767 { 0x1f, 0x0002 },
2768 { 0x0c, 0x7eb8 },
2769 { 0x06, 0x5461 },
2770 { 0x1f, 0x0003 },
2771 { 0x16, 0x0f0a },
2772 { 0x1f, 0x0000 }
2773 };
2774
2775 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2776
2777 rtl_patchphy(tp, 0x16, 1 << 0);
2778 rtl_patchphy(tp, 0x14, 1 << 5);
2779 rtl_patchphy(tp, 0x0d, 1 << 5);
2780 rtl_writephy(tp, 0x1f, 0x0000);
2781}
2782
2783static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2784{
2785 rtl8168c_3_hw_phy_config(tp);
2786}
2787
2788static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2789{
2790 static const struct phy_reg phy_reg_init_0[] = {
2791 /* Channel Estimation */
2792 { 0x1f, 0x0001 },
2793 { 0x06, 0x4064 },
2794 { 0x07, 0x2863 },
2795 { 0x08, 0x059c },
2796 { 0x09, 0x26b4 },
2797 { 0x0a, 0x6a19 },
2798 { 0x0b, 0xdcc8 },
2799 { 0x10, 0xf06d },
2800 { 0x14, 0x7f68 },
2801 { 0x18, 0x7fd9 },
2802 { 0x1c, 0xf0ff },
2803 { 0x1d, 0x3d9c },
2804 { 0x1f, 0x0003 },
2805 { 0x12, 0xf49f },
2806 { 0x13, 0x070b },
2807 { 0x1a, 0x05ad },
2808 { 0x14, 0x94c0 },
2809
2810 /*
2811 * Tx Error Issue
2812 * Enhance line driver power
2813 */
2814 { 0x1f, 0x0002 },
2815 { 0x06, 0x5561 },
2816 { 0x1f, 0x0005 },
2817 { 0x05, 0x8332 },
2818 { 0x06, 0x5561 },
2819
2820 /*
2821 * Can not link to 1Gbps with bad cable
2822 * Decrease SNR threshold form 21.07dB to 19.04dB
2823 */
2824 { 0x1f, 0x0001 },
2825 { 0x17, 0x0cc0 },
2826
2827 { 0x1f, 0x0000 },
2828 { 0x0d, 0xf880 }
2829 };
2830
2831 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2832
2833 /*
2834 * Rx Error Issue
2835 * Fine Tune Switching regulator parameter
2836 */
2837 rtl_writephy(tp, 0x1f, 0x0002);
2838 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2839 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2840
2841 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2842 static const struct phy_reg phy_reg_init[] = {
2843 { 0x1f, 0x0002 },
2844 { 0x05, 0x669a },
2845 { 0x1f, 0x0005 },
2846 { 0x05, 0x8330 },
2847 { 0x06, 0x669a },
2848 { 0x1f, 0x0002 }
2849 };
2850 int val;
2851
2852 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2853
2854 val = rtl_readphy(tp, 0x0d);
2855
2856 if ((val & 0x00ff) != 0x006c) {
2857 static const u32 set[] = {
2858 0x0065, 0x0066, 0x0067, 0x0068,
2859 0x0069, 0x006a, 0x006b, 0x006c
2860 };
2861 int i;
2862
2863 rtl_writephy(tp, 0x1f, 0x0002);
2864
2865 val &= 0xff00;
2866 for (i = 0; i < ARRAY_SIZE(set); i++)
2867 rtl_writephy(tp, 0x0d, val | set[i]);
2868 }
2869 } else {
2870 static const struct phy_reg phy_reg_init[] = {
2871 { 0x1f, 0x0002 },
2872 { 0x05, 0x6662 },
2873 { 0x1f, 0x0005 },
2874 { 0x05, 0x8330 },
2875 { 0x06, 0x6662 }
2876 };
2877
2878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2879 }
2880
2881 /* RSET couple improve */
2882 rtl_writephy(tp, 0x1f, 0x0002);
2883 rtl_patchphy(tp, 0x0d, 0x0300);
2884 rtl_patchphy(tp, 0x0f, 0x0010);
2885
2886 /* Fine tune PLL performance */
2887 rtl_writephy(tp, 0x1f, 0x0002);
2888 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2889 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2890
2891 rtl_writephy(tp, 0x1f, 0x0005);
2892 rtl_writephy(tp, 0x05, 0x001b);
2893
2894 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2895
2896 rtl_writephy(tp, 0x1f, 0x0000);
2897}
2898
2899static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2900{
2901 static const struct phy_reg phy_reg_init_0[] = {
2902 /* Channel Estimation */
2903 { 0x1f, 0x0001 },
2904 { 0x06, 0x4064 },
2905 { 0x07, 0x2863 },
2906 { 0x08, 0x059c },
2907 { 0x09, 0x26b4 },
2908 { 0x0a, 0x6a19 },
2909 { 0x0b, 0xdcc8 },
2910 { 0x10, 0xf06d },
2911 { 0x14, 0x7f68 },
2912 { 0x18, 0x7fd9 },
2913 { 0x1c, 0xf0ff },
2914 { 0x1d, 0x3d9c },
2915 { 0x1f, 0x0003 },
2916 { 0x12, 0xf49f },
2917 { 0x13, 0x070b },
2918 { 0x1a, 0x05ad },
2919 { 0x14, 0x94c0 },
2920
2921 /*
2922 * Tx Error Issue
2923 * Enhance line driver power
2924 */
2925 { 0x1f, 0x0002 },
2926 { 0x06, 0x5561 },
2927 { 0x1f, 0x0005 },
2928 { 0x05, 0x8332 },
2929 { 0x06, 0x5561 },
2930
2931 /*
2932 * Can not link to 1Gbps with bad cable
2933 * Decrease SNR threshold form 21.07dB to 19.04dB
2934 */
2935 { 0x1f, 0x0001 },
2936 { 0x17, 0x0cc0 },
2937
2938 { 0x1f, 0x0000 },
2939 { 0x0d, 0xf880 }
2940 };
2941
2942 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2943
2944 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2945 static const struct phy_reg phy_reg_init[] = {
2946 { 0x1f, 0x0002 },
2947 { 0x05, 0x669a },
2948 { 0x1f, 0x0005 },
2949 { 0x05, 0x8330 },
2950 { 0x06, 0x669a },
2951
2952 { 0x1f, 0x0002 }
2953 };
2954 int val;
2955
2956 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2957
2958 val = rtl_readphy(tp, 0x0d);
2959 if ((val & 0x00ff) != 0x006c) {
2960 static const u32 set[] = {
2961 0x0065, 0x0066, 0x0067, 0x0068,
2962 0x0069, 0x006a, 0x006b, 0x006c
2963 };
2964 int i;
2965
2966 rtl_writephy(tp, 0x1f, 0x0002);
2967
2968 val &= 0xff00;
2969 for (i = 0; i < ARRAY_SIZE(set); i++)
2970 rtl_writephy(tp, 0x0d, val | set[i]);
2971 }
2972 } else {
2973 static const struct phy_reg phy_reg_init[] = {
2974 { 0x1f, 0x0002 },
2975 { 0x05, 0x2642 },
2976 { 0x1f, 0x0005 },
2977 { 0x05, 0x8330 },
2978 { 0x06, 0x2642 }
2979 };
2980
2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2982 }
2983
2984 /* Fine tune PLL performance */
2985 rtl_writephy(tp, 0x1f, 0x0002);
2986 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2987 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2988
2989 /* Switching regulator Slew rate */
2990 rtl_writephy(tp, 0x1f, 0x0002);
2991 rtl_patchphy(tp, 0x0f, 0x0017);
2992
2993 rtl_writephy(tp, 0x1f, 0x0005);
2994 rtl_writephy(tp, 0x05, 0x001b);
2995
2996 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2997
2998 rtl_writephy(tp, 0x1f, 0x0000);
2999}
3000
3001static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3002{
3003 static const struct phy_reg phy_reg_init[] = {
3004 { 0x1f, 0x0002 },
3005 { 0x10, 0x0008 },
3006 { 0x0d, 0x006c },
3007
3008 { 0x1f, 0x0000 },
3009 { 0x0d, 0xf880 },
3010
3011 { 0x1f, 0x0001 },
3012 { 0x17, 0x0cc0 },
3013
3014 { 0x1f, 0x0001 },
3015 { 0x0b, 0xa4d8 },
3016 { 0x09, 0x281c },
3017 { 0x07, 0x2883 },
3018 { 0x0a, 0x6b35 },
3019 { 0x1d, 0x3da4 },
3020 { 0x1c, 0xeffd },
3021 { 0x14, 0x7f52 },
3022 { 0x18, 0x7fc6 },
3023 { 0x08, 0x0601 },
3024 { 0x06, 0x4063 },
3025 { 0x10, 0xf074 },
3026 { 0x1f, 0x0003 },
3027 { 0x13, 0x0789 },
3028 { 0x12, 0xf4bd },
3029 { 0x1a, 0x04fd },
3030 { 0x14, 0x84b0 },
3031 { 0x1f, 0x0000 },
3032 { 0x00, 0x9200 },
3033
3034 { 0x1f, 0x0005 },
3035 { 0x01, 0x0340 },
3036 { 0x1f, 0x0001 },
3037 { 0x04, 0x4000 },
3038 { 0x03, 0x1d21 },
3039 { 0x02, 0x0c32 },
3040 { 0x01, 0x0200 },
3041 { 0x00, 0x5554 },
3042 { 0x04, 0x4800 },
3043 { 0x04, 0x4000 },
3044 { 0x04, 0xf000 },
3045 { 0x03, 0xdf01 },
3046 { 0x02, 0xdf20 },
3047 { 0x01, 0x101a },
3048 { 0x00, 0xa0ff },
3049 { 0x04, 0xf800 },
3050 { 0x04, 0xf000 },
3051 { 0x1f, 0x0000 },
3052
3053 { 0x1f, 0x0007 },
3054 { 0x1e, 0x0023 },
3055 { 0x16, 0x0000 },
3056 { 0x1f, 0x0000 }
3057 };
3058
3059 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3060}
3061
3062static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3063{
3064 static const struct phy_reg phy_reg_init[] = {
3065 { 0x1f, 0x0001 },
3066 { 0x17, 0x0cc0 },
3067
3068 { 0x1f, 0x0007 },
3069 { 0x1e, 0x002d },
3070 { 0x18, 0x0040 },
3071 { 0x1f, 0x0000 }
3072 };
3073
3074 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3075 rtl_patchphy(tp, 0x0d, 1 << 5);
3076}
3077
3078static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3079{
3080 static const struct phy_reg phy_reg_init[] = {
3081 /* Enable Delay cap */
3082 { 0x1f, 0x0005 },
3083 { 0x05, 0x8b80 },
3084 { 0x06, 0xc896 },
3085 { 0x1f, 0x0000 },
3086
3087 /* Channel estimation fine tune */
3088 { 0x1f, 0x0001 },
3089 { 0x0b, 0x6c20 },
3090 { 0x07, 0x2872 },
3091 { 0x1c, 0xefff },
3092 { 0x1f, 0x0003 },
3093 { 0x14, 0x6420 },
3094 { 0x1f, 0x0000 },
3095
3096 /* Update PFM & 10M TX idle timer */
3097 { 0x1f, 0x0007 },
3098 { 0x1e, 0x002f },
3099 { 0x15, 0x1919 },
3100 { 0x1f, 0x0000 },
3101
3102 { 0x1f, 0x0007 },
3103 { 0x1e, 0x00ac },
3104 { 0x18, 0x0006 },
3105 { 0x1f, 0x0000 }
3106 };
3107
3108 rtl_apply_firmware(tp);
3109
3110 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3111
3112 /* DCO enable for 10M IDLE Power */
3113 rtl_writephy(tp, 0x1f, 0x0007);
3114 rtl_writephy(tp, 0x1e, 0x0023);
3115 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3116 rtl_writephy(tp, 0x1f, 0x0000);
3117
3118 /* For impedance matching */
3119 rtl_writephy(tp, 0x1f, 0x0002);
3120 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3121 rtl_writephy(tp, 0x1f, 0x0000);
3122
3123 /* PHY auto speed down */
3124 rtl_writephy(tp, 0x1f, 0x0007);
3125 rtl_writephy(tp, 0x1e, 0x002d);
3126 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3127 rtl_writephy(tp, 0x1f, 0x0000);
3128 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3129
3130 rtl_writephy(tp, 0x1f, 0x0005);
3131 rtl_writephy(tp, 0x05, 0x8b86);
3132 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3133 rtl_writephy(tp, 0x1f, 0x0000);
3134
3135 rtl_writephy(tp, 0x1f, 0x0005);
3136 rtl_writephy(tp, 0x05, 0x8b85);
3137 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3138 rtl_writephy(tp, 0x1f, 0x0007);
3139 rtl_writephy(tp, 0x1e, 0x0020);
3140 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3141 rtl_writephy(tp, 0x1f, 0x0006);
3142 rtl_writephy(tp, 0x00, 0x5a00);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144 rtl_writephy(tp, 0x0d, 0x0007);
3145 rtl_writephy(tp, 0x0e, 0x003c);
3146 rtl_writephy(tp, 0x0d, 0x4007);
3147 rtl_writephy(tp, 0x0e, 0x0000);
3148 rtl_writephy(tp, 0x0d, 0x0000);
3149}
3150
3151static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3152{
3153 const u16 w[] = {
3154 addr[0] | (addr[1] << 8),
3155 addr[2] | (addr[3] << 8),
3156 addr[4] | (addr[5] << 8)
3157 };
3158 const struct exgmac_reg e[] = {
3159 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3160 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3161 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3162 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3163 };
3164
3165 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3166}
3167
3168static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3169{
3170 static const struct phy_reg phy_reg_init[] = {
3171 /* Enable Delay cap */
3172 { 0x1f, 0x0004 },
3173 { 0x1f, 0x0007 },
3174 { 0x1e, 0x00ac },
3175 { 0x18, 0x0006 },
3176 { 0x1f, 0x0002 },
3177 { 0x1f, 0x0000 },
3178 { 0x1f, 0x0000 },
3179
3180 /* Channel estimation fine tune */
3181 { 0x1f, 0x0003 },
3182 { 0x09, 0xa20f },
3183 { 0x1f, 0x0000 },
3184 { 0x1f, 0x0000 },
3185
3186 /* Green Setting */
3187 { 0x1f, 0x0005 },
3188 { 0x05, 0x8b5b },
3189 { 0x06, 0x9222 },
3190 { 0x05, 0x8b6d },
3191 { 0x06, 0x8000 },
3192 { 0x05, 0x8b76 },
3193 { 0x06, 0x8000 },
3194 { 0x1f, 0x0000 }
3195 };
3196
3197 rtl_apply_firmware(tp);
3198
3199 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3200
3201 /* For 4-corner performance improve */
3202 rtl_writephy(tp, 0x1f, 0x0005);
3203 rtl_writephy(tp, 0x05, 0x8b80);
3204 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3205 rtl_writephy(tp, 0x1f, 0x0000);
3206
3207 /* PHY auto speed down */
3208 rtl_writephy(tp, 0x1f, 0x0004);
3209 rtl_writephy(tp, 0x1f, 0x0007);
3210 rtl_writephy(tp, 0x1e, 0x002d);
3211 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3212 rtl_writephy(tp, 0x1f, 0x0002);
3213 rtl_writephy(tp, 0x1f, 0x0000);
3214 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3215
3216 /* improve 10M EEE waveform */
3217 rtl_writephy(tp, 0x1f, 0x0005);
3218 rtl_writephy(tp, 0x05, 0x8b86);
3219 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3220 rtl_writephy(tp, 0x1f, 0x0000);
3221
3222 /* Improve 2-pair detection performance */
3223 rtl_writephy(tp, 0x1f, 0x0005);
3224 rtl_writephy(tp, 0x05, 0x8b85);
3225 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3227
3228 /* EEE setting */
3229 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3230 rtl_writephy(tp, 0x1f, 0x0005);
3231 rtl_writephy(tp, 0x05, 0x8b85);
3232 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3233 rtl_writephy(tp, 0x1f, 0x0004);
3234 rtl_writephy(tp, 0x1f, 0x0007);
3235 rtl_writephy(tp, 0x1e, 0x0020);
3236 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3237 rtl_writephy(tp, 0x1f, 0x0002);
3238 rtl_writephy(tp, 0x1f, 0x0000);
3239 rtl_writephy(tp, 0x0d, 0x0007);
3240 rtl_writephy(tp, 0x0e, 0x003c);
3241 rtl_writephy(tp, 0x0d, 0x4007);
3242 rtl_writephy(tp, 0x0e, 0x0006);
3243 rtl_writephy(tp, 0x0d, 0x0000);
3244
3245 /* Green feature */
3246 rtl_writephy(tp, 0x1f, 0x0003);
3247 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3248 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3249 rtl_writephy(tp, 0x1f, 0x0000);
3250 rtl_writephy(tp, 0x1f, 0x0005);
3251 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3252 rtl_writephy(tp, 0x1f, 0x0000);
3253
3254 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3255 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3256}
3257
3258static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3259{
3260 /* For 4-corner performance improve */
3261 rtl_writephy(tp, 0x1f, 0x0005);
3262 rtl_writephy(tp, 0x05, 0x8b80);
3263 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3264 rtl_writephy(tp, 0x1f, 0x0000);
3265
3266 /* PHY auto speed down */
3267 rtl_writephy(tp, 0x1f, 0x0007);
3268 rtl_writephy(tp, 0x1e, 0x002d);
3269 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3270 rtl_writephy(tp, 0x1f, 0x0000);
3271 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3272
3273 /* Improve 10M EEE waveform */
3274 rtl_writephy(tp, 0x1f, 0x0005);
3275 rtl_writephy(tp, 0x05, 0x8b86);
3276 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3277 rtl_writephy(tp, 0x1f, 0x0000);
3278}
3279
3280static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3281{
3282 static const struct phy_reg phy_reg_init[] = {
3283 /* Channel estimation fine tune */
3284 { 0x1f, 0x0003 },
3285 { 0x09, 0xa20f },
3286 { 0x1f, 0x0000 },
3287
3288 /* Modify green table for giga & fnet */
3289 { 0x1f, 0x0005 },
3290 { 0x05, 0x8b55 },
3291 { 0x06, 0x0000 },
3292 { 0x05, 0x8b5e },
3293 { 0x06, 0x0000 },
3294 { 0x05, 0x8b67 },
3295 { 0x06, 0x0000 },
3296 { 0x05, 0x8b70 },
3297 { 0x06, 0x0000 },
3298 { 0x1f, 0x0000 },
3299 { 0x1f, 0x0007 },
3300 { 0x1e, 0x0078 },
3301 { 0x17, 0x0000 },
3302 { 0x19, 0x00fb },
3303 { 0x1f, 0x0000 },
3304
3305 /* Modify green table for 10M */
3306 { 0x1f, 0x0005 },
3307 { 0x05, 0x8b79 },
3308 { 0x06, 0xaa00 },
3309 { 0x1f, 0x0000 },
3310
3311 /* Disable hiimpedance detection (RTCT) */
3312 { 0x1f, 0x0003 },
3313 { 0x01, 0x328a },
3314 { 0x1f, 0x0000 }
3315 };
3316
3317 rtl_apply_firmware(tp);
3318
3319 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3320
3321 rtl8168f_hw_phy_config(tp);
3322
3323 /* Improve 2-pair detection performance */
3324 rtl_writephy(tp, 0x1f, 0x0005);
3325 rtl_writephy(tp, 0x05, 0x8b85);
3326 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3327 rtl_writephy(tp, 0x1f, 0x0000);
3328}
3329
3330static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3331{
3332 rtl_apply_firmware(tp);
3333
3334 rtl8168f_hw_phy_config(tp);
3335}
3336
3337static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3338{
3339 static const struct phy_reg phy_reg_init[] = {
3340 /* Channel estimation fine tune */
3341 { 0x1f, 0x0003 },
3342 { 0x09, 0xa20f },
3343 { 0x1f, 0x0000 },
3344
3345 /* Modify green table for giga & fnet */
3346 { 0x1f, 0x0005 },
3347 { 0x05, 0x8b55 },
3348 { 0x06, 0x0000 },
3349 { 0x05, 0x8b5e },
3350 { 0x06, 0x0000 },
3351 { 0x05, 0x8b67 },
3352 { 0x06, 0x0000 },
3353 { 0x05, 0x8b70 },
3354 { 0x06, 0x0000 },
3355 { 0x1f, 0x0000 },
3356 { 0x1f, 0x0007 },
3357 { 0x1e, 0x0078 },
3358 { 0x17, 0x0000 },
3359 { 0x19, 0x00aa },
3360 { 0x1f, 0x0000 },
3361
3362 /* Modify green table for 10M */
3363 { 0x1f, 0x0005 },
3364 { 0x05, 0x8b79 },
3365 { 0x06, 0xaa00 },
3366 { 0x1f, 0x0000 },
3367
3368 /* Disable hiimpedance detection (RTCT) */
3369 { 0x1f, 0x0003 },
3370 { 0x01, 0x328a },
3371 { 0x1f, 0x0000 }
3372 };
3373
3374
3375 rtl_apply_firmware(tp);
3376
3377 rtl8168f_hw_phy_config(tp);
3378
3379 /* Improve 2-pair detection performance */
3380 rtl_writephy(tp, 0x1f, 0x0005);
3381 rtl_writephy(tp, 0x05, 0x8b85);
3382 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3383 rtl_writephy(tp, 0x1f, 0x0000);
3384
3385 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3386
3387 /* Modify green table for giga */
3388 rtl_writephy(tp, 0x1f, 0x0005);
3389 rtl_writephy(tp, 0x05, 0x8b54);
3390 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3391 rtl_writephy(tp, 0x05, 0x8b5d);
3392 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3393 rtl_writephy(tp, 0x05, 0x8a7c);
3394 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3395 rtl_writephy(tp, 0x05, 0x8a7f);
3396 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3397 rtl_writephy(tp, 0x05, 0x8a82);
3398 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3399 rtl_writephy(tp, 0x05, 0x8a85);
3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3401 rtl_writephy(tp, 0x05, 0x8a88);
3402 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3403 rtl_writephy(tp, 0x1f, 0x0000);
3404
3405 /* uc same-seed solution */
3406 rtl_writephy(tp, 0x1f, 0x0005);
3407 rtl_writephy(tp, 0x05, 0x8b85);
3408 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3409 rtl_writephy(tp, 0x1f, 0x0000);
3410
3411 /* eee setting */
3412 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3413 rtl_writephy(tp, 0x1f, 0x0005);
3414 rtl_writephy(tp, 0x05, 0x8b85);
3415 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3416 rtl_writephy(tp, 0x1f, 0x0004);
3417 rtl_writephy(tp, 0x1f, 0x0007);
3418 rtl_writephy(tp, 0x1e, 0x0020);
3419 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3420 rtl_writephy(tp, 0x1f, 0x0000);
3421 rtl_writephy(tp, 0x0d, 0x0007);
3422 rtl_writephy(tp, 0x0e, 0x003c);
3423 rtl_writephy(tp, 0x0d, 0x4007);
3424 rtl_writephy(tp, 0x0e, 0x0000);
3425 rtl_writephy(tp, 0x0d, 0x0000);
3426
3427 /* Green feature */
3428 rtl_writephy(tp, 0x1f, 0x0003);
3429 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3430 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3431 rtl_writephy(tp, 0x1f, 0x0000);
3432}
3433
3434static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3435{
3436 rtl_apply_firmware(tp);
3437
3438 rtl_writephy(tp, 0x1f, 0x0a46);
3439 if (rtl_readphy(tp, 0x10) & 0x0100) {
3440 rtl_writephy(tp, 0x1f, 0x0bcc);
3441 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3442 } else {
3443 rtl_writephy(tp, 0x1f, 0x0bcc);
3444 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3445 }
3446
3447 rtl_writephy(tp, 0x1f, 0x0a46);
3448 if (rtl_readphy(tp, 0x13) & 0x0100) {
3449 rtl_writephy(tp, 0x1f, 0x0c41);
3450 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3451 } else {
3452 rtl_writephy(tp, 0x1f, 0x0c41);
3453 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3454 }
3455
3456 /* Enable PHY auto speed down */
3457 rtl_writephy(tp, 0x1f, 0x0a44);
3458 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3459
3460 rtl_writephy(tp, 0x1f, 0x0bcc);
3461 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3462 rtl_writephy(tp, 0x1f, 0x0a44);
3463 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3464 rtl_writephy(tp, 0x1f, 0x0a43);
3465 rtl_writephy(tp, 0x13, 0x8084);
3466 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3467 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3468
3469 /* EEE auto-fallback function */
3470 rtl_writephy(tp, 0x1f, 0x0a4b);
3471 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3472
3473 /* Enable UC LPF tune function */
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x8012);
3476 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3477
3478 rtl_writephy(tp, 0x1f, 0x0c42);
3479 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3480
3481 /* Improve SWR Efficiency */
3482 rtl_writephy(tp, 0x1f, 0x0bcd);
3483 rtl_writephy(tp, 0x14, 0x5065);
3484 rtl_writephy(tp, 0x14, 0xd065);
3485 rtl_writephy(tp, 0x1f, 0x0bc8);
3486 rtl_writephy(tp, 0x11, 0x5655);
3487 rtl_writephy(tp, 0x1f, 0x0bcd);
3488 rtl_writephy(tp, 0x14, 0x1065);
3489 rtl_writephy(tp, 0x14, 0x9065);
3490 rtl_writephy(tp, 0x14, 0x1065);
3491
3492 /* Check ALDPS bit, disable it if enabled */
3493 rtl_writephy(tp, 0x1f, 0x0a43);
3494 if (rtl_readphy(tp, 0x10) & 0x0004)
3495 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3496
3497 rtl_writephy(tp, 0x1f, 0x0000);
3498}
3499
3500static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3501{
3502 rtl_apply_firmware(tp);
3503}
3504
3505static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3506{
3507 u16 dout_tapbin;
3508 u32 data;
3509
3510 rtl_apply_firmware(tp);
3511
3512 /* CHN EST parameters adjust - giga master */
3513 rtl_writephy(tp, 0x1f, 0x0a43);
3514 rtl_writephy(tp, 0x13, 0x809b);
3515 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3516 rtl_writephy(tp, 0x13, 0x80a2);
3517 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3518 rtl_writephy(tp, 0x13, 0x80a4);
3519 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3520 rtl_writephy(tp, 0x13, 0x809c);
3521 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3522 rtl_writephy(tp, 0x1f, 0x0000);
3523
3524 /* CHN EST parameters adjust - giga slave */
3525 rtl_writephy(tp, 0x1f, 0x0a43);
3526 rtl_writephy(tp, 0x13, 0x80ad);
3527 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3528 rtl_writephy(tp, 0x13, 0x80b4);
3529 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3530 rtl_writephy(tp, 0x13, 0x80ac);
3531 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533
3534 /* CHN EST parameters adjust - fnet */
3535 rtl_writephy(tp, 0x1f, 0x0a43);
3536 rtl_writephy(tp, 0x13, 0x808e);
3537 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3538 rtl_writephy(tp, 0x13, 0x8090);
3539 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3540 rtl_writephy(tp, 0x13, 0x8092);
3541 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3542 rtl_writephy(tp, 0x1f, 0x0000);
3543
3544 /* enable R-tune & PGA-retune function */
3545 dout_tapbin = 0;
3546 rtl_writephy(tp, 0x1f, 0x0a46);
3547 data = rtl_readphy(tp, 0x13);
3548 data &= 3;
3549 data <<= 2;
3550 dout_tapbin |= data;
3551 data = rtl_readphy(tp, 0x12);
3552 data &= 0xc000;
3553 data >>= 14;
3554 dout_tapbin |= data;
3555 dout_tapbin = ~(dout_tapbin^0x08);
3556 dout_tapbin <<= 12;
3557 dout_tapbin &= 0xf000;
3558 rtl_writephy(tp, 0x1f, 0x0a43);
3559 rtl_writephy(tp, 0x13, 0x827a);
3560 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3561 rtl_writephy(tp, 0x13, 0x827b);
3562 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3563 rtl_writephy(tp, 0x13, 0x827c);
3564 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3565 rtl_writephy(tp, 0x13, 0x827d);
3566 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3567
3568 rtl_writephy(tp, 0x1f, 0x0a43);
3569 rtl_writephy(tp, 0x13, 0x0811);
3570 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3571 rtl_writephy(tp, 0x1f, 0x0a42);
3572 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3573 rtl_writephy(tp, 0x1f, 0x0000);
3574
3575 /* enable GPHY 10M */
3576 rtl_writephy(tp, 0x1f, 0x0a44);
3577 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3578 rtl_writephy(tp, 0x1f, 0x0000);
3579
3580 /* SAR ADC performance */
3581 rtl_writephy(tp, 0x1f, 0x0bca);
3582 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3583 rtl_writephy(tp, 0x1f, 0x0000);
3584
3585 rtl_writephy(tp, 0x1f, 0x0a43);
3586 rtl_writephy(tp, 0x13, 0x803f);
3587 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3588 rtl_writephy(tp, 0x13, 0x8047);
3589 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3590 rtl_writephy(tp, 0x13, 0x804f);
3591 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3592 rtl_writephy(tp, 0x13, 0x8057);
3593 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3594 rtl_writephy(tp, 0x13, 0x805f);
3595 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3596 rtl_writephy(tp, 0x13, 0x8067);
3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3598 rtl_writephy(tp, 0x13, 0x806f);
3599 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3600 rtl_writephy(tp, 0x1f, 0x0000);
3601
3602 /* disable phy pfm mode */
3603 rtl_writephy(tp, 0x1f, 0x0a44);
3604 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3605 rtl_writephy(tp, 0x1f, 0x0000);
3606
3607 /* Check ALDPS bit, disable it if enabled */
3608 rtl_writephy(tp, 0x1f, 0x0a43);
3609 if (rtl_readphy(tp, 0x10) & 0x0004)
3610 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3611
3612 rtl_writephy(tp, 0x1f, 0x0000);
3613}
3614
3615static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3616{
3617 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3618 u16 rlen;
3619 u32 data;
3620
3621 rtl_apply_firmware(tp);
3622
3623 /* CHIN EST parameter update */
3624 rtl_writephy(tp, 0x1f, 0x0a43);
3625 rtl_writephy(tp, 0x13, 0x808a);
3626 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3627 rtl_writephy(tp, 0x1f, 0x0000);
3628
3629 /* enable R-tune & PGA-retune function */
3630 rtl_writephy(tp, 0x1f, 0x0a43);
3631 rtl_writephy(tp, 0x13, 0x0811);
3632 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3633 rtl_writephy(tp, 0x1f, 0x0a42);
3634 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3635 rtl_writephy(tp, 0x1f, 0x0000);
3636
3637 /* enable GPHY 10M */
3638 rtl_writephy(tp, 0x1f, 0x0a44);
3639 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3640 rtl_writephy(tp, 0x1f, 0x0000);
3641
3642 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3643 data = r8168_mac_ocp_read(tp, 0xdd02);
3644 ioffset_p3 = ((data & 0x80)>>7);
3645 ioffset_p3 <<= 3;
3646
3647 data = r8168_mac_ocp_read(tp, 0xdd00);
3648 ioffset_p3 |= ((data & (0xe000))>>13);
3649 ioffset_p2 = ((data & (0x1e00))>>9);
3650 ioffset_p1 = ((data & (0x01e0))>>5);
3651 ioffset_p0 = ((data & 0x0010)>>4);
3652 ioffset_p0 <<= 3;
3653 ioffset_p0 |= (data & (0x07));
3654 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3655
3656 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3657 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3658 rtl_writephy(tp, 0x1f, 0x0bcf);
3659 rtl_writephy(tp, 0x16, data);
3660 rtl_writephy(tp, 0x1f, 0x0000);
3661 }
3662
3663 /* Modify rlen (TX LPF corner frequency) level */
3664 rtl_writephy(tp, 0x1f, 0x0bcd);
3665 data = rtl_readphy(tp, 0x16);
3666 data &= 0x000f;
3667 rlen = 0;
3668 if (data > 3)
3669 rlen = data - 3;
3670 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3671 rtl_writephy(tp, 0x17, data);
3672 rtl_writephy(tp, 0x1f, 0x0bcd);
3673 rtl_writephy(tp, 0x1f, 0x0000);
3674
3675 /* disable phy pfm mode */
3676 rtl_writephy(tp, 0x1f, 0x0a44);
3677 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3678 rtl_writephy(tp, 0x1f, 0x0000);
3679
3680 /* Check ALDPS bit, disable it if enabled */
3681 rtl_writephy(tp, 0x1f, 0x0a43);
3682 if (rtl_readphy(tp, 0x10) & 0x0004)
3683 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3684
3685 rtl_writephy(tp, 0x1f, 0x0000);
3686}
3687
3688static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3689{
3690 /* Enable PHY auto speed down */
3691 rtl_writephy(tp, 0x1f, 0x0a44);
3692 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3693 rtl_writephy(tp, 0x1f, 0x0000);
3694
3695 /* patch 10M & ALDPS */
3696 rtl_writephy(tp, 0x1f, 0x0bcc);
3697 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3698 rtl_writephy(tp, 0x1f, 0x0a44);
3699 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3700 rtl_writephy(tp, 0x1f, 0x0a43);
3701 rtl_writephy(tp, 0x13, 0x8084);
3702 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3703 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3704 rtl_writephy(tp, 0x1f, 0x0000);
3705
3706 /* Enable EEE auto-fallback function */
3707 rtl_writephy(tp, 0x1f, 0x0a4b);
3708 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3709 rtl_writephy(tp, 0x1f, 0x0000);
3710
3711 /* Enable UC LPF tune function */
3712 rtl_writephy(tp, 0x1f, 0x0a43);
3713 rtl_writephy(tp, 0x13, 0x8012);
3714 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3715 rtl_writephy(tp, 0x1f, 0x0000);
3716
3717 /* set rg_sel_sdm_rate */
3718 rtl_writephy(tp, 0x1f, 0x0c42);
3719 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3720 rtl_writephy(tp, 0x1f, 0x0000);
3721
3722 /* Check ALDPS bit, disable it if enabled */
3723 rtl_writephy(tp, 0x1f, 0x0a43);
3724 if (rtl_readphy(tp, 0x10) & 0x0004)
3725 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3726
3727 rtl_writephy(tp, 0x1f, 0x0000);
3728}
3729
3730static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3731{
3732 /* patch 10M & ALDPS */
3733 rtl_writephy(tp, 0x1f, 0x0bcc);
3734 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3735 rtl_writephy(tp, 0x1f, 0x0a44);
3736 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3737 rtl_writephy(tp, 0x1f, 0x0a43);
3738 rtl_writephy(tp, 0x13, 0x8084);
3739 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3740 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3741 rtl_writephy(tp, 0x1f, 0x0000);
3742
3743 /* Enable UC LPF tune function */
3744 rtl_writephy(tp, 0x1f, 0x0a43);
3745 rtl_writephy(tp, 0x13, 0x8012);
3746 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3748
3749 /* Set rg_sel_sdm_rate */
3750 rtl_writephy(tp, 0x1f, 0x0c42);
3751 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3752 rtl_writephy(tp, 0x1f, 0x0000);
3753
3754 /* Channel estimation parameters */
3755 rtl_writephy(tp, 0x1f, 0x0a43);
3756 rtl_writephy(tp, 0x13, 0x80f3);
3757 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3758 rtl_writephy(tp, 0x13, 0x80f0);
3759 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3760 rtl_writephy(tp, 0x13, 0x80ef);
3761 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3762 rtl_writephy(tp, 0x13, 0x80f6);
3763 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3764 rtl_writephy(tp, 0x13, 0x80ec);
3765 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3766 rtl_writephy(tp, 0x13, 0x80ed);
3767 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3768 rtl_writephy(tp, 0x13, 0x80f2);
3769 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3770 rtl_writephy(tp, 0x13, 0x80f4);
3771 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3772 rtl_writephy(tp, 0x1f, 0x0a43);
3773 rtl_writephy(tp, 0x13, 0x8110);
3774 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3775 rtl_writephy(tp, 0x13, 0x810f);
3776 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3777 rtl_writephy(tp, 0x13, 0x8111);
3778 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3779 rtl_writephy(tp, 0x13, 0x8113);
3780 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3781 rtl_writephy(tp, 0x13, 0x8115);
3782 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3783 rtl_writephy(tp, 0x13, 0x810e);
3784 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3785 rtl_writephy(tp, 0x13, 0x810c);
3786 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3787 rtl_writephy(tp, 0x13, 0x810b);
3788 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3789 rtl_writephy(tp, 0x1f, 0x0a43);
3790 rtl_writephy(tp, 0x13, 0x80d1);
3791 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3792 rtl_writephy(tp, 0x13, 0x80cd);
3793 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3794 rtl_writephy(tp, 0x13, 0x80d3);
3795 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3796 rtl_writephy(tp, 0x13, 0x80d5);
3797 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3798 rtl_writephy(tp, 0x13, 0x80d7);
3799 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3800
3801 /* Force PWM-mode */
3802 rtl_writephy(tp, 0x1f, 0x0bcd);
3803 rtl_writephy(tp, 0x14, 0x5065);
3804 rtl_writephy(tp, 0x14, 0xd065);
3805 rtl_writephy(tp, 0x1f, 0x0bc8);
3806 rtl_writephy(tp, 0x12, 0x00ed);
3807 rtl_writephy(tp, 0x1f, 0x0bcd);
3808 rtl_writephy(tp, 0x14, 0x1065);
3809 rtl_writephy(tp, 0x14, 0x9065);
3810 rtl_writephy(tp, 0x14, 0x1065);
3811 rtl_writephy(tp, 0x1f, 0x0000);
3812
3813 /* Check ALDPS bit, disable it if enabled */
3814 rtl_writephy(tp, 0x1f, 0x0a43);
3815 if (rtl_readphy(tp, 0x10) & 0x0004)
3816 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3817
3818 rtl_writephy(tp, 0x1f, 0x0000);
3819}
3820
3821static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3822{
3823 static const struct phy_reg phy_reg_init[] = {
3824 { 0x1f, 0x0003 },
3825 { 0x08, 0x441d },
3826 { 0x01, 0x9100 },
3827 { 0x1f, 0x0000 }
3828 };
3829
3830 rtl_writephy(tp, 0x1f, 0x0000);
3831 rtl_patchphy(tp, 0x11, 1 << 12);
3832 rtl_patchphy(tp, 0x19, 1 << 13);
3833 rtl_patchphy(tp, 0x10, 1 << 15);
3834
3835 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3836}
3837
3838static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3839{
3840 static const struct phy_reg phy_reg_init[] = {
3841 { 0x1f, 0x0005 },
3842 { 0x1a, 0x0000 },
3843 { 0x1f, 0x0000 },
3844
3845 { 0x1f, 0x0004 },
3846 { 0x1c, 0x0000 },
3847 { 0x1f, 0x0000 },
3848
3849 { 0x1f, 0x0001 },
3850 { 0x15, 0x7701 },
3851 { 0x1f, 0x0000 }
3852 };
3853
3854 /* Disable ALDPS before ram code */
3855 rtl_writephy(tp, 0x1f, 0x0000);
3856 rtl_writephy(tp, 0x18, 0x0310);
3857 msleep(100);
3858
3859 rtl_apply_firmware(tp);
3860
3861 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3862}
3863
3864static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3865{
3866 /* Disable ALDPS before setting firmware */
3867 rtl_writephy(tp, 0x1f, 0x0000);
3868 rtl_writephy(tp, 0x18, 0x0310);
3869 msleep(20);
3870
3871 rtl_apply_firmware(tp);
3872
3873 /* EEE setting */
3874 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3875 rtl_writephy(tp, 0x1f, 0x0004);
3876 rtl_writephy(tp, 0x10, 0x401f);
3877 rtl_writephy(tp, 0x19, 0x7030);
3878 rtl_writephy(tp, 0x1f, 0x0000);
3879}
3880
3881static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3882{
3883 static const struct phy_reg phy_reg_init[] = {
3884 { 0x1f, 0x0004 },
3885 { 0x10, 0xc07f },
3886 { 0x19, 0x7030 },
3887 { 0x1f, 0x0000 }
3888 };
3889
3890 /* Disable ALDPS before ram code */
3891 rtl_writephy(tp, 0x1f, 0x0000);
3892 rtl_writephy(tp, 0x18, 0x0310);
3893 msleep(100);
3894
3895 rtl_apply_firmware(tp);
3896
3897 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3898 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3899
3900 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3901}
3902
3903static void rtl_hw_phy_config(struct net_device *dev)
3904{
3905 struct rtl8169_private *tp = netdev_priv(dev);
3906
3907 rtl8169_print_mac_version(tp);
3908
3909 switch (tp->mac_version) {
3910 case RTL_GIGA_MAC_VER_01:
3911 break;
3912 case RTL_GIGA_MAC_VER_02:
3913 case RTL_GIGA_MAC_VER_03:
3914 rtl8169s_hw_phy_config(tp);
3915 break;
3916 case RTL_GIGA_MAC_VER_04:
3917 rtl8169sb_hw_phy_config(tp);
3918 break;
3919 case RTL_GIGA_MAC_VER_05:
3920 rtl8169scd_hw_phy_config(tp);
3921 break;
3922 case RTL_GIGA_MAC_VER_06:
3923 rtl8169sce_hw_phy_config(tp);
3924 break;
3925 case RTL_GIGA_MAC_VER_07:
3926 case RTL_GIGA_MAC_VER_08:
3927 case RTL_GIGA_MAC_VER_09:
3928 rtl8102e_hw_phy_config(tp);
3929 break;
3930 case RTL_GIGA_MAC_VER_11:
3931 rtl8168bb_hw_phy_config(tp);
3932 break;
3933 case RTL_GIGA_MAC_VER_12:
3934 rtl8168bef_hw_phy_config(tp);
3935 break;
3936 case RTL_GIGA_MAC_VER_17:
3937 rtl8168bef_hw_phy_config(tp);
3938 break;
3939 case RTL_GIGA_MAC_VER_18:
3940 rtl8168cp_1_hw_phy_config(tp);
3941 break;
3942 case RTL_GIGA_MAC_VER_19:
3943 rtl8168c_1_hw_phy_config(tp);
3944 break;
3945 case RTL_GIGA_MAC_VER_20:
3946 rtl8168c_2_hw_phy_config(tp);
3947 break;
3948 case RTL_GIGA_MAC_VER_21:
3949 rtl8168c_3_hw_phy_config(tp);
3950 break;
3951 case RTL_GIGA_MAC_VER_22:
3952 rtl8168c_4_hw_phy_config(tp);
3953 break;
3954 case RTL_GIGA_MAC_VER_23:
3955 case RTL_GIGA_MAC_VER_24:
3956 rtl8168cp_2_hw_phy_config(tp);
3957 break;
3958 case RTL_GIGA_MAC_VER_25:
3959 rtl8168d_1_hw_phy_config(tp);
3960 break;
3961 case RTL_GIGA_MAC_VER_26:
3962 rtl8168d_2_hw_phy_config(tp);
3963 break;
3964 case RTL_GIGA_MAC_VER_27:
3965 rtl8168d_3_hw_phy_config(tp);
3966 break;
3967 case RTL_GIGA_MAC_VER_28:
3968 rtl8168d_4_hw_phy_config(tp);
3969 break;
3970 case RTL_GIGA_MAC_VER_29:
3971 case RTL_GIGA_MAC_VER_30:
3972 rtl8105e_hw_phy_config(tp);
3973 break;
3974 case RTL_GIGA_MAC_VER_31:
3975 /* None. */
3976 break;
3977 case RTL_GIGA_MAC_VER_32:
3978 case RTL_GIGA_MAC_VER_33:
3979 rtl8168e_1_hw_phy_config(tp);
3980 break;
3981 case RTL_GIGA_MAC_VER_34:
3982 rtl8168e_2_hw_phy_config(tp);
3983 break;
3984 case RTL_GIGA_MAC_VER_35:
3985 rtl8168f_1_hw_phy_config(tp);
3986 break;
3987 case RTL_GIGA_MAC_VER_36:
3988 rtl8168f_2_hw_phy_config(tp);
3989 break;
3990
3991 case RTL_GIGA_MAC_VER_37:
3992 rtl8402_hw_phy_config(tp);
3993 break;
3994
3995 case RTL_GIGA_MAC_VER_38:
3996 rtl8411_hw_phy_config(tp);
3997 break;
3998
3999 case RTL_GIGA_MAC_VER_39:
4000 rtl8106e_hw_phy_config(tp);
4001 break;
4002
4003 case RTL_GIGA_MAC_VER_40:
4004 rtl8168g_1_hw_phy_config(tp);
4005 break;
4006 case RTL_GIGA_MAC_VER_42:
4007 case RTL_GIGA_MAC_VER_43:
4008 case RTL_GIGA_MAC_VER_44:
4009 rtl8168g_2_hw_phy_config(tp);
4010 break;
4011 case RTL_GIGA_MAC_VER_45:
4012 case RTL_GIGA_MAC_VER_47:
4013 rtl8168h_1_hw_phy_config(tp);
4014 break;
4015 case RTL_GIGA_MAC_VER_46:
4016 case RTL_GIGA_MAC_VER_48:
4017 rtl8168h_2_hw_phy_config(tp);
4018 break;
4019
4020 case RTL_GIGA_MAC_VER_49:
4021 rtl8168ep_1_hw_phy_config(tp);
4022 break;
4023 case RTL_GIGA_MAC_VER_50:
4024 case RTL_GIGA_MAC_VER_51:
4025 rtl8168ep_2_hw_phy_config(tp);
4026 break;
4027
4028 case RTL_GIGA_MAC_VER_41:
4029 default:
4030 break;
4031 }
4032}
4033
4034static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4035{
4036 if (!test_and_set_bit(flag, tp->wk.flags))
4037 schedule_work(&tp->wk.work);
4038}
4039
4040static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4041{
4042 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4043 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4044}
4045
4046static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4047{
4048 rtl_hw_phy_config(dev);
4049
4050 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4051 netif_dbg(tp, drv, dev,
4052 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4053 RTL_W8(tp, 0x82, 0x01);
4054 }
4055
4056 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4057
4058 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4059 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4060
4061 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4062 netif_dbg(tp, drv, dev,
4063 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4064 RTL_W8(tp, 0x82, 0x01);
4065 netif_dbg(tp, drv, dev,
4066 "Set PHY Reg 0x0bh = 0x00h\n");
4067 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4068 }
4069
4070 /* We may have called phy_speed_down before */
4071 phy_speed_up(dev->phydev);
4072
4073 genphy_soft_reset(dev->phydev);
4074
4075 /* It was reported that several chips end up with 10MBit/Half on a
4076 * 1GBit link after resuming from S3. For whatever reason the PHY on
4077 * these chips doesn't properly start a renegotiation when soft-reset.
4078 * Explicitly requesting a renegotiation fixes this.
4079 */
4080 if (dev->phydev->autoneg == AUTONEG_ENABLE)
4081 phy_restart_aneg(dev->phydev);
4082}
4083
4084static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4085{
4086 rtl_lock_work(tp);
4087
4088 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4089
4090 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4091 RTL_R32(tp, MAC4);
4092
4093 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4094 RTL_R32(tp, MAC0);
4095
4096 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4097 rtl_rar_exgmac_set(tp, addr);
4098
4099 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4100
4101 rtl_unlock_work(tp);
4102}
4103
4104static int rtl_set_mac_address(struct net_device *dev, void *p)
4105{
4106 struct rtl8169_private *tp = netdev_priv(dev);
4107 struct device *d = tp_to_dev(tp);
4108 int ret;
4109
4110 ret = eth_mac_addr(dev, p);
4111 if (ret)
4112 return ret;
4113
4114 pm_runtime_get_noresume(d);
4115
4116 if (pm_runtime_active(d))
4117 rtl_rar_set(tp, dev->dev_addr);
4118
4119 pm_runtime_put_noidle(d);
4120
4121 return 0;
4122}
4123
4124static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4125{
4126 if (!netif_running(dev))
4127 return -ENODEV;
4128
4129 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4130}
4131
4132static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4133{
4134 struct mdio_ops *ops = &tp->mdio_ops;
4135
4136 switch (tp->mac_version) {
4137 case RTL_GIGA_MAC_VER_27:
4138 ops->write = r8168dp_1_mdio_write;
4139 ops->read = r8168dp_1_mdio_read;
4140 break;
4141 case RTL_GIGA_MAC_VER_28:
4142 case RTL_GIGA_MAC_VER_31:
4143 ops->write = r8168dp_2_mdio_write;
4144 ops->read = r8168dp_2_mdio_read;
4145 break;
4146 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4147 ops->write = r8168g_mdio_write;
4148 ops->read = r8168g_mdio_read;
4149 break;
4150 default:
4151 ops->write = r8169_mdio_write;
4152 ops->read = r8169_mdio_read;
4153 break;
4154 }
4155}
4156
4157static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4158{
4159 switch (tp->mac_version) {
4160 case RTL_GIGA_MAC_VER_25:
4161 case RTL_GIGA_MAC_VER_26:
4162 case RTL_GIGA_MAC_VER_29:
4163 case RTL_GIGA_MAC_VER_30:
4164 case RTL_GIGA_MAC_VER_32:
4165 case RTL_GIGA_MAC_VER_33:
4166 case RTL_GIGA_MAC_VER_34:
4167 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4168 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4169 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4170 break;
4171 default:
4172 break;
4173 }
4174}
4175
4176static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4177{
4178 struct phy_device *phydev;
4179
4180 if (!__rtl8169_get_wol(tp))
4181 return false;
4182
4183 /* phydev may not be attached to netdevice */
4184 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4185
4186 phy_speed_down(phydev, false);
4187 rtl_wol_suspend_quirk(tp);
4188
4189 return true;
4190}
4191
4192static void r8168_pll_power_down(struct rtl8169_private *tp)
4193{
4194 if (r8168_check_dash(tp))
4195 return;
4196
4197 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4198 tp->mac_version == RTL_GIGA_MAC_VER_33)
4199 rtl_ephy_write(tp, 0x19, 0xff64);
4200
4201 if (rtl_wol_pll_power_down(tp))
4202 return;
4203
4204 switch (tp->mac_version) {
4205 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4206 case RTL_GIGA_MAC_VER_37:
4207 case RTL_GIGA_MAC_VER_39:
4208 case RTL_GIGA_MAC_VER_43:
4209 case RTL_GIGA_MAC_VER_44:
4210 case RTL_GIGA_MAC_VER_45:
4211 case RTL_GIGA_MAC_VER_46:
4212 case RTL_GIGA_MAC_VER_47:
4213 case RTL_GIGA_MAC_VER_48:
4214 case RTL_GIGA_MAC_VER_50:
4215 case RTL_GIGA_MAC_VER_51:
4216 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4217 break;
4218 case RTL_GIGA_MAC_VER_40:
4219 case RTL_GIGA_MAC_VER_41:
4220 case RTL_GIGA_MAC_VER_49:
4221 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4222 0xfc000000, ERIAR_EXGMAC);
4223 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4224 break;
4225 }
4226}
4227
4228static void r8168_pll_power_up(struct rtl8169_private *tp)
4229{
4230 switch (tp->mac_version) {
4231 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4232 case RTL_GIGA_MAC_VER_37:
4233 case RTL_GIGA_MAC_VER_39:
4234 case RTL_GIGA_MAC_VER_43:
4235 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4236 break;
4237 case RTL_GIGA_MAC_VER_44:
4238 case RTL_GIGA_MAC_VER_45:
4239 case RTL_GIGA_MAC_VER_46:
4240 case RTL_GIGA_MAC_VER_47:
4241 case RTL_GIGA_MAC_VER_48:
4242 case RTL_GIGA_MAC_VER_50:
4243 case RTL_GIGA_MAC_VER_51:
4244 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4245 break;
4246 case RTL_GIGA_MAC_VER_40:
4247 case RTL_GIGA_MAC_VER_41:
4248 case RTL_GIGA_MAC_VER_49:
4249 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4250 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4251 0x00000000, ERIAR_EXGMAC);
4252 break;
4253 }
4254
4255 phy_resume(tp->dev->phydev);
4256 /* give MAC/PHY some time to resume */
4257 msleep(20);
4258}
4259
4260static void rtl_pll_power_down(struct rtl8169_private *tp)
4261{
4262 switch (tp->mac_version) {
4263 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4264 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4265 break;
4266 default:
4267 r8168_pll_power_down(tp);
4268 }
4269}
4270
4271static void rtl_pll_power_up(struct rtl8169_private *tp)
4272{
4273 switch (tp->mac_version) {
4274 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4275 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4276 break;
4277 default:
4278 r8168_pll_power_up(tp);
4279 }
4280}
4281
4282static void rtl_init_rxcfg(struct rtl8169_private *tp)
4283{
4284 switch (tp->mac_version) {
4285 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4286 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4287 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4288 break;
4289 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4290 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4291 case RTL_GIGA_MAC_VER_38:
4292 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4293 break;
4294 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4295 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4296 break;
4297 default:
4298 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4299 break;
4300 }
4301}
4302
4303static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4304{
4305 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4306}
4307
4308static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4309{
4310 if (tp->jumbo_ops.enable) {
4311 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4312 tp->jumbo_ops.enable(tp);
4313 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4314 }
4315}
4316
4317static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4318{
4319 if (tp->jumbo_ops.disable) {
4320 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4321 tp->jumbo_ops.disable(tp);
4322 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4323 }
4324}
4325
4326static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4327{
4328 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4329 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4330 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4331}
4332
4333static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4334{
4335 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4336 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4337 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4338}
4339
4340static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4341{
4342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4343}
4344
4345static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4346{
4347 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4348}
4349
4350static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4351{
4352 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4353 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4354 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4355 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4356}
4357
4358static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4359{
4360 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4361 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4362 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4363 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4364}
4365
4366static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4367{
4368 rtl_tx_performance_tweak(tp,
4369 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4370}
4371
4372static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4373{
4374 rtl_tx_performance_tweak(tp,
4375 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4376}
4377
4378static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4379{
4380 r8168b_0_hw_jumbo_enable(tp);
4381
4382 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4383}
4384
4385static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4386{
4387 r8168b_0_hw_jumbo_disable(tp);
4388
4389 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4390}
4391
4392static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4393{
4394 struct jumbo_ops *ops = &tp->jumbo_ops;
4395
4396 switch (tp->mac_version) {
4397 case RTL_GIGA_MAC_VER_11:
4398 ops->disable = r8168b_0_hw_jumbo_disable;
4399 ops->enable = r8168b_0_hw_jumbo_enable;
4400 break;
4401 case RTL_GIGA_MAC_VER_12:
4402 case RTL_GIGA_MAC_VER_17:
4403 ops->disable = r8168b_1_hw_jumbo_disable;
4404 ops->enable = r8168b_1_hw_jumbo_enable;
4405 break;
4406 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4407 case RTL_GIGA_MAC_VER_19:
4408 case RTL_GIGA_MAC_VER_20:
4409 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4410 case RTL_GIGA_MAC_VER_22:
4411 case RTL_GIGA_MAC_VER_23:
4412 case RTL_GIGA_MAC_VER_24:
4413 case RTL_GIGA_MAC_VER_25:
4414 case RTL_GIGA_MAC_VER_26:
4415 ops->disable = r8168c_hw_jumbo_disable;
4416 ops->enable = r8168c_hw_jumbo_enable;
4417 break;
4418 case RTL_GIGA_MAC_VER_27:
4419 case RTL_GIGA_MAC_VER_28:
4420 ops->disable = r8168dp_hw_jumbo_disable;
4421 ops->enable = r8168dp_hw_jumbo_enable;
4422 break;
4423 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4424 case RTL_GIGA_MAC_VER_32:
4425 case RTL_GIGA_MAC_VER_33:
4426 case RTL_GIGA_MAC_VER_34:
4427 ops->disable = r8168e_hw_jumbo_disable;
4428 ops->enable = r8168e_hw_jumbo_enable;
4429 break;
4430
4431 /*
4432 * No action needed for jumbo frames with 8169.
4433 * No jumbo for 810x at all.
4434 */
4435 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4436 default:
4437 ops->disable = NULL;
4438 ops->enable = NULL;
4439 break;
4440 }
4441}
4442
4443DECLARE_RTL_COND(rtl_chipcmd_cond)
4444{
4445 return RTL_R8(tp, ChipCmd) & CmdReset;
4446}
4447
4448static void rtl_hw_reset(struct rtl8169_private *tp)
4449{
4450 RTL_W8(tp, ChipCmd, CmdReset);
4451
4452 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4453}
4454
4455static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4456{
4457 struct rtl_fw *rtl_fw;
4458 const char *name;
4459 int rc = -ENOMEM;
4460
4461 name = rtl_lookup_firmware_name(tp);
4462 if (!name)
4463 goto out_no_firmware;
4464
4465 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4466 if (!rtl_fw)
4467 goto err_warn;
4468
4469 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4470 if (rc < 0)
4471 goto err_free;
4472
4473 rc = rtl_check_firmware(tp, rtl_fw);
4474 if (rc < 0)
4475 goto err_release_firmware;
4476
4477 tp->rtl_fw = rtl_fw;
4478out:
4479 return;
4480
4481err_release_firmware:
4482 release_firmware(rtl_fw->fw);
4483err_free:
4484 kfree(rtl_fw);
4485err_warn:
4486 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4487 name, rc);
4488out_no_firmware:
4489 tp->rtl_fw = NULL;
4490 goto out;
4491}
4492
4493static void rtl_request_firmware(struct rtl8169_private *tp)
4494{
4495 if (IS_ERR(tp->rtl_fw))
4496 rtl_request_uncached_firmware(tp);
4497}
4498
4499static void rtl_rx_close(struct rtl8169_private *tp)
4500{
4501 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4502}
4503
4504DECLARE_RTL_COND(rtl_npq_cond)
4505{
4506 return RTL_R8(tp, TxPoll) & NPQ;
4507}
4508
4509DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4510{
4511 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4512}
4513
4514static void rtl8169_hw_reset(struct rtl8169_private *tp)
4515{
4516 /* Disable interrupts */
4517 rtl8169_irq_mask_and_ack(tp);
4518
4519 rtl_rx_close(tp);
4520
4521 switch (tp->mac_version) {
4522 case RTL_GIGA_MAC_VER_27:
4523 case RTL_GIGA_MAC_VER_28:
4524 case RTL_GIGA_MAC_VER_31:
4525 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4526 break;
4527 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4528 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4529 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4530 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4531 break;
4532 default:
4533 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4534 udelay(100);
4535 break;
4536 }
4537
4538 rtl_hw_reset(tp);
4539}
4540
4541static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4542{
4543 u32 val = TX_DMA_BURST << TxDMAShift |
4544 InterFrameGap << TxInterFrameGapShift;
4545
4546 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4547 tp->mac_version != RTL_GIGA_MAC_VER_39)
4548 val |= TXCFG_AUTO_FIFO;
4549
4550 RTL_W32(tp, TxConfig, val);
4551}
4552
4553static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4554{
4555 /* Low hurts. Let's disable the filtering. */
4556 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4557}
4558
4559static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4560{
4561 /*
4562 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4563 * register to be written before TxDescAddrLow to work.
4564 * Switching from MMIO to I/O access fixes the issue as well.
4565 */
4566 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4567 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4568 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4569 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4570}
4571
4572static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4573{
4574 static const struct rtl_cfg2_info {
4575 u32 mac_version;
4576 u32 clk;
4577 u32 val;
4578 } cfg2_info [] = {
4579 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4580 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4581 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4582 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4583 };
4584 const struct rtl_cfg2_info *p = cfg2_info;
4585 unsigned int i;
4586 u32 clk;
4587
4588 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4589 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4590 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4591 RTL_W32(tp, 0x7c, p->val);
4592 break;
4593 }
4594 }
4595}
4596
4597static void rtl_set_rx_mode(struct net_device *dev)
4598{
4599 struct rtl8169_private *tp = netdev_priv(dev);
4600 u32 mc_filter[2]; /* Multicast hash filter */
4601 int rx_mode;
4602 u32 tmp = 0;
4603
4604 if (dev->flags & IFF_PROMISC) {
4605 /* Unconditionally log net taps. */
4606 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4607 rx_mode =
4608 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4609 AcceptAllPhys;
4610 mc_filter[1] = mc_filter[0] = 0xffffffff;
4611 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4612 (dev->flags & IFF_ALLMULTI)) {
4613 /* Too many to filter perfectly -- accept all multicasts. */
4614 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4615 mc_filter[1] = mc_filter[0] = 0xffffffff;
4616 } else {
4617 struct netdev_hw_addr *ha;
4618
4619 rx_mode = AcceptBroadcast | AcceptMyPhys;
4620 mc_filter[1] = mc_filter[0] = 0;
4621 netdev_for_each_mc_addr(ha, dev) {
4622 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4623 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4624 rx_mode |= AcceptMulticast;
4625 }
4626 }
4627
4628 if (dev->features & NETIF_F_RXALL)
4629 rx_mode |= (AcceptErr | AcceptRunt);
4630
4631 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4632
4633 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4634 u32 data = mc_filter[0];
4635
4636 mc_filter[0] = swab32(mc_filter[1]);
4637 mc_filter[1] = swab32(data);
4638 }
4639
4640 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4641 mc_filter[1] = mc_filter[0] = 0xffffffff;
4642
4643 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4644 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4645
4646 RTL_W32(tp, RxConfig, tmp);
4647}
4648
4649static void rtl_hw_start(struct rtl8169_private *tp)
4650{
4651 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4652
4653 tp->hw_start(tp);
4654
4655 rtl_set_rx_max_size(tp);
4656 rtl_set_rx_tx_desc_registers(tp);
4657 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4658
4659 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4660 RTL_R8(tp, IntrMask);
4661 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4662 rtl_init_rxcfg(tp);
4663 rtl_set_tx_config_registers(tp);
4664
4665 rtl_set_rx_mode(tp->dev);
4666 /* no early-rx interrupts */
4667 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4668 rtl_irq_enable_all(tp);
4669}
4670
4671static void rtl_hw_start_8169(struct rtl8169_private *tp)
4672{
4673 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4674 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4675
4676 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4677
4678 tp->cp_cmd |= PCIMulRW;
4679
4680 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4681 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4682 netif_dbg(tp, drv, tp->dev,
4683 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4684 tp->cp_cmd |= (1 << 14);
4685 }
4686
4687 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4688
4689 rtl8169_set_magic_reg(tp, tp->mac_version);
4690
4691 /*
4692 * Undocumented corner. Supposedly:
4693 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4694 */
4695 RTL_W16(tp, IntrMitigate, 0x0000);
4696
4697 RTL_W32(tp, RxMissed, 0);
4698}
4699
4700DECLARE_RTL_COND(rtl_csiar_cond)
4701{
4702 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4703}
4704
4705static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4706{
4707 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4708
4709 RTL_W32(tp, CSIDR, value);
4710 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4711 CSIAR_BYTE_ENABLE | func << 16);
4712
4713 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4714}
4715
4716static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4717{
4718 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4719
4720 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4721 CSIAR_BYTE_ENABLE);
4722
4723 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4724 RTL_R32(tp, CSIDR) : ~0;
4725}
4726
4727static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4728{
4729 struct pci_dev *pdev = tp->pci_dev;
4730 u32 csi;
4731
4732 /* According to Realtek the value at config space address 0x070f
4733 * controls the L0s/L1 entrance latency. We try standard ECAM access
4734 * first and if it fails fall back to CSI.
4735 */
4736 if (pdev->cfg_size > 0x070f &&
4737 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4738 return;
4739
4740 netdev_notice_once(tp->dev,
4741 "No native access to PCI extended config space, falling back to CSI\n");
4742 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4743 rtl_csi_write(tp, 0x070c, csi | val << 24);
4744}
4745
4746static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4747{
4748 rtl_csi_access_enable(tp, 0x27);
4749}
4750
4751struct ephy_info {
4752 unsigned int offset;
4753 u16 mask;
4754 u16 bits;
4755};
4756
4757static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4758 int len)
4759{
4760 u16 w;
4761
4762 while (len-- > 0) {
4763 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4764 rtl_ephy_write(tp, e->offset, w);
4765 e++;
4766 }
4767}
4768
4769static void rtl_disable_clock_request(struct rtl8169_private *tp)
4770{
4771 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4772 PCI_EXP_LNKCTL_CLKREQ_EN);
4773}
4774
4775static void rtl_enable_clock_request(struct rtl8169_private *tp)
4776{
4777 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4778 PCI_EXP_LNKCTL_CLKREQ_EN);
4779}
4780
4781static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4782{
4783 u8 data;
4784
4785 data = RTL_R8(tp, Config3);
4786
4787 if (enable)
4788 data |= Rdy_to_L23;
4789 else
4790 data &= ~Rdy_to_L23;
4791
4792 RTL_W8(tp, Config3, data);
4793}
4794
4795static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4796{
4797 if (enable) {
4798 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4799 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4800 } else {
4801 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4802 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4803 }
4804
4805 udelay(10);
4806}
4807
4808static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4809{
4810 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4811
4812 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4813 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4814
4815 if (tp->dev->mtu <= ETH_DATA_LEN) {
4816 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4817 PCI_EXP_DEVCTL_NOSNOOP_EN);
4818 }
4819}
4820
4821static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4822{
4823 rtl_hw_start_8168bb(tp);
4824
4825 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4826
4827 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4828}
4829
4830static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4831{
4832 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4833
4834 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4835
4836 if (tp->dev->mtu <= ETH_DATA_LEN)
4837 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4838
4839 rtl_disable_clock_request(tp);
4840
4841 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4842 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4843}
4844
4845static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4846{
4847 static const struct ephy_info e_info_8168cp[] = {
4848 { 0x01, 0, 0x0001 },
4849 { 0x02, 0x0800, 0x1000 },
4850 { 0x03, 0, 0x0042 },
4851 { 0x06, 0x0080, 0x0000 },
4852 { 0x07, 0, 0x2000 }
4853 };
4854
4855 rtl_set_def_aspm_entry_latency(tp);
4856
4857 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4858
4859 __rtl_hw_start_8168cp(tp);
4860}
4861
4862static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4863{
4864 rtl_set_def_aspm_entry_latency(tp);
4865
4866 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4867
4868 if (tp->dev->mtu <= ETH_DATA_LEN)
4869 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4870
4871 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4872 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4873}
4874
4875static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4876{
4877 rtl_set_def_aspm_entry_latency(tp);
4878
4879 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4880
4881 /* Magic. */
4882 RTL_W8(tp, DBG_REG, 0x20);
4883
4884 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4885
4886 if (tp->dev->mtu <= ETH_DATA_LEN)
4887 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4888
4889 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4890 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4891}
4892
4893static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4894{
4895 static const struct ephy_info e_info_8168c_1[] = {
4896 { 0x02, 0x0800, 0x1000 },
4897 { 0x03, 0, 0x0002 },
4898 { 0x06, 0x0080, 0x0000 }
4899 };
4900
4901 rtl_set_def_aspm_entry_latency(tp);
4902
4903 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4904
4905 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4906
4907 __rtl_hw_start_8168cp(tp);
4908}
4909
4910static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4911{
4912 static const struct ephy_info e_info_8168c_2[] = {
4913 { 0x01, 0, 0x0001 },
4914 { 0x03, 0x0400, 0x0220 }
4915 };
4916
4917 rtl_set_def_aspm_entry_latency(tp);
4918
4919 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4920
4921 __rtl_hw_start_8168cp(tp);
4922}
4923
4924static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4925{
4926 rtl_hw_start_8168c_2(tp);
4927}
4928
4929static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4930{
4931 rtl_set_def_aspm_entry_latency(tp);
4932
4933 __rtl_hw_start_8168cp(tp);
4934}
4935
4936static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4937{
4938 rtl_set_def_aspm_entry_latency(tp);
4939
4940 rtl_disable_clock_request(tp);
4941
4942 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4943
4944 if (tp->dev->mtu <= ETH_DATA_LEN)
4945 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4946
4947 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4948 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4949}
4950
4951static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4952{
4953 rtl_set_def_aspm_entry_latency(tp);
4954
4955 if (tp->dev->mtu <= ETH_DATA_LEN)
4956 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4957
4958 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4959
4960 rtl_disable_clock_request(tp);
4961}
4962
4963static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4964{
4965 static const struct ephy_info e_info_8168d_4[] = {
4966 { 0x0b, 0x0000, 0x0048 },
4967 { 0x19, 0x0020, 0x0050 },
4968 { 0x0c, 0x0100, 0x0020 }
4969 };
4970
4971 rtl_set_def_aspm_entry_latency(tp);
4972
4973 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4974
4975 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4976
4977 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4978
4979 rtl_enable_clock_request(tp);
4980}
4981
4982static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4983{
4984 static const struct ephy_info e_info_8168e_1[] = {
4985 { 0x00, 0x0200, 0x0100 },
4986 { 0x00, 0x0000, 0x0004 },
4987 { 0x06, 0x0002, 0x0001 },
4988 { 0x06, 0x0000, 0x0030 },
4989 { 0x07, 0x0000, 0x2000 },
4990 { 0x00, 0x0000, 0x0020 },
4991 { 0x03, 0x5800, 0x2000 },
4992 { 0x03, 0x0000, 0x0001 },
4993 { 0x01, 0x0800, 0x1000 },
4994 { 0x07, 0x0000, 0x4000 },
4995 { 0x1e, 0x0000, 0x2000 },
4996 { 0x19, 0xffff, 0xfe6c },
4997 { 0x0a, 0x0000, 0x0040 }
4998 };
4999
5000 rtl_set_def_aspm_entry_latency(tp);
5001
5002 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5003
5004 if (tp->dev->mtu <= ETH_DATA_LEN)
5005 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5006
5007 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5008
5009 rtl_disable_clock_request(tp);
5010
5011 /* Reset tx FIFO pointer */
5012 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5013 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5014
5015 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5016}
5017
5018static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5019{
5020 static const struct ephy_info e_info_8168e_2[] = {
5021 { 0x09, 0x0000, 0x0080 },
5022 { 0x19, 0x0000, 0x0224 }
5023 };
5024
5025 rtl_set_def_aspm_entry_latency(tp);
5026
5027 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5028
5029 if (tp->dev->mtu <= ETH_DATA_LEN)
5030 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5031
5032 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5033 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5034 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5035 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5036 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5037 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5038 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5039 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5040
5041 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5042
5043 rtl_disable_clock_request(tp);
5044
5045 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5046
5047 /* Adjust EEE LED frequency */
5048 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5049
5050 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5051 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5052 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5053
5054 rtl_hw_aspm_clkreq_enable(tp, true);
5055}
5056
5057static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5058{
5059 rtl_set_def_aspm_entry_latency(tp);
5060
5061 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5062
5063 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5064 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5065 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5066 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5067 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5068 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5069 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5070 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5071 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5072 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5073
5074 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5075
5076 rtl_disable_clock_request(tp);
5077
5078 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5079 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5080 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5081 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5082}
5083
5084static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5085{
5086 static const struct ephy_info e_info_8168f_1[] = {
5087 { 0x06, 0x00c0, 0x0020 },
5088 { 0x08, 0x0001, 0x0002 },
5089 { 0x09, 0x0000, 0x0080 },
5090 { 0x19, 0x0000, 0x0224 }
5091 };
5092
5093 rtl_hw_start_8168f(tp);
5094
5095 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5096
5097 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5098
5099 /* Adjust EEE LED frequency */
5100 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5101}
5102
5103static void rtl_hw_start_8411(struct rtl8169_private *tp)
5104{
5105 static const struct ephy_info e_info_8168f_1[] = {
5106 { 0x06, 0x00c0, 0x0020 },
5107 { 0x0f, 0xffff, 0x5200 },
5108 { 0x1e, 0x0000, 0x4000 },
5109 { 0x19, 0x0000, 0x0224 }
5110 };
5111
5112 rtl_hw_start_8168f(tp);
5113 rtl_pcie_state_l2l3_enable(tp, false);
5114
5115 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5116
5117 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5118}
5119
5120static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5121{
5122 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5123 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5124 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5125 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5126
5127 rtl_set_def_aspm_entry_latency(tp);
5128
5129 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5130
5131 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5132 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5133 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5134
5135 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5136 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5137
5138 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5139 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5140
5141 /* Adjust EEE LED frequency */
5142 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5143
5144 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5145 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5146
5147 rtl_pcie_state_l2l3_enable(tp, false);
5148}
5149
5150static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5151{
5152 static const struct ephy_info e_info_8168g_1[] = {
5153 { 0x00, 0x0000, 0x0008 },
5154 { 0x0c, 0x37d0, 0x0820 },
5155 { 0x1e, 0x0000, 0x0001 },
5156 { 0x19, 0x8000, 0x0000 }
5157 };
5158
5159 rtl_hw_start_8168g(tp);
5160
5161 /* disable aspm and clock request before access ephy */
5162 rtl_hw_aspm_clkreq_enable(tp, false);
5163 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5164 rtl_hw_aspm_clkreq_enable(tp, true);
5165}
5166
5167static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5168{
5169 static const struct ephy_info e_info_8168g_2[] = {
5170 { 0x00, 0x0000, 0x0008 },
5171 { 0x0c, 0x3df0, 0x0200 },
5172 { 0x19, 0xffff, 0xfc00 },
5173 { 0x1e, 0xffff, 0x20eb }
5174 };
5175
5176 rtl_hw_start_8168g(tp);
5177
5178 /* disable aspm and clock request before access ephy */
5179 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5180 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5181 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5182}
5183
5184static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5185{
5186 static const struct ephy_info e_info_8411_2[] = {
5187 { 0x00, 0x0000, 0x0008 },
5188 { 0x0c, 0x3df0, 0x0200 },
5189 { 0x0f, 0xffff, 0x5200 },
5190 { 0x19, 0x0020, 0x0000 },
5191 { 0x1e, 0x0000, 0x2000 }
5192 };
5193
5194 rtl_hw_start_8168g(tp);
5195
5196 /* disable aspm and clock request before access ephy */
5197 rtl_hw_aspm_clkreq_enable(tp, false);
5198 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5199 rtl_hw_aspm_clkreq_enable(tp, true);
5200}
5201
5202static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5203{
5204 int rg_saw_cnt;
5205 u32 data;
5206 static const struct ephy_info e_info_8168h_1[] = {
5207 { 0x1e, 0x0800, 0x0001 },
5208 { 0x1d, 0x0000, 0x0800 },
5209 { 0x05, 0xffff, 0x2089 },
5210 { 0x06, 0xffff, 0x5881 },
5211 { 0x04, 0xffff, 0x154a },
5212 { 0x01, 0xffff, 0x068b }
5213 };
5214
5215 /* disable aspm and clock request before access ephy */
5216 rtl_hw_aspm_clkreq_enable(tp, false);
5217 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5218
5219 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5220 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5221 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5222 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5223
5224 rtl_set_def_aspm_entry_latency(tp);
5225
5226 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5227
5228 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5229 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5230
5231 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5232
5233 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5234
5235 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5236
5237 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5238 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5239
5240 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5241 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5242
5243 /* Adjust EEE LED frequency */
5244 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5245
5246 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5247 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5248
5249 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5250
5251 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5252
5253 rtl_pcie_state_l2l3_enable(tp, false);
5254
5255 rtl_writephy(tp, 0x1f, 0x0c42);
5256 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5257 rtl_writephy(tp, 0x1f, 0x0000);
5258 if (rg_saw_cnt > 0) {
5259 u16 sw_cnt_1ms_ini;
5260
5261 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5262 sw_cnt_1ms_ini &= 0x0fff;
5263 data = r8168_mac_ocp_read(tp, 0xd412);
5264 data &= ~0x0fff;
5265 data |= sw_cnt_1ms_ini;
5266 r8168_mac_ocp_write(tp, 0xd412, data);
5267 }
5268
5269 data = r8168_mac_ocp_read(tp, 0xe056);
5270 data &= ~0xf0;
5271 data |= 0x70;
5272 r8168_mac_ocp_write(tp, 0xe056, data);
5273
5274 data = r8168_mac_ocp_read(tp, 0xe052);
5275 data &= ~0x6000;
5276 data |= 0x8008;
5277 r8168_mac_ocp_write(tp, 0xe052, data);
5278
5279 data = r8168_mac_ocp_read(tp, 0xe0d6);
5280 data &= ~0x01ff;
5281 data |= 0x017f;
5282 r8168_mac_ocp_write(tp, 0xe0d6, data);
5283
5284 data = r8168_mac_ocp_read(tp, 0xd420);
5285 data &= ~0x0fff;
5286 data |= 0x047f;
5287 r8168_mac_ocp_write(tp, 0xd420, data);
5288
5289 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5290 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5291 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5292 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5293
5294 rtl_hw_aspm_clkreq_enable(tp, true);
5295}
5296
5297static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5298{
5299 rtl8168ep_stop_cmac(tp);
5300
5301 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5302 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5303 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5304 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5305
5306 rtl_set_def_aspm_entry_latency(tp);
5307
5308 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5309
5310 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5311 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5312
5313 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5314
5315 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5316
5317 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5318 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5319
5320 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5321 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5322
5323 /* Adjust EEE LED frequency */
5324 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5325
5326 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5327
5328 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5329
5330 rtl_pcie_state_l2l3_enable(tp, false);
5331}
5332
5333static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5334{
5335 static const struct ephy_info e_info_8168ep_1[] = {
5336 { 0x00, 0xffff, 0x10ab },
5337 { 0x06, 0xffff, 0xf030 },
5338 { 0x08, 0xffff, 0x2006 },
5339 { 0x0d, 0xffff, 0x1666 },
5340 { 0x0c, 0x3ff0, 0x0000 }
5341 };
5342
5343 /* disable aspm and clock request before access ephy */
5344 rtl_hw_aspm_clkreq_enable(tp, false);
5345 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5346
5347 rtl_hw_start_8168ep(tp);
5348
5349 rtl_hw_aspm_clkreq_enable(tp, true);
5350}
5351
5352static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5353{
5354 static const struct ephy_info e_info_8168ep_2[] = {
5355 { 0x00, 0xffff, 0x10a3 },
5356 { 0x19, 0xffff, 0xfc00 },
5357 { 0x1e, 0xffff, 0x20ea }
5358 };
5359
5360 /* disable aspm and clock request before access ephy */
5361 rtl_hw_aspm_clkreq_enable(tp, false);
5362 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5363
5364 rtl_hw_start_8168ep(tp);
5365
5366 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5367 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5368
5369 rtl_hw_aspm_clkreq_enable(tp, true);
5370}
5371
5372static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5373{
5374 u32 data;
5375 static const struct ephy_info e_info_8168ep_3[] = {
5376 { 0x00, 0xffff, 0x10a3 },
5377 { 0x19, 0xffff, 0x7c00 },
5378 { 0x1e, 0xffff, 0x20eb },
5379 { 0x0d, 0xffff, 0x1666 }
5380 };
5381
5382 /* disable aspm and clock request before access ephy */
5383 rtl_hw_aspm_clkreq_enable(tp, false);
5384 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5385
5386 rtl_hw_start_8168ep(tp);
5387
5388 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5389 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5390
5391 data = r8168_mac_ocp_read(tp, 0xd3e2);
5392 data &= 0xf000;
5393 data |= 0x0271;
5394 r8168_mac_ocp_write(tp, 0xd3e2, data);
5395
5396 data = r8168_mac_ocp_read(tp, 0xd3e4);
5397 data &= 0xff00;
5398 r8168_mac_ocp_write(tp, 0xd3e4, data);
5399
5400 data = r8168_mac_ocp_read(tp, 0xe860);
5401 data |= 0x0080;
5402 r8168_mac_ocp_write(tp, 0xe860, data);
5403
5404 rtl_hw_aspm_clkreq_enable(tp, true);
5405}
5406
5407static void rtl_hw_start_8168(struct rtl8169_private *tp)
5408{
5409 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5410
5411 tp->cp_cmd &= ~INTT_MASK;
5412 tp->cp_cmd |= PktCntrDisable | INTT_1;
5413 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5414
5415 RTL_W16(tp, IntrMitigate, 0x5151);
5416
5417 /* Work around for RxFIFO overflow. */
5418 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5419 tp->event_slow |= RxFIFOOver | PCSTimeout;
5420 tp->event_slow &= ~RxOverflow;
5421 }
5422
5423 switch (tp->mac_version) {
5424 case RTL_GIGA_MAC_VER_11:
5425 rtl_hw_start_8168bb(tp);
5426 break;
5427
5428 case RTL_GIGA_MAC_VER_12:
5429 case RTL_GIGA_MAC_VER_17:
5430 rtl_hw_start_8168bef(tp);
5431 break;
5432
5433 case RTL_GIGA_MAC_VER_18:
5434 rtl_hw_start_8168cp_1(tp);
5435 break;
5436
5437 case RTL_GIGA_MAC_VER_19:
5438 rtl_hw_start_8168c_1(tp);
5439 break;
5440
5441 case RTL_GIGA_MAC_VER_20:
5442 rtl_hw_start_8168c_2(tp);
5443 break;
5444
5445 case RTL_GIGA_MAC_VER_21:
5446 rtl_hw_start_8168c_3(tp);
5447 break;
5448
5449 case RTL_GIGA_MAC_VER_22:
5450 rtl_hw_start_8168c_4(tp);
5451 break;
5452
5453 case RTL_GIGA_MAC_VER_23:
5454 rtl_hw_start_8168cp_2(tp);
5455 break;
5456
5457 case RTL_GIGA_MAC_VER_24:
5458 rtl_hw_start_8168cp_3(tp);
5459 break;
5460
5461 case RTL_GIGA_MAC_VER_25:
5462 case RTL_GIGA_MAC_VER_26:
5463 case RTL_GIGA_MAC_VER_27:
5464 rtl_hw_start_8168d(tp);
5465 break;
5466
5467 case RTL_GIGA_MAC_VER_28:
5468 rtl_hw_start_8168d_4(tp);
5469 break;
5470
5471 case RTL_GIGA_MAC_VER_31:
5472 rtl_hw_start_8168dp(tp);
5473 break;
5474
5475 case RTL_GIGA_MAC_VER_32:
5476 case RTL_GIGA_MAC_VER_33:
5477 rtl_hw_start_8168e_1(tp);
5478 break;
5479 case RTL_GIGA_MAC_VER_34:
5480 rtl_hw_start_8168e_2(tp);
5481 break;
5482
5483 case RTL_GIGA_MAC_VER_35:
5484 case RTL_GIGA_MAC_VER_36:
5485 rtl_hw_start_8168f_1(tp);
5486 break;
5487
5488 case RTL_GIGA_MAC_VER_38:
5489 rtl_hw_start_8411(tp);
5490 break;
5491
5492 case RTL_GIGA_MAC_VER_40:
5493 case RTL_GIGA_MAC_VER_41:
5494 rtl_hw_start_8168g_1(tp);
5495 break;
5496 case RTL_GIGA_MAC_VER_42:
5497 rtl_hw_start_8168g_2(tp);
5498 break;
5499
5500 case RTL_GIGA_MAC_VER_44:
5501 rtl_hw_start_8411_2(tp);
5502 break;
5503
5504 case RTL_GIGA_MAC_VER_45:
5505 case RTL_GIGA_MAC_VER_46:
5506 rtl_hw_start_8168h_1(tp);
5507 break;
5508
5509 case RTL_GIGA_MAC_VER_49:
5510 rtl_hw_start_8168ep_1(tp);
5511 break;
5512
5513 case RTL_GIGA_MAC_VER_50:
5514 rtl_hw_start_8168ep_2(tp);
5515 break;
5516
5517 case RTL_GIGA_MAC_VER_51:
5518 rtl_hw_start_8168ep_3(tp);
5519 break;
5520
5521 default:
5522 netif_err(tp, drv, tp->dev,
5523 "unknown chipset (mac_version = %d)\n",
5524 tp->mac_version);
5525 break;
5526 }
5527}
5528
5529static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5530{
5531 static const struct ephy_info e_info_8102e_1[] = {
5532 { 0x01, 0, 0x6e65 },
5533 { 0x02, 0, 0x091f },
5534 { 0x03, 0, 0xc2f9 },
5535 { 0x06, 0, 0xafb5 },
5536 { 0x07, 0, 0x0e00 },
5537 { 0x19, 0, 0xec80 },
5538 { 0x01, 0, 0x2e65 },
5539 { 0x01, 0, 0x6e65 }
5540 };
5541 u8 cfg1;
5542
5543 rtl_set_def_aspm_entry_latency(tp);
5544
5545 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5546
5547 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5548
5549 RTL_W8(tp, Config1,
5550 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5551 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5552
5553 cfg1 = RTL_R8(tp, Config1);
5554 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5555 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5556
5557 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5558}
5559
5560static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5561{
5562 rtl_set_def_aspm_entry_latency(tp);
5563
5564 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5565
5566 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5567 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5568}
5569
5570static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5571{
5572 rtl_hw_start_8102e_2(tp);
5573
5574 rtl_ephy_write(tp, 0x03, 0xc2f9);
5575}
5576
5577static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5578{
5579 static const struct ephy_info e_info_8105e_1[] = {
5580 { 0x07, 0, 0x4000 },
5581 { 0x19, 0, 0x0200 },
5582 { 0x19, 0, 0x0020 },
5583 { 0x1e, 0, 0x2000 },
5584 { 0x03, 0, 0x0001 },
5585 { 0x19, 0, 0x0100 },
5586 { 0x19, 0, 0x0004 },
5587 { 0x0a, 0, 0x0020 }
5588 };
5589
5590 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5591 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5592
5593 /* Disable Early Tally Counter */
5594 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5595
5596 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5597 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5598
5599 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5600
5601 rtl_pcie_state_l2l3_enable(tp, false);
5602}
5603
5604static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5605{
5606 rtl_hw_start_8105e_1(tp);
5607 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5608}
5609
5610static void rtl_hw_start_8402(struct rtl8169_private *tp)
5611{
5612 static const struct ephy_info e_info_8402[] = {
5613 { 0x19, 0xffff, 0xff64 },
5614 { 0x1e, 0, 0x4000 }
5615 };
5616
5617 rtl_set_def_aspm_entry_latency(tp);
5618
5619 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5620 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5621
5622 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5623
5624 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5625
5626 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5627
5628 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5629 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5630 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5631 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5632 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5633 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5634 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5635
5636 rtl_pcie_state_l2l3_enable(tp, false);
5637}
5638
5639static void rtl_hw_start_8106(struct rtl8169_private *tp)
5640{
5641 rtl_hw_aspm_clkreq_enable(tp, false);
5642
5643 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5644 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5645
5646 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5647 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5648 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5649
5650 rtl_pcie_state_l2l3_enable(tp, false);
5651 rtl_hw_aspm_clkreq_enable(tp, true);
5652}
5653
5654static void rtl_hw_start_8101(struct rtl8169_private *tp)
5655{
5656 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5657 tp->event_slow &= ~RxFIFOOver;
5658
5659 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5660 tp->mac_version == RTL_GIGA_MAC_VER_16)
5661 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5662 PCI_EXP_DEVCTL_NOSNOOP_EN);
5663
5664 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5665
5666 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5667 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5668
5669 switch (tp->mac_version) {
5670 case RTL_GIGA_MAC_VER_07:
5671 rtl_hw_start_8102e_1(tp);
5672 break;
5673
5674 case RTL_GIGA_MAC_VER_08:
5675 rtl_hw_start_8102e_3(tp);
5676 break;
5677
5678 case RTL_GIGA_MAC_VER_09:
5679 rtl_hw_start_8102e_2(tp);
5680 break;
5681
5682 case RTL_GIGA_MAC_VER_29:
5683 rtl_hw_start_8105e_1(tp);
5684 break;
5685 case RTL_GIGA_MAC_VER_30:
5686 rtl_hw_start_8105e_2(tp);
5687 break;
5688
5689 case RTL_GIGA_MAC_VER_37:
5690 rtl_hw_start_8402(tp);
5691 break;
5692
5693 case RTL_GIGA_MAC_VER_39:
5694 rtl_hw_start_8106(tp);
5695 break;
5696 case RTL_GIGA_MAC_VER_43:
5697 rtl_hw_start_8168g_2(tp);
5698 break;
5699 case RTL_GIGA_MAC_VER_47:
5700 case RTL_GIGA_MAC_VER_48:
5701 rtl_hw_start_8168h_1(tp);
5702 break;
5703 }
5704
5705 RTL_W16(tp, IntrMitigate, 0x0000);
5706}
5707
5708static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5709{
5710 struct rtl8169_private *tp = netdev_priv(dev);
5711
5712 if (new_mtu > ETH_DATA_LEN)
5713 rtl_hw_jumbo_enable(tp);
5714 else
5715 rtl_hw_jumbo_disable(tp);
5716
5717 dev->mtu = new_mtu;
5718 netdev_update_features(dev);
5719
5720 return 0;
5721}
5722
5723static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5724{
5725 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5726 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5727}
5728
5729static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5730 void **data_buff, struct RxDesc *desc)
5731{
5732 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5733 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5734
5735 kfree(*data_buff);
5736 *data_buff = NULL;
5737 rtl8169_make_unusable_by_asic(desc);
5738}
5739
5740static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5741{
5742 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5743
5744 /* Force memory writes to complete before releasing descriptor */
5745 dma_wmb();
5746
5747 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5748}
5749
5750static inline void *rtl8169_align(void *data)
5751{
5752 return (void *)ALIGN((long)data, 16);
5753}
5754
5755static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5756 struct RxDesc *desc)
5757{
5758 void *data;
5759 dma_addr_t mapping;
5760 struct device *d = tp_to_dev(tp);
5761 int node = dev_to_node(d);
5762
5763 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5764 if (!data)
5765 return NULL;
5766
5767 if (rtl8169_align(data) != data) {
5768 kfree(data);
5769 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5770 if (!data)
5771 return NULL;
5772 }
5773
5774 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5775 DMA_FROM_DEVICE);
5776 if (unlikely(dma_mapping_error(d, mapping))) {
5777 if (net_ratelimit())
5778 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5779 goto err_out;
5780 }
5781
5782 desc->addr = cpu_to_le64(mapping);
5783 rtl8169_mark_to_asic(desc);
5784 return data;
5785
5786err_out:
5787 kfree(data);
5788 return NULL;
5789}
5790
5791static void rtl8169_rx_clear(struct rtl8169_private *tp)
5792{
5793 unsigned int i;
5794
5795 for (i = 0; i < NUM_RX_DESC; i++) {
5796 if (tp->Rx_databuff[i]) {
5797 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5798 tp->RxDescArray + i);
5799 }
5800 }
5801}
5802
5803static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5804{
5805 desc->opts1 |= cpu_to_le32(RingEnd);
5806}
5807
5808static int rtl8169_rx_fill(struct rtl8169_private *tp)
5809{
5810 unsigned int i;
5811
5812 for (i = 0; i < NUM_RX_DESC; i++) {
5813 void *data;
5814
5815 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5816 if (!data) {
5817 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5818 goto err_out;
5819 }
5820 tp->Rx_databuff[i] = data;
5821 }
5822
5823 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5824 return 0;
5825
5826err_out:
5827 rtl8169_rx_clear(tp);
5828 return -ENOMEM;
5829}
5830
5831static int rtl8169_init_ring(struct rtl8169_private *tp)
5832{
5833 rtl8169_init_ring_indexes(tp);
5834
5835 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5836 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5837
5838 return rtl8169_rx_fill(tp);
5839}
5840
5841static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5842 struct TxDesc *desc)
5843{
5844 unsigned int len = tx_skb->len;
5845
5846 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5847
5848 desc->opts1 = 0x00;
5849 desc->opts2 = 0x00;
5850 desc->addr = 0x00;
5851 tx_skb->len = 0;
5852}
5853
5854static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
5855 unsigned int n)
5856{
5857 unsigned int i;
5858
5859 for (i = 0; i < n; i++) {
5860 unsigned int entry = (start + i) % NUM_TX_DESC;
5861 struct ring_info *tx_skb = tp->tx_skb + entry;
5862 unsigned int len = tx_skb->len;
5863
5864 if (len) {
5865 struct sk_buff *skb = tx_skb->skb;
5866
5867 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
5868 tp->TxDescArray + entry);
5869 if (skb) {
5870 dev_consume_skb_any(skb);
5871 tx_skb->skb = NULL;
5872 }
5873 }
5874 }
5875}
5876
5877static void rtl8169_tx_clear(struct rtl8169_private *tp)
5878{
5879 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
5880 tp->cur_tx = tp->dirty_tx = 0;
5881}
5882
5883static void rtl_reset_work(struct rtl8169_private *tp)
5884{
5885 struct net_device *dev = tp->dev;
5886 int i;
5887
5888 napi_disable(&tp->napi);
5889 netif_stop_queue(dev);
5890 synchronize_sched();
5891
5892 rtl8169_hw_reset(tp);
5893
5894 for (i = 0; i < NUM_RX_DESC; i++)
5895 rtl8169_mark_to_asic(tp->RxDescArray + i);
5896
5897 rtl8169_tx_clear(tp);
5898 rtl8169_init_ring_indexes(tp);
5899
5900 napi_enable(&tp->napi);
5901 rtl_hw_start(tp);
5902 netif_wake_queue(dev);
5903}
5904
5905static void rtl8169_tx_timeout(struct net_device *dev)
5906{
5907 struct rtl8169_private *tp = netdev_priv(dev);
5908
5909 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
5910}
5911
5912static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
5913 u32 *opts)
5914{
5915 struct skb_shared_info *info = skb_shinfo(skb);
5916 unsigned int cur_frag, entry;
5917 struct TxDesc *uninitialized_var(txd);
5918 struct device *d = tp_to_dev(tp);
5919
5920 entry = tp->cur_tx;
5921 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5922 const skb_frag_t *frag = info->frags + cur_frag;
5923 dma_addr_t mapping;
5924 u32 status, len;
5925 void *addr;
5926
5927 entry = (entry + 1) % NUM_TX_DESC;
5928
5929 txd = tp->TxDescArray + entry;
5930 len = skb_frag_size(frag);
5931 addr = skb_frag_address(frag);
5932 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
5933 if (unlikely(dma_mapping_error(d, mapping))) {
5934 if (net_ratelimit())
5935 netif_err(tp, drv, tp->dev,
5936 "Failed to map TX fragments DMA!\n");
5937 goto err_out;
5938 }
5939
5940 /* Anti gcc 2.95.3 bugware (sic) */
5941 status = opts[0] | len |
5942 (RingEnd * !((entry + 1) % NUM_TX_DESC));
5943
5944 txd->opts1 = cpu_to_le32(status);
5945 txd->opts2 = cpu_to_le32(opts[1]);
5946 txd->addr = cpu_to_le64(mapping);
5947
5948 tp->tx_skb[entry].len = len;
5949 }
5950
5951 if (cur_frag) {
5952 tp->tx_skb[entry].skb = skb;
5953 txd->opts1 |= cpu_to_le32(LastFrag);
5954 }
5955
5956 return cur_frag;
5957
5958err_out:
5959 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5960 return -EIO;
5961}
5962
5963static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
5964{
5965 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
5966}
5967
5968static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5969 struct net_device *dev);
5970/* r8169_csum_workaround()
5971 * The hw limites the value the transport offset. When the offset is out of the
5972 * range, calculate the checksum by sw.
5973 */
5974static void r8169_csum_workaround(struct rtl8169_private *tp,
5975 struct sk_buff *skb)
5976{
5977 if (skb_shinfo(skb)->gso_size) {
5978 netdev_features_t features = tp->dev->features;
5979 struct sk_buff *segs, *nskb;
5980
5981 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
5982 segs = skb_gso_segment(skb, features);
5983 if (IS_ERR(segs) || !segs)
5984 goto drop;
5985
5986 do {
5987 nskb = segs;
5988 segs = segs->next;
5989 nskb->next = NULL;
5990 rtl8169_start_xmit(nskb, tp->dev);
5991 } while (segs);
5992
5993 dev_consume_skb_any(skb);
5994 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5995 if (skb_checksum_help(skb) < 0)
5996 goto drop;
5997
5998 rtl8169_start_xmit(skb, tp->dev);
5999 } else {
6000 struct net_device_stats *stats;
6001
6002drop:
6003 stats = &tp->dev->stats;
6004 stats->tx_dropped++;
6005 dev_kfree_skb_any(skb);
6006 }
6007}
6008
6009/* msdn_giant_send_check()
6010 * According to the document of microsoft, the TCP Pseudo Header excludes the
6011 * packet length for IPv6 TCP large packets.
6012 */
6013static int msdn_giant_send_check(struct sk_buff *skb)
6014{
6015 const struct ipv6hdr *ipv6h;
6016 struct tcphdr *th;
6017 int ret;
6018
6019 ret = skb_cow_head(skb, 0);
6020 if (ret)
6021 return ret;
6022
6023 ipv6h = ipv6_hdr(skb);
6024 th = tcp_hdr(skb);
6025
6026 th->check = 0;
6027 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6028
6029 return ret;
6030}
6031
6032static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6033 struct sk_buff *skb, u32 *opts)
6034{
6035 u32 mss = skb_shinfo(skb)->gso_size;
6036
6037 if (mss) {
6038 opts[0] |= TD_LSO;
6039 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6040 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6041 const struct iphdr *ip = ip_hdr(skb);
6042
6043 if (ip->protocol == IPPROTO_TCP)
6044 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6045 else if (ip->protocol == IPPROTO_UDP)
6046 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6047 else
6048 WARN_ON_ONCE(1);
6049 }
6050
6051 return true;
6052}
6053
6054static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6055 struct sk_buff *skb, u32 *opts)
6056{
6057 u32 transport_offset = (u32)skb_transport_offset(skb);
6058 u32 mss = skb_shinfo(skb)->gso_size;
6059
6060 if (mss) {
6061 if (transport_offset > GTTCPHO_MAX) {
6062 netif_warn(tp, tx_err, tp->dev,
6063 "Invalid transport offset 0x%x for TSO\n",
6064 transport_offset);
6065 return false;
6066 }
6067
6068 switch (vlan_get_protocol(skb)) {
6069 case htons(ETH_P_IP):
6070 opts[0] |= TD1_GTSENV4;
6071 break;
6072
6073 case htons(ETH_P_IPV6):
6074 if (msdn_giant_send_check(skb))
6075 return false;
6076
6077 opts[0] |= TD1_GTSENV6;
6078 break;
6079
6080 default:
6081 WARN_ON_ONCE(1);
6082 break;
6083 }
6084
6085 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6086 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6087 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6088 u8 ip_protocol;
6089
6090 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6091 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6092
6093 if (transport_offset > TCPHO_MAX) {
6094 netif_warn(tp, tx_err, tp->dev,
6095 "Invalid transport offset 0x%x\n",
6096 transport_offset);
6097 return false;
6098 }
6099
6100 switch (vlan_get_protocol(skb)) {
6101 case htons(ETH_P_IP):
6102 opts[1] |= TD1_IPv4_CS;
6103 ip_protocol = ip_hdr(skb)->protocol;
6104 break;
6105
6106 case htons(ETH_P_IPV6):
6107 opts[1] |= TD1_IPv6_CS;
6108 ip_protocol = ipv6_hdr(skb)->nexthdr;
6109 break;
6110
6111 default:
6112 ip_protocol = IPPROTO_RAW;
6113 break;
6114 }
6115
6116 if (ip_protocol == IPPROTO_TCP)
6117 opts[1] |= TD1_TCP_CS;
6118 else if (ip_protocol == IPPROTO_UDP)
6119 opts[1] |= TD1_UDP_CS;
6120 else
6121 WARN_ON_ONCE(1);
6122
6123 opts[1] |= transport_offset << TCPHO_SHIFT;
6124 } else {
6125 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6126 return !eth_skb_pad(skb);
6127 }
6128
6129 return true;
6130}
6131
6132static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6133 struct net_device *dev)
6134{
6135 struct rtl8169_private *tp = netdev_priv(dev);
6136 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6137 struct TxDesc *txd = tp->TxDescArray + entry;
6138 struct device *d = tp_to_dev(tp);
6139 dma_addr_t mapping;
6140 u32 status, len;
6141 u32 opts[2];
6142 int frags;
6143
6144 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6145 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6146 goto err_stop_0;
6147 }
6148
6149 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6150 goto err_stop_0;
6151
6152 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6153 opts[0] = DescOwn;
6154
6155 if (!tp->tso_csum(tp, skb, opts)) {
6156 r8169_csum_workaround(tp, skb);
6157 return NETDEV_TX_OK;
6158 }
6159
6160 len = skb_headlen(skb);
6161 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6162 if (unlikely(dma_mapping_error(d, mapping))) {
6163 if (net_ratelimit())
6164 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6165 goto err_dma_0;
6166 }
6167
6168 tp->tx_skb[entry].len = len;
6169 txd->addr = cpu_to_le64(mapping);
6170
6171 frags = rtl8169_xmit_frags(tp, skb, opts);
6172 if (frags < 0)
6173 goto err_dma_1;
6174 else if (frags)
6175 opts[0] |= FirstFrag;
6176 else {
6177 opts[0] |= FirstFrag | LastFrag;
6178 tp->tx_skb[entry].skb = skb;
6179 }
6180
6181 txd->opts2 = cpu_to_le32(opts[1]);
6182
6183 skb_tx_timestamp(skb);
6184
6185 /* Force memory writes to complete before releasing descriptor */
6186 dma_wmb();
6187
6188 /* Anti gcc 2.95.3 bugware (sic) */
6189 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6190 txd->opts1 = cpu_to_le32(status);
6191
6192 /* Force all memory writes to complete before notifying device */
6193 wmb();
6194
6195 tp->cur_tx += frags + 1;
6196
6197 RTL_W8(tp, TxPoll, NPQ);
6198
6199 mmiowb();
6200
6201 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6202 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6203 * not miss a ring update when it notices a stopped queue.
6204 */
6205 smp_wmb();
6206 netif_stop_queue(dev);
6207 /* Sync with rtl_tx:
6208 * - publish queue status and cur_tx ring index (write barrier)
6209 * - refresh dirty_tx ring index (read barrier).
6210 * May the current thread have a pessimistic view of the ring
6211 * status and forget to wake up queue, a racing rtl_tx thread
6212 * can't.
6213 */
6214 smp_mb();
6215 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6216 netif_wake_queue(dev);
6217 }
6218
6219 return NETDEV_TX_OK;
6220
6221err_dma_1:
6222 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6223err_dma_0:
6224 dev_kfree_skb_any(skb);
6225 dev->stats.tx_dropped++;
6226 return NETDEV_TX_OK;
6227
6228err_stop_0:
6229 netif_stop_queue(dev);
6230 dev->stats.tx_dropped++;
6231 return NETDEV_TX_BUSY;
6232}
6233
6234static void rtl8169_pcierr_interrupt(struct net_device *dev)
6235{
6236 struct rtl8169_private *tp = netdev_priv(dev);
6237 struct pci_dev *pdev = tp->pci_dev;
6238 u16 pci_status, pci_cmd;
6239
6240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6242
6243 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6244 pci_cmd, pci_status);
6245
6246 /*
6247 * The recovery sequence below admits a very elaborated explanation:
6248 * - it seems to work;
6249 * - I did not see what else could be done;
6250 * - it makes iop3xx happy.
6251 *
6252 * Feel free to adjust to your needs.
6253 */
6254 if (pdev->broken_parity_status)
6255 pci_cmd &= ~PCI_COMMAND_PARITY;
6256 else
6257 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6258
6259 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6260
6261 pci_write_config_word(pdev, PCI_STATUS,
6262 pci_status & (PCI_STATUS_DETECTED_PARITY |
6263 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6264 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6265
6266 /* The infamous DAC f*ckup only happens at boot time */
6267 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6268 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6269 tp->cp_cmd &= ~PCIDAC;
6270 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6271 dev->features &= ~NETIF_F_HIGHDMA;
6272 }
6273
6274 rtl8169_hw_reset(tp);
6275
6276 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6277}
6278
6279static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6280{
6281 unsigned int dirty_tx, tx_left;
6282
6283 dirty_tx = tp->dirty_tx;
6284 smp_rmb();
6285 tx_left = tp->cur_tx - dirty_tx;
6286
6287 while (tx_left > 0) {
6288 unsigned int entry = dirty_tx % NUM_TX_DESC;
6289 struct ring_info *tx_skb = tp->tx_skb + entry;
6290 u32 status;
6291
6292 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6293 if (status & DescOwn)
6294 break;
6295
6296 /* This barrier is needed to keep us from reading
6297 * any other fields out of the Tx descriptor until
6298 * we know the status of DescOwn
6299 */
6300 dma_rmb();
6301
6302 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6303 tp->TxDescArray + entry);
6304 if (status & LastFrag) {
6305 u64_stats_update_begin(&tp->tx_stats.syncp);
6306 tp->tx_stats.packets++;
6307 tp->tx_stats.bytes += tx_skb->skb->len;
6308 u64_stats_update_end(&tp->tx_stats.syncp);
6309 dev_consume_skb_any(tx_skb->skb);
6310 tx_skb->skb = NULL;
6311 }
6312 dirty_tx++;
6313 tx_left--;
6314 }
6315
6316 if (tp->dirty_tx != dirty_tx) {
6317 tp->dirty_tx = dirty_tx;
6318 /* Sync with rtl8169_start_xmit:
6319 * - publish dirty_tx ring index (write barrier)
6320 * - refresh cur_tx ring index and queue status (read barrier)
6321 * May the current thread miss the stopped queue condition,
6322 * a racing xmit thread can only have a right view of the
6323 * ring status.
6324 */
6325 smp_mb();
6326 if (netif_queue_stopped(dev) &&
6327 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6328 netif_wake_queue(dev);
6329 }
6330 /*
6331 * 8168 hack: TxPoll requests are lost when the Tx packets are
6332 * too close. Let's kick an extra TxPoll request when a burst
6333 * of start_xmit activity is detected (if it is not detected,
6334 * it is slow enough). -- FR
6335 */
6336 if (tp->cur_tx != dirty_tx)
6337 RTL_W8(tp, TxPoll, NPQ);
6338 }
6339}
6340
6341static inline int rtl8169_fragmented_frame(u32 status)
6342{
6343 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6344}
6345
6346static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6347{
6348 u32 status = opts1 & RxProtoMask;
6349
6350 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6351 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6352 skb->ip_summed = CHECKSUM_UNNECESSARY;
6353 else
6354 skb_checksum_none_assert(skb);
6355}
6356
6357static struct sk_buff *rtl8169_try_rx_copy(void *data,
6358 struct rtl8169_private *tp,
6359 int pkt_size,
6360 dma_addr_t addr)
6361{
6362 struct sk_buff *skb;
6363 struct device *d = tp_to_dev(tp);
6364
6365 data = rtl8169_align(data);
6366 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6367 prefetch(data);
6368 skb = napi_alloc_skb(&tp->napi, pkt_size);
6369 if (skb)
6370 skb_copy_to_linear_data(skb, data, pkt_size);
6371 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6372
6373 return skb;
6374}
6375
6376static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6377{
6378 unsigned int cur_rx, rx_left;
6379 unsigned int count;
6380
6381 cur_rx = tp->cur_rx;
6382
6383 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6384 unsigned int entry = cur_rx % NUM_RX_DESC;
6385 struct RxDesc *desc = tp->RxDescArray + entry;
6386 u32 status;
6387
6388 status = le32_to_cpu(desc->opts1);
6389 if (status & DescOwn)
6390 break;
6391
6392 /* This barrier is needed to keep us from reading
6393 * any other fields out of the Rx descriptor until
6394 * we know the status of DescOwn
6395 */
6396 dma_rmb();
6397
6398 if (unlikely(status & RxRES)) {
6399 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6400 status);
6401 dev->stats.rx_errors++;
6402 if (status & (RxRWT | RxRUNT))
6403 dev->stats.rx_length_errors++;
6404 if (status & RxCRC)
6405 dev->stats.rx_crc_errors++;
6406 /* RxFOVF is a reserved bit on later chip versions */
6407 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6408 status & RxFOVF) {
6409 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6410 dev->stats.rx_fifo_errors++;
6411 } else if (status & (RxRUNT | RxCRC) &&
6412 !(status & RxRWT) &&
6413 dev->features & NETIF_F_RXALL) {
6414 goto process_pkt;
6415 }
6416 } else {
6417 struct sk_buff *skb;
6418 dma_addr_t addr;
6419 int pkt_size;
6420
6421process_pkt:
6422 addr = le64_to_cpu(desc->addr);
6423 if (likely(!(dev->features & NETIF_F_RXFCS)))
6424 pkt_size = (status & 0x00003fff) - 4;
6425 else
6426 pkt_size = status & 0x00003fff;
6427
6428 /*
6429 * The driver does not support incoming fragmented
6430 * frames. They are seen as a symptom of over-mtu
6431 * sized frames.
6432 */
6433 if (unlikely(rtl8169_fragmented_frame(status))) {
6434 dev->stats.rx_dropped++;
6435 dev->stats.rx_length_errors++;
6436 goto release_descriptor;
6437 }
6438
6439 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6440 tp, pkt_size, addr);
6441 if (!skb) {
6442 dev->stats.rx_dropped++;
6443 goto release_descriptor;
6444 }
6445
6446 rtl8169_rx_csum(skb, status);
6447 skb_put(skb, pkt_size);
6448 skb->protocol = eth_type_trans(skb, dev);
6449
6450 rtl8169_rx_vlan_tag(desc, skb);
6451
6452 if (skb->pkt_type == PACKET_MULTICAST)
6453 dev->stats.multicast++;
6454
6455 napi_gro_receive(&tp->napi, skb);
6456
6457 u64_stats_update_begin(&tp->rx_stats.syncp);
6458 tp->rx_stats.packets++;
6459 tp->rx_stats.bytes += pkt_size;
6460 u64_stats_update_end(&tp->rx_stats.syncp);
6461 }
6462release_descriptor:
6463 desc->opts2 = 0;
6464 rtl8169_mark_to_asic(desc);
6465 }
6466
6467 count = cur_rx - tp->cur_rx;
6468 tp->cur_rx = cur_rx;
6469
6470 return count;
6471}
6472
6473static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6474{
6475 struct rtl8169_private *tp = dev_instance;
6476 u16 status = rtl_get_events(tp);
6477
6478 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6479 return IRQ_NONE;
6480
6481 rtl_irq_disable(tp);
6482 napi_schedule_irqoff(&tp->napi);
6483
6484 return IRQ_HANDLED;
6485}
6486
6487/*
6488 * Workqueue context.
6489 */
6490static void rtl_slow_event_work(struct rtl8169_private *tp)
6491{
6492 struct net_device *dev = tp->dev;
6493 u16 status;
6494
6495 status = rtl_get_events(tp) & tp->event_slow;
6496 rtl_ack_events(tp, status);
6497
6498 if (unlikely(status & RxFIFOOver)) {
6499 switch (tp->mac_version) {
6500 /* Work around for rx fifo overflow */
6501 case RTL_GIGA_MAC_VER_11:
6502 netif_stop_queue(dev);
6503 /* XXX - Hack alert. See rtl_task(). */
6504 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6505 default:
6506 break;
6507 }
6508 }
6509
6510 if (unlikely(status & SYSErr))
6511 rtl8169_pcierr_interrupt(dev);
6512
6513 if (status & LinkChg)
6514 phy_mac_interrupt(dev->phydev);
6515
6516 rtl_irq_enable_all(tp);
6517}
6518
6519static void rtl_task(struct work_struct *work)
6520{
6521 static const struct {
6522 int bitnr;
6523 void (*action)(struct rtl8169_private *);
6524 } rtl_work[] = {
6525 /* XXX - keep rtl_slow_event_work() as first element. */
6526 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6527 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6528 };
6529 struct rtl8169_private *tp =
6530 container_of(work, struct rtl8169_private, wk.work);
6531 struct net_device *dev = tp->dev;
6532 int i;
6533
6534 rtl_lock_work(tp);
6535
6536 if (!netif_running(dev) ||
6537 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6538 goto out_unlock;
6539
6540 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6541 bool pending;
6542
6543 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6544 if (pending)
6545 rtl_work[i].action(tp);
6546 }
6547
6548out_unlock:
6549 rtl_unlock_work(tp);
6550}
6551
6552static int rtl8169_poll(struct napi_struct *napi, int budget)
6553{
6554 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6555 struct net_device *dev = tp->dev;
6556 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6557 int work_done;
6558 u16 status;
6559
6560 status = rtl_get_events(tp);
6561 rtl_ack_events(tp, status & ~tp->event_slow);
6562
6563 work_done = rtl_rx(dev, tp, (u32) budget);
6564
6565 rtl_tx(dev, tp);
6566
6567 if (status & tp->event_slow) {
6568 enable_mask &= ~tp->event_slow;
6569
6570 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6571 }
6572
6573 if (work_done < budget) {
6574 napi_complete_done(napi, work_done);
6575
6576 rtl_irq_enable(tp, enable_mask);
6577 mmiowb();
6578 }
6579
6580 return work_done;
6581}
6582
6583static void rtl8169_rx_missed(struct net_device *dev)
6584{
6585 struct rtl8169_private *tp = netdev_priv(dev);
6586
6587 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6588 return;
6589
6590 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6591 RTL_W32(tp, RxMissed, 0);
6592}
6593
6594static void r8169_phylink_handler(struct net_device *ndev)
6595{
6596 struct rtl8169_private *tp = netdev_priv(ndev);
6597
6598 if (netif_carrier_ok(ndev)) {
6599 rtl_link_chg_patch(tp);
6600 pm_request_resume(&tp->pci_dev->dev);
6601 } else {
6602 pm_runtime_idle(&tp->pci_dev->dev);
6603 }
6604
6605 if (net_ratelimit())
6606 phy_print_status(ndev->phydev);
6607}
6608
6609static int r8169_phy_connect(struct rtl8169_private *tp)
6610{
6611 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6612 phy_interface_t phy_mode;
6613 int ret;
6614
6615 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6616 PHY_INTERFACE_MODE_MII;
6617
6618 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6619 phy_mode);
6620 if (ret)
6621 return ret;
6622
6623 if (!tp->supports_gmii)
6624 phy_set_max_speed(phydev, SPEED_100);
6625
6626 /* Ensure to advertise everything, incl. pause */
6627 phydev->advertising = phydev->supported;
6628
6629 phy_attached_info(phydev);
6630
6631 return 0;
6632}
6633
6634static void rtl8169_down(struct net_device *dev)
6635{
6636 struct rtl8169_private *tp = netdev_priv(dev);
6637
6638 phy_stop(dev->phydev);
6639
6640 napi_disable(&tp->napi);
6641 netif_stop_queue(dev);
6642
6643 rtl8169_hw_reset(tp);
6644 /*
6645 * At this point device interrupts can not be enabled in any function,
6646 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6647 * and napi is disabled (rtl8169_poll).
6648 */
6649 rtl8169_rx_missed(dev);
6650
6651 /* Give a racing hard_start_xmit a few cycles to complete. */
6652 synchronize_sched();
6653
6654 rtl8169_tx_clear(tp);
6655
6656 rtl8169_rx_clear(tp);
6657
6658 rtl_pll_power_down(tp);
6659}
6660
6661static int rtl8169_close(struct net_device *dev)
6662{
6663 struct rtl8169_private *tp = netdev_priv(dev);
6664 struct pci_dev *pdev = tp->pci_dev;
6665
6666 pm_runtime_get_sync(&pdev->dev);
6667
6668 /* Update counters before going down */
6669 rtl8169_update_counters(tp);
6670
6671 rtl_lock_work(tp);
6672 /* Clear all task flags */
6673 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6674
6675 rtl8169_down(dev);
6676 rtl_unlock_work(tp);
6677
6678 cancel_work_sync(&tp->wk.work);
6679
6680 phy_disconnect(dev->phydev);
6681
6682 pci_free_irq(pdev, 0, tp);
6683
6684 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6685 tp->RxPhyAddr);
6686 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6687 tp->TxPhyAddr);
6688 tp->TxDescArray = NULL;
6689 tp->RxDescArray = NULL;
6690
6691 pm_runtime_put_sync(&pdev->dev);
6692
6693 return 0;
6694}
6695
6696#ifdef CONFIG_NET_POLL_CONTROLLER
6697static void rtl8169_netpoll(struct net_device *dev)
6698{
6699 struct rtl8169_private *tp = netdev_priv(dev);
6700
6701 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6702}
6703#endif
6704
6705static int rtl_open(struct net_device *dev)
6706{
6707 struct rtl8169_private *tp = netdev_priv(dev);
6708 struct pci_dev *pdev = tp->pci_dev;
6709 int retval = -ENOMEM;
6710
6711 pm_runtime_get_sync(&pdev->dev);
6712
6713 /*
6714 * Rx and Tx descriptors needs 256 bytes alignment.
6715 * dma_alloc_coherent provides more.
6716 */
6717 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6718 &tp->TxPhyAddr, GFP_KERNEL);
6719 if (!tp->TxDescArray)
6720 goto err_pm_runtime_put;
6721
6722 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6723 &tp->RxPhyAddr, GFP_KERNEL);
6724 if (!tp->RxDescArray)
6725 goto err_free_tx_0;
6726
6727 retval = rtl8169_init_ring(tp);
6728 if (retval < 0)
6729 goto err_free_rx_1;
6730
6731 INIT_WORK(&tp->wk.work, rtl_task);
6732
6733 smp_mb();
6734
6735 rtl_request_firmware(tp);
6736
6737 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
6738 dev->name);
6739 if (retval < 0)
6740 goto err_release_fw_2;
6741
6742 retval = r8169_phy_connect(tp);
6743 if (retval)
6744 goto err_free_irq;
6745
6746 rtl_lock_work(tp);
6747
6748 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6749
6750 napi_enable(&tp->napi);
6751
6752 rtl8169_init_phy(dev, tp);
6753
6754 rtl_pll_power_up(tp);
6755
6756 rtl_hw_start(tp);
6757
6758 if (!rtl8169_init_counter_offsets(tp))
6759 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6760
6761 phy_start(dev->phydev);
6762 netif_start_queue(dev);
6763
6764 rtl_unlock_work(tp);
6765
6766 pm_runtime_put_sync(&pdev->dev);
6767out:
6768 return retval;
6769
6770err_free_irq:
6771 pci_free_irq(pdev, 0, tp);
6772err_release_fw_2:
6773 rtl_release_firmware(tp);
6774 rtl8169_rx_clear(tp);
6775err_free_rx_1:
6776 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6777 tp->RxPhyAddr);
6778 tp->RxDescArray = NULL;
6779err_free_tx_0:
6780 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6781 tp->TxPhyAddr);
6782 tp->TxDescArray = NULL;
6783err_pm_runtime_put:
6784 pm_runtime_put_noidle(&pdev->dev);
6785 goto out;
6786}
6787
6788static void
6789rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6790{
6791 struct rtl8169_private *tp = netdev_priv(dev);
6792 struct pci_dev *pdev = tp->pci_dev;
6793 struct rtl8169_counters *counters = tp->counters;
6794 unsigned int start;
6795
6796 pm_runtime_get_noresume(&pdev->dev);
6797
6798 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6799 rtl8169_rx_missed(dev);
6800
6801 do {
6802 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6803 stats->rx_packets = tp->rx_stats.packets;
6804 stats->rx_bytes = tp->rx_stats.bytes;
6805 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6806
6807 do {
6808 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6809 stats->tx_packets = tp->tx_stats.packets;
6810 stats->tx_bytes = tp->tx_stats.bytes;
6811 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6812
6813 stats->rx_dropped = dev->stats.rx_dropped;
6814 stats->tx_dropped = dev->stats.tx_dropped;
6815 stats->rx_length_errors = dev->stats.rx_length_errors;
6816 stats->rx_errors = dev->stats.rx_errors;
6817 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6818 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6819 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6820 stats->multicast = dev->stats.multicast;
6821
6822 /*
6823 * Fetch additonal counter values missing in stats collected by driver
6824 * from tally counters.
6825 */
6826 if (pm_runtime_active(&pdev->dev))
6827 rtl8169_update_counters(tp);
6828
6829 /*
6830 * Subtract values fetched during initalization.
6831 * See rtl8169_init_counter_offsets for a description why we do that.
6832 */
6833 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6834 le64_to_cpu(tp->tc_offset.tx_errors);
6835 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6836 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6837 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6838 le16_to_cpu(tp->tc_offset.tx_aborted);
6839
6840 pm_runtime_put_noidle(&pdev->dev);
6841}
6842
6843static void rtl8169_net_suspend(struct net_device *dev)
6844{
6845 struct rtl8169_private *tp = netdev_priv(dev);
6846
6847 if (!netif_running(dev))
6848 return;
6849
6850 phy_stop(dev->phydev);
6851 netif_device_detach(dev);
6852 netif_stop_queue(dev);
6853
6854 rtl_lock_work(tp);
6855 napi_disable(&tp->napi);
6856 /* Clear all task flags */
6857 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6858
6859 rtl_unlock_work(tp);
6860
6861 rtl_pll_power_down(tp);
6862}
6863
6864#ifdef CONFIG_PM
6865
6866static int rtl8169_suspend(struct device *device)
6867{
6868 struct pci_dev *pdev = to_pci_dev(device);
6869 struct net_device *dev = pci_get_drvdata(pdev);
6870 struct rtl8169_private *tp = netdev_priv(dev);
6871
6872 rtl8169_net_suspend(dev);
6873 clk_disable_unprepare(tp->clk);
6874
6875 return 0;
6876}
6877
6878static void __rtl8169_resume(struct net_device *dev)
6879{
6880 struct rtl8169_private *tp = netdev_priv(dev);
6881
6882 netif_device_attach(dev);
6883
6884 rtl_pll_power_up(tp);
6885 rtl8169_init_phy(dev, tp);
6886
6887 phy_start(tp->dev->phydev);
6888
6889 rtl_lock_work(tp);
6890 napi_enable(&tp->napi);
6891 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6892 rtl_unlock_work(tp);
6893
6894 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6895}
6896
6897static int rtl8169_resume(struct device *device)
6898{
6899 struct pci_dev *pdev = to_pci_dev(device);
6900 struct net_device *dev = pci_get_drvdata(pdev);
6901 struct rtl8169_private *tp = netdev_priv(dev);
6902
6903 clk_prepare_enable(tp->clk);
6904
6905 if (netif_running(dev))
6906 __rtl8169_resume(dev);
6907
6908 return 0;
6909}
6910
6911static int rtl8169_runtime_suspend(struct device *device)
6912{
6913 struct pci_dev *pdev = to_pci_dev(device);
6914 struct net_device *dev = pci_get_drvdata(pdev);
6915 struct rtl8169_private *tp = netdev_priv(dev);
6916
6917 if (!tp->TxDescArray)
6918 return 0;
6919
6920 rtl_lock_work(tp);
6921 __rtl8169_set_wol(tp, WAKE_ANY);
6922 rtl_unlock_work(tp);
6923
6924 rtl8169_net_suspend(dev);
6925
6926 /* Update counters before going runtime suspend */
6927 rtl8169_rx_missed(dev);
6928 rtl8169_update_counters(tp);
6929
6930 return 0;
6931}
6932
6933static int rtl8169_runtime_resume(struct device *device)
6934{
6935 struct pci_dev *pdev = to_pci_dev(device);
6936 struct net_device *dev = pci_get_drvdata(pdev);
6937 struct rtl8169_private *tp = netdev_priv(dev);
6938 rtl_rar_set(tp, dev->dev_addr);
6939
6940 if (!tp->TxDescArray)
6941 return 0;
6942
6943 rtl_lock_work(tp);
6944 __rtl8169_set_wol(tp, tp->saved_wolopts);
6945 rtl_unlock_work(tp);
6946
6947 __rtl8169_resume(dev);
6948
6949 return 0;
6950}
6951
6952static int rtl8169_runtime_idle(struct device *device)
6953{
6954 struct pci_dev *pdev = to_pci_dev(device);
6955 struct net_device *dev = pci_get_drvdata(pdev);
6956
6957 if (!netif_running(dev) || !netif_carrier_ok(dev))
6958 pm_schedule_suspend(device, 10000);
6959
6960 return -EBUSY;
6961}
6962
6963static const struct dev_pm_ops rtl8169_pm_ops = {
6964 .suspend = rtl8169_suspend,
6965 .resume = rtl8169_resume,
6966 .freeze = rtl8169_suspend,
6967 .thaw = rtl8169_resume,
6968 .poweroff = rtl8169_suspend,
6969 .restore = rtl8169_resume,
6970 .runtime_suspend = rtl8169_runtime_suspend,
6971 .runtime_resume = rtl8169_runtime_resume,
6972 .runtime_idle = rtl8169_runtime_idle,
6973};
6974
6975#define RTL8169_PM_OPS (&rtl8169_pm_ops)
6976
6977#else /* !CONFIG_PM */
6978
6979#define RTL8169_PM_OPS NULL
6980
6981#endif /* !CONFIG_PM */
6982
6983static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
6984{
6985 /* WoL fails with 8168b when the receiver is disabled. */
6986 switch (tp->mac_version) {
6987 case RTL_GIGA_MAC_VER_11:
6988 case RTL_GIGA_MAC_VER_12:
6989 case RTL_GIGA_MAC_VER_17:
6990 pci_clear_master(tp->pci_dev);
6991
6992 RTL_W8(tp, ChipCmd, CmdRxEnb);
6993 /* PCI commit */
6994 RTL_R8(tp, ChipCmd);
6995 break;
6996 default:
6997 break;
6998 }
6999}
7000
7001static void rtl_shutdown(struct pci_dev *pdev)
7002{
7003 struct net_device *dev = pci_get_drvdata(pdev);
7004 struct rtl8169_private *tp = netdev_priv(dev);
7005
7006 rtl8169_net_suspend(dev);
7007
7008 /* Restore original MAC address */
7009 rtl_rar_set(tp, dev->perm_addr);
7010
7011 rtl8169_hw_reset(tp);
7012
7013 if (system_state == SYSTEM_POWER_OFF) {
7014 if (tp->saved_wolopts) {
7015 rtl_wol_suspend_quirk(tp);
7016 rtl_wol_shutdown_quirk(tp);
7017 }
7018
7019 pci_wake_from_d3(pdev, true);
7020 pci_set_power_state(pdev, PCI_D3hot);
7021 }
7022}
7023
7024static void rtl_remove_one(struct pci_dev *pdev)
7025{
7026 struct net_device *dev = pci_get_drvdata(pdev);
7027 struct rtl8169_private *tp = netdev_priv(dev);
7028
7029 if (r8168_check_dash(tp))
7030 rtl8168_driver_stop(tp);
7031
7032 netif_napi_del(&tp->napi);
7033
7034 unregister_netdev(dev);
7035 mdiobus_unregister(tp->mii_bus);
7036
7037 rtl_release_firmware(tp);
7038
7039 if (pci_dev_run_wake(pdev))
7040 pm_runtime_get_noresume(&pdev->dev);
7041
7042 /* restore original MAC address */
7043 rtl_rar_set(tp, dev->perm_addr);
7044}
7045
7046static const struct net_device_ops rtl_netdev_ops = {
7047 .ndo_open = rtl_open,
7048 .ndo_stop = rtl8169_close,
7049 .ndo_get_stats64 = rtl8169_get_stats64,
7050 .ndo_start_xmit = rtl8169_start_xmit,
7051 .ndo_tx_timeout = rtl8169_tx_timeout,
7052 .ndo_validate_addr = eth_validate_addr,
7053 .ndo_change_mtu = rtl8169_change_mtu,
7054 .ndo_fix_features = rtl8169_fix_features,
7055 .ndo_set_features = rtl8169_set_features,
7056 .ndo_set_mac_address = rtl_set_mac_address,
7057 .ndo_do_ioctl = rtl8169_ioctl,
7058 .ndo_set_rx_mode = rtl_set_rx_mode,
7059#ifdef CONFIG_NET_POLL_CONTROLLER
7060 .ndo_poll_controller = rtl8169_netpoll,
7061#endif
7062
7063};
7064
7065static const struct rtl_cfg_info {
7066 void (*hw_start)(struct rtl8169_private *tp);
7067 u16 event_slow;
7068 unsigned int has_gmii:1;
7069 const struct rtl_coalesce_info *coalesce_info;
7070 u8 default_ver;
7071} rtl_cfg_infos [] = {
7072 [RTL_CFG_0] = {
7073 .hw_start = rtl_hw_start_8169,
7074 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7075 .has_gmii = 1,
7076 .coalesce_info = rtl_coalesce_info_8169,
7077 .default_ver = RTL_GIGA_MAC_VER_01,
7078 },
7079 [RTL_CFG_1] = {
7080 .hw_start = rtl_hw_start_8168,
7081 .event_slow = SYSErr | LinkChg | RxOverflow,
7082 .has_gmii = 1,
7083 .coalesce_info = rtl_coalesce_info_8168_8136,
7084 .default_ver = RTL_GIGA_MAC_VER_11,
7085 },
7086 [RTL_CFG_2] = {
7087 .hw_start = rtl_hw_start_8101,
7088 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7089 PCSTimeout,
7090 .coalesce_info = rtl_coalesce_info_8168_8136,
7091 .default_ver = RTL_GIGA_MAC_VER_13,
7092 }
7093};
7094
7095static int rtl_alloc_irq(struct rtl8169_private *tp)
7096{
7097 unsigned int flags;
7098
7099 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
7100 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7101 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7102 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7103 flags = PCI_IRQ_LEGACY;
7104 } else {
7105 flags = PCI_IRQ_ALL_TYPES;
7106 }
7107
7108 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7109}
7110
7111DECLARE_RTL_COND(rtl_link_list_ready_cond)
7112{
7113 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7114}
7115
7116DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7117{
7118 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7119}
7120
7121static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7122{
7123 struct rtl8169_private *tp = mii_bus->priv;
7124
7125 if (phyaddr > 0)
7126 return -ENODEV;
7127
7128 return rtl_readphy(tp, phyreg);
7129}
7130
7131static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7132 int phyreg, u16 val)
7133{
7134 struct rtl8169_private *tp = mii_bus->priv;
7135
7136 if (phyaddr > 0)
7137 return -ENODEV;
7138
7139 rtl_writephy(tp, phyreg, val);
7140
7141 return 0;
7142}
7143
7144static int r8169_mdio_register(struct rtl8169_private *tp)
7145{
7146 struct pci_dev *pdev = tp->pci_dev;
7147 struct phy_device *phydev;
7148 struct mii_bus *new_bus;
7149 int ret;
7150
7151 new_bus = devm_mdiobus_alloc(&pdev->dev);
7152 if (!new_bus)
7153 return -ENOMEM;
7154
7155 new_bus->name = "r8169";
7156 new_bus->priv = tp;
7157 new_bus->parent = &pdev->dev;
7158 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7159 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7160 PCI_DEVID(pdev->bus->number, pdev->devfn));
7161
7162 new_bus->read = r8169_mdio_read_reg;
7163 new_bus->write = r8169_mdio_write_reg;
7164
7165 ret = mdiobus_register(new_bus);
7166 if (ret)
7167 return ret;
7168
7169 phydev = mdiobus_get_phy(new_bus, 0);
7170 if (!phydev) {
7171 mdiobus_unregister(new_bus);
7172 return -ENODEV;
7173 }
7174
7175 /* PHY will be woken up in rtl_open() */
7176 phy_suspend(phydev);
7177
7178 tp->mii_bus = new_bus;
7179
7180 return 0;
7181}
7182
7183static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7184{
7185 u32 data;
7186
7187 tp->ocp_base = OCP_STD_PHY_BASE;
7188
7189 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7190
7191 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7192 return;
7193
7194 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7195 return;
7196
7197 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7198 msleep(1);
7199 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7200
7201 data = r8168_mac_ocp_read(tp, 0xe8de);
7202 data &= ~(1 << 14);
7203 r8168_mac_ocp_write(tp, 0xe8de, data);
7204
7205 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7206 return;
7207
7208 data = r8168_mac_ocp_read(tp, 0xe8de);
7209 data |= (1 << 15);
7210 r8168_mac_ocp_write(tp, 0xe8de, data);
7211
7212 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7213 return;
7214}
7215
7216static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7217{
7218 rtl8168ep_stop_cmac(tp);
7219 rtl_hw_init_8168g(tp);
7220}
7221
7222static void rtl_hw_initialize(struct rtl8169_private *tp)
7223{
7224 switch (tp->mac_version) {
7225 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7226 rtl_hw_init_8168g(tp);
7227 break;
7228 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7229 rtl_hw_init_8168ep(tp);
7230 break;
7231 default:
7232 break;
7233 }
7234}
7235
7236/* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
7237static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7238{
7239 switch (tp->mac_version) {
7240 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7241 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7242 return false;
7243 default:
7244 return true;
7245 }
7246}
7247
7248static int rtl_jumbo_max(struct rtl8169_private *tp)
7249{
7250 /* Non-GBit versions don't support jumbo frames */
7251 if (!tp->supports_gmii)
7252 return JUMBO_1K;
7253
7254 switch (tp->mac_version) {
7255 /* RTL8169 */
7256 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7257 return JUMBO_7K;
7258 /* RTL8168b */
7259 case RTL_GIGA_MAC_VER_11:
7260 case RTL_GIGA_MAC_VER_12:
7261 case RTL_GIGA_MAC_VER_17:
7262 return JUMBO_4K;
7263 /* RTL8168c */
7264 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7265 return JUMBO_6K;
7266 default:
7267 return JUMBO_9K;
7268 }
7269}
7270
7271static void rtl_disable_clk(void *data)
7272{
7273 clk_disable_unprepare(data);
7274}
7275
7276static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7277{
7278 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7279 struct rtl8169_private *tp;
7280 struct net_device *dev;
7281 int chipset, region, i;
7282 int jumbo_max, rc;
7283
7284 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7285 if (!dev)
7286 return -ENOMEM;
7287
7288 SET_NETDEV_DEV(dev, &pdev->dev);
7289 dev->netdev_ops = &rtl_netdev_ops;
7290 tp = netdev_priv(dev);
7291 tp->dev = dev;
7292 tp->pci_dev = pdev;
7293 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7294 tp->supports_gmii = cfg->has_gmii;
7295
7296 /* Get the *optional* external "ether_clk" used on some boards */
7297 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7298 if (IS_ERR(tp->clk)) {
7299 rc = PTR_ERR(tp->clk);
7300 if (rc == -ENOENT) {
7301 /* clk-core allows NULL (for suspend / resume) */
7302 tp->clk = NULL;
7303 } else if (rc == -EPROBE_DEFER) {
7304 return rc;
7305 } else {
7306 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7307 return rc;
7308 }
7309 } else {
7310 rc = clk_prepare_enable(tp->clk);
7311 if (rc) {
7312 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7313 return rc;
7314 }
7315
7316 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7317 tp->clk);
7318 if (rc)
7319 return rc;
7320 }
7321
7322 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7323 rc = pcim_enable_device(pdev);
7324 if (rc < 0) {
7325 dev_err(&pdev->dev, "enable failure\n");
7326 return rc;
7327 }
7328
7329 if (pcim_set_mwi(pdev) < 0)
7330 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7331
7332 /* use first MMIO region */
7333 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7334 if (region < 0) {
7335 dev_err(&pdev->dev, "no MMIO resource found\n");
7336 return -ENODEV;
7337 }
7338
7339 /* check for weird/broken PCI region reporting */
7340 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7341 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7342 return -ENODEV;
7343 }
7344
7345 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7346 if (rc < 0) {
7347 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7348 return rc;
7349 }
7350
7351 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7352
7353 if (!pci_is_pcie(pdev))
7354 dev_info(&pdev->dev, "not PCI Express\n");
7355
7356 /* Identify chip attached to board */
7357 rtl8169_get_mac_version(tp, cfg->default_ver);
7358
7359 if (rtl_tbi_enabled(tp)) {
7360 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7361 return -ENODEV;
7362 }
7363
7364 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7365
7366 if ((sizeof(dma_addr_t) > 4) &&
7367 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7368 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7369 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7370 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7371
7372 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7373 if (!pci_is_pcie(pdev))
7374 tp->cp_cmd |= PCIDAC;
7375 dev->features |= NETIF_F_HIGHDMA;
7376 } else {
7377 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7378 if (rc < 0) {
7379 dev_err(&pdev->dev, "DMA configuration failed\n");
7380 return rc;
7381 }
7382 }
7383
7384 rtl_init_rxcfg(tp);
7385
7386 rtl_irq_disable(tp);
7387
7388 rtl_hw_initialize(tp);
7389
7390 rtl_hw_reset(tp);
7391
7392 rtl_ack_events(tp, 0xffff);
7393
7394 pci_set_master(pdev);
7395
7396 rtl_init_mdio_ops(tp);
7397 rtl_init_jumbo_ops(tp);
7398
7399 rtl8169_print_mac_version(tp);
7400
7401 chipset = tp->mac_version;
7402
7403 rc = rtl_alloc_irq(tp);
7404 if (rc < 0) {
7405 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7406 return rc;
7407 }
7408
7409 tp->saved_wolopts = __rtl8169_get_wol(tp);
7410
7411 mutex_init(&tp->wk.mutex);
7412 u64_stats_init(&tp->rx_stats.syncp);
7413 u64_stats_init(&tp->tx_stats.syncp);
7414
7415 /* Get MAC address */
7416 switch (tp->mac_version) {
7417 u8 mac_addr[ETH_ALEN] __aligned(4);
7418 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7419 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7420 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7421 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7422
7423 if (is_valid_ether_addr(mac_addr))
7424 rtl_rar_set(tp, mac_addr);
7425 break;
7426 default:
7427 break;
7428 }
7429 for (i = 0; i < ETH_ALEN; i++)
7430 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7431
7432 dev->ethtool_ops = &rtl8169_ethtool_ops;
7433 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7434
7435 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7436
7437 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7438 * properly for all devices */
7439 dev->features |= NETIF_F_RXCSUM |
7440 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7441
7442 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7443 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7444 NETIF_F_HW_VLAN_CTAG_RX;
7445 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7446 NETIF_F_HIGHDMA;
7447 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7448
7449 tp->cp_cmd |= RxChkSum | RxVlan;
7450
7451 /*
7452 * Pretend we are using VLANs; This bypasses a nasty bug where
7453 * Interrupts stop flowing on high load on 8110SCd controllers.
7454 */
7455 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7456 /* Disallow toggling */
7457 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7458
7459 if (rtl_chip_supports_csum_v2(tp)) {
7460 tp->tso_csum = rtl8169_tso_csum_v2;
7461 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7462 } else {
7463 tp->tso_csum = rtl8169_tso_csum_v1;
7464 }
7465
7466 dev->hw_features |= NETIF_F_RXALL;
7467 dev->hw_features |= NETIF_F_RXFCS;
7468
7469 /* MTU range: 60 - hw-specific max */
7470 dev->min_mtu = ETH_ZLEN;
7471 jumbo_max = rtl_jumbo_max(tp);
7472 dev->max_mtu = jumbo_max;
7473
7474 tp->hw_start = cfg->hw_start;
7475 tp->event_slow = cfg->event_slow;
7476 tp->coalesce_info = cfg->coalesce_info;
7477
7478 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7479
7480 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7481 &tp->counters_phys_addr,
7482 GFP_KERNEL);
7483 if (!tp->counters)
7484 return -ENOMEM;
7485
7486 pci_set_drvdata(pdev, dev);
7487
7488 rc = r8169_mdio_register(tp);
7489 if (rc)
7490 return rc;
7491
7492 /* chip gets powered up in rtl_open() */
7493 rtl_pll_power_down(tp);
7494
7495 rc = register_netdev(dev);
7496 if (rc)
7497 goto err_mdio_unregister;
7498
7499 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7500 rtl_chip_infos[chipset].name, dev->dev_addr,
7501 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7502 pci_irq_vector(pdev, 0));
7503
7504 if (jumbo_max > JUMBO_1K)
7505 netif_info(tp, probe, dev,
7506 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7507 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7508 "ok" : "ko");
7509
7510 if (r8168_check_dash(tp))
7511 rtl8168_driver_start(tp);
7512
7513 if (pci_dev_run_wake(pdev))
7514 pm_runtime_put_sync(&pdev->dev);
7515
7516 return 0;
7517
7518err_mdio_unregister:
7519 mdiobus_unregister(tp->mii_bus);
7520 return rc;
7521}
7522
7523static struct pci_driver rtl8169_pci_driver = {
7524 .name = MODULENAME,
7525 .id_table = rtl8169_pci_tbl,
7526 .probe = rtl_init_one,
7527 .remove = rtl_remove_one,
7528 .shutdown = rtl_shutdown,
7529 .driver.pm = RTL8169_PM_OPS,
7530};
7531
7532module_pci_driver(rtl8169_pci_driver);