blob: c61109f7b7933c91be58c836a24a7506009ee93a [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00001/*
2 * Secure Digital Host Controller Interface ACPI driver.
3 *
4 * Copyright (c) 2012, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 */
20
21#include <linux/init.h>
22#include <linux/export.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/platform_device.h>
26#include <linux/ioport.h>
27#include <linux/io.h>
28#include <linux/dma-mapping.h>
29#include <linux/compiler.h>
30#include <linux/stddef.h>
31#include <linux/bitops.h>
32#include <linux/types.h>
33#include <linux/err.h>
34#include <linux/interrupt.h>
35#include <linux/acpi.h>
36#include <linux/pm.h>
37#include <linux/pm_runtime.h>
38#include <linux/delay.h>
39
40#include <linux/mmc/host.h>
41#include <linux/mmc/pm.h>
42#include <linux/mmc/slot-gpio.h>
43
44#ifdef CONFIG_X86
45#include <asm/cpu_device_id.h>
46#include <asm/intel-family.h>
47#include <asm/iosf_mbi.h>
48#include <linux/pci.h>
49#endif
50
51#include "sdhci.h"
52
53enum {
54 SDHCI_ACPI_SD_CD = BIT(0),
55 SDHCI_ACPI_RUNTIME_PM = BIT(1),
56 SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL = BIT(2),
57};
58
59struct sdhci_acpi_chip {
60 const struct sdhci_ops *ops;
61 unsigned int quirks;
62 unsigned int quirks2;
63 unsigned long caps;
64 unsigned int caps2;
65 mmc_pm_flag_t pm_caps;
66};
67
68struct sdhci_acpi_slot {
69 const struct sdhci_acpi_chip *chip;
70 unsigned int quirks;
71 unsigned int quirks2;
72 unsigned long caps;
73 unsigned int caps2;
74 mmc_pm_flag_t pm_caps;
75 unsigned int flags;
76 size_t priv_size;
77 int (*probe_slot)(struct platform_device *, const char *, const char *);
78 int (*remove_slot)(struct platform_device *);
79 int (*free_slot)(struct platform_device *pdev);
80 int (*setup_host)(struct platform_device *pdev);
81};
82
83struct sdhci_acpi_host {
84 struct sdhci_host *host;
85 const struct sdhci_acpi_slot *slot;
86 struct platform_device *pdev;
87 bool use_runtime_pm;
88 unsigned long private[0] ____cacheline_aligned;
89};
90
91static inline void *sdhci_acpi_priv(struct sdhci_acpi_host *c)
92{
93 return (void *)c->private;
94}
95
96static inline bool sdhci_acpi_flag(struct sdhci_acpi_host *c, unsigned int flag)
97{
98 return c->slot && (c->slot->flags & flag);
99}
100
101#define INTEL_DSM_HS_CAPS_SDR25 BIT(0)
102#define INTEL_DSM_HS_CAPS_DDR50 BIT(1)
103#define INTEL_DSM_HS_CAPS_SDR50 BIT(2)
104#define INTEL_DSM_HS_CAPS_SDR104 BIT(3)
105
106enum {
107 INTEL_DSM_FNS = 0,
108 INTEL_DSM_V18_SWITCH = 3,
109 INTEL_DSM_V33_SWITCH = 4,
110 INTEL_DSM_HS_CAPS = 8,
111};
112
113struct intel_host {
114 u32 dsm_fns;
115 u32 hs_caps;
116};
117
118static const guid_t intel_dsm_guid =
119 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
120 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
121
122static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
123 unsigned int fn, u32 *result)
124{
125 union acpi_object *obj;
126 int err = 0;
127
128 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
129 if (!obj)
130 return -EOPNOTSUPP;
131
132 if (obj->type == ACPI_TYPE_INTEGER) {
133 *result = obj->integer.value;
134 } else if (obj->type == ACPI_TYPE_BUFFER && obj->buffer.length > 0) {
135 size_t len = min_t(size_t, obj->buffer.length, 4);
136
137 *result = 0;
138 memcpy(result, obj->buffer.pointer, len);
139 } else {
140 dev_err(dev, "%s DSM fn %u obj->type %d obj->buffer.length %d\n",
141 __func__, fn, obj->type, obj->buffer.length);
142 err = -EINVAL;
143 }
144
145 ACPI_FREE(obj);
146
147 return err;
148}
149
150static int intel_dsm(struct intel_host *intel_host, struct device *dev,
151 unsigned int fn, u32 *result)
152{
153 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
154 return -EOPNOTSUPP;
155
156 return __intel_dsm(intel_host, dev, fn, result);
157}
158
159static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
160 struct mmc_host *mmc)
161{
162 int err;
163
164 intel_host->hs_caps = ~0;
165
166 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
167 if (err) {
168 pr_debug("%s: DSM not supported, error %d\n",
169 mmc_hostname(mmc), err);
170 return;
171 }
172
173 pr_debug("%s: DSM function mask %#x\n",
174 mmc_hostname(mmc), intel_host->dsm_fns);
175
176 intel_dsm(intel_host, dev, INTEL_DSM_HS_CAPS, &intel_host->hs_caps);
177}
178
179static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
180 struct mmc_ios *ios)
181{
182 struct device *dev = mmc_dev(mmc);
183 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
184 struct intel_host *intel_host = sdhci_acpi_priv(c);
185 unsigned int fn;
186 u32 result = 0;
187 int err;
188
189 err = sdhci_start_signal_voltage_switch(mmc, ios);
190 if (err)
191 return err;
192
193 switch (ios->signal_voltage) {
194 case MMC_SIGNAL_VOLTAGE_330:
195 fn = INTEL_DSM_V33_SWITCH;
196 break;
197 case MMC_SIGNAL_VOLTAGE_180:
198 fn = INTEL_DSM_V18_SWITCH;
199 break;
200 default:
201 return 0;
202 }
203
204 err = intel_dsm(intel_host, dev, fn, &result);
205 pr_debug("%s: %s DSM fn %u error %d result %u\n",
206 mmc_hostname(mmc), __func__, fn, err, result);
207
208 return 0;
209}
210
211static void sdhci_acpi_int_hw_reset(struct sdhci_host *host)
212{
213 u8 reg;
214
215 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
216 reg |= 0x10;
217 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
218 /* For eMMC, minimum is 1us but give it 9us for good measure */
219 udelay(9);
220 reg &= ~0x10;
221 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
222 /* For eMMC, minimum is 200us but give it 300us for good measure */
223 usleep_range(300, 1000);
224}
225
226static const struct sdhci_ops sdhci_acpi_ops_dflt = {
227 .set_clock = sdhci_set_clock,
228 .set_bus_width = sdhci_set_bus_width,
229 .reset = sdhci_reset,
230 .set_uhs_signaling = sdhci_set_uhs_signaling,
231};
232
233static const struct sdhci_ops sdhci_acpi_ops_int = {
234 .set_clock = sdhci_set_clock,
235 .set_bus_width = sdhci_set_bus_width,
236 .reset = sdhci_reset,
237 .set_uhs_signaling = sdhci_set_uhs_signaling,
238 .hw_reset = sdhci_acpi_int_hw_reset,
239};
240
241static const struct sdhci_acpi_chip sdhci_acpi_chip_int = {
242 .ops = &sdhci_acpi_ops_int,
243};
244
245#ifdef CONFIG_X86
246
247static bool sdhci_acpi_byt(void)
248{
249 static const struct x86_cpu_id byt[] = {
250 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1 },
251 {}
252 };
253
254 return x86_match_cpu(byt);
255}
256
257static bool sdhci_acpi_cht(void)
258{
259 static const struct x86_cpu_id cht[] = {
260 { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_AIRMONT },
261 {}
262 };
263
264 return x86_match_cpu(cht);
265}
266
267#define BYT_IOSF_SCCEP 0x63
268#define BYT_IOSF_OCP_NETCTRL0 0x1078
269#define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
270
271static void sdhci_acpi_byt_setting(struct device *dev)
272{
273 u32 val = 0;
274
275 if (!sdhci_acpi_byt())
276 return;
277
278 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
279 &val)) {
280 dev_err(dev, "%s read error\n", __func__);
281 return;
282 }
283
284 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
285 return;
286
287 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
288
289 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
290 val)) {
291 dev_err(dev, "%s write error\n", __func__);
292 return;
293 }
294
295 dev_dbg(dev, "%s completed\n", __func__);
296}
297
298static bool sdhci_acpi_byt_defer(struct device *dev)
299{
300 if (!sdhci_acpi_byt())
301 return false;
302
303 if (!iosf_mbi_available())
304 return true;
305
306 sdhci_acpi_byt_setting(dev);
307
308 return false;
309}
310
311static bool sdhci_acpi_cht_pci_wifi(unsigned int vendor, unsigned int device,
312 unsigned int slot, unsigned int parent_slot)
313{
314 struct pci_dev *dev, *parent, *from = NULL;
315
316 while (1) {
317 dev = pci_get_device(vendor, device, from);
318 pci_dev_put(from);
319 if (!dev)
320 break;
321 parent = pci_upstream_bridge(dev);
322 if (ACPI_COMPANION(&dev->dev) && PCI_SLOT(dev->devfn) == slot &&
323 parent && PCI_SLOT(parent->devfn) == parent_slot &&
324 !pci_upstream_bridge(parent)) {
325 pci_dev_put(dev);
326 return true;
327 }
328 from = dev;
329 }
330
331 return false;
332}
333
334/*
335 * GPDwin uses PCI wifi which conflicts with SDIO's use of
336 * acpi_device_fix_up_power() on child device nodes. Identifying GPDwin is
337 * problematic, but since SDIO is only used for wifi, the presence of the PCI
338 * wifi card in the expected slot with an ACPI companion node, is used to
339 * indicate that acpi_device_fix_up_power() should be avoided.
340 */
341static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
342 const char *uid)
343{
344 return sdhci_acpi_cht() &&
345 !strcmp(hid, "80860F14") &&
346 !strcmp(uid, "2") &&
347 sdhci_acpi_cht_pci_wifi(0x14e4, 0x43ec, 0, 28);
348}
349
350#else
351
352static inline void sdhci_acpi_byt_setting(struct device *dev)
353{
354}
355
356static inline bool sdhci_acpi_byt_defer(struct device *dev)
357{
358 return false;
359}
360
361static inline bool sdhci_acpi_no_fixup_child_power(const char *hid,
362 const char *uid)
363{
364 return false;
365}
366
367#endif
368
369static int bxt_get_cd(struct mmc_host *mmc)
370{
371 int gpio_cd = mmc_gpio_get_cd(mmc);
372 struct sdhci_host *host = mmc_priv(mmc);
373 unsigned long flags;
374 int ret = 0;
375
376 if (!gpio_cd)
377 return 0;
378
379 spin_lock_irqsave(&host->lock, flags);
380
381 if (host->flags & SDHCI_DEVICE_DEAD)
382 goto out;
383
384 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
385out:
386 spin_unlock_irqrestore(&host->lock, flags);
387
388 return ret;
389}
390
391static int intel_probe_slot(struct platform_device *pdev, const char *hid,
392 const char *uid)
393{
394 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
395 struct intel_host *intel_host = sdhci_acpi_priv(c);
396 struct sdhci_host *host = c->host;
397
398 if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") &&
399 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
400 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
401 host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
402
403 if (hid && !strcmp(hid, "80865ACA"))
404 host->mmc_host_ops.get_cd = bxt_get_cd;
405
406 intel_dsm_init(intel_host, &pdev->dev, host->mmc);
407
408 host->mmc_host_ops.start_signal_voltage_switch =
409 intel_start_signal_voltage_switch;
410
411 return 0;
412}
413
414static int intel_setup_host(struct platform_device *pdev)
415{
416 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
417 struct intel_host *intel_host = sdhci_acpi_priv(c);
418
419 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR25))
420 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR25;
421
422 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR50))
423 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR50;
424
425 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_DDR50))
426 c->host->mmc->caps &= ~MMC_CAP_UHS_DDR50;
427
428 if (!(intel_host->hs_caps & INTEL_DSM_HS_CAPS_SDR104))
429 c->host->mmc->caps &= ~MMC_CAP_UHS_SDR104;
430
431 return 0;
432}
433
434static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
435 .chip = &sdhci_acpi_chip_int,
436 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
437 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
438 MMC_CAP_CMD_DURING_TFR | MMC_CAP_WAIT_WHILE_BUSY,
439 .flags = SDHCI_ACPI_RUNTIME_PM,
440 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
441 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
442 SDHCI_QUIRK2_STOP_WITH_TC |
443 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400,
444 .probe_slot = intel_probe_slot,
445 .setup_host = intel_setup_host,
446 .priv_size = sizeof(struct intel_host),
447};
448
449static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
450 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
451 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
452 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
453 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
454 MMC_CAP_WAIT_WHILE_BUSY,
455 .flags = SDHCI_ACPI_RUNTIME_PM,
456 .pm_caps = MMC_PM_KEEP_POWER,
457 .probe_slot = intel_probe_slot,
458 .setup_host = intel_setup_host,
459 .priv_size = sizeof(struct intel_host),
460};
461
462static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
463 .flags = SDHCI_ACPI_SD_CD | SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL |
464 SDHCI_ACPI_RUNTIME_PM,
465 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
466 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
467 SDHCI_QUIRK2_STOP_WITH_TC,
468 .caps = MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_AGGRESSIVE_PM,
469 .probe_slot = intel_probe_slot,
470 .setup_host = intel_setup_host,
471 .priv_size = sizeof(struct intel_host),
472};
473
474static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd_3v = {
475 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
476 .quirks2 = SDHCI_QUIRK2_NO_1_8_V,
477 .caps = MMC_CAP_NONREMOVABLE,
478};
479
480static const struct sdhci_acpi_slot sdhci_acpi_slot_qcom_sd = {
481 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION,
482 .caps = MMC_CAP_NONREMOVABLE,
483};
484
485/* AMD sdhci reset dll register. */
486#define SDHCI_AMD_RESET_DLL_REGISTER 0x908
487
488static int amd_select_drive_strength(struct mmc_card *card,
489 unsigned int max_dtr, int host_drv,
490 int card_drv, int *drv_type)
491{
492 return MMC_SET_DRIVER_TYPE_A;
493}
494
495static void sdhci_acpi_amd_hs400_dll(struct sdhci_host *host)
496{
497 /* AMD Platform requires dll setting */
498 sdhci_writel(host, 0x40003210, SDHCI_AMD_RESET_DLL_REGISTER);
499 usleep_range(10, 20);
500 sdhci_writel(host, 0x40033210, SDHCI_AMD_RESET_DLL_REGISTER);
501}
502
503/*
504 * For AMD Platform it is required to disable the tuning
505 * bit first controller to bring to HS Mode from HS200
506 * mode, later enable to tune to HS400 mode.
507 */
508static void amd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
509{
510 struct sdhci_host *host = mmc_priv(mmc);
511 unsigned int old_timing = host->timing;
512
513 sdhci_set_ios(mmc, ios);
514 if (old_timing == MMC_TIMING_MMC_HS200 &&
515 ios->timing == MMC_TIMING_MMC_HS)
516 sdhci_writew(host, 0x9, SDHCI_HOST_CONTROL2);
517 if (old_timing != MMC_TIMING_MMC_HS400 &&
518 ios->timing == MMC_TIMING_MMC_HS400) {
519 sdhci_writew(host, 0x80, SDHCI_HOST_CONTROL2);
520 sdhci_acpi_amd_hs400_dll(host);
521 }
522}
523
524static const struct sdhci_ops sdhci_acpi_ops_amd = {
525 .set_clock = sdhci_set_clock,
526 .set_bus_width = sdhci_set_bus_width,
527 .reset = sdhci_reset,
528 .set_uhs_signaling = sdhci_set_uhs_signaling,
529};
530
531static const struct sdhci_acpi_chip sdhci_acpi_chip_amd = {
532 .ops = &sdhci_acpi_ops_amd,
533};
534
535static int sdhci_acpi_emmc_amd_probe_slot(struct platform_device *pdev,
536 const char *hid, const char *uid)
537{
538 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
539 struct sdhci_host *host = c->host;
540
541 sdhci_read_caps(host);
542 if (host->caps1 & SDHCI_SUPPORT_DDR50)
543 host->mmc->caps = MMC_CAP_1_8V_DDR;
544
545 if ((host->caps1 & SDHCI_SUPPORT_SDR104) &&
546 (host->mmc->caps & MMC_CAP_1_8V_DDR))
547 host->mmc->caps2 = MMC_CAP2_HS400_1_8V;
548
549 host->mmc_host_ops.select_drive_strength = amd_select_drive_strength;
550 host->mmc_host_ops.set_ios = amd_set_ios;
551 return 0;
552}
553
554static const struct sdhci_acpi_slot sdhci_acpi_slot_amd_emmc = {
555 .chip = &sdhci_acpi_chip_amd,
556 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
557 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_32BIT_DMA_SIZE |
558 SDHCI_QUIRK_32BIT_ADMA_SIZE,
559 .probe_slot = sdhci_acpi_emmc_amd_probe_slot,
560};
561
562struct sdhci_acpi_uid_slot {
563 const char *hid;
564 const char *uid;
565 const struct sdhci_acpi_slot *slot;
566};
567
568static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
569 { "80865ACA", NULL, &sdhci_acpi_slot_int_sd },
570 { "80865ACC", NULL, &sdhci_acpi_slot_int_emmc },
571 { "80865AD0", NULL, &sdhci_acpi_slot_int_sdio },
572 { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
573 { "80860F14" , "2" , &sdhci_acpi_slot_int_sdio },
574 { "80860F14" , "3" , &sdhci_acpi_slot_int_sd },
575 { "80860F16" , NULL, &sdhci_acpi_slot_int_sd },
576 { "INT33BB" , "2" , &sdhci_acpi_slot_int_sdio },
577 { "INT33BB" , "3" , &sdhci_acpi_slot_int_sd },
578 { "INT33C6" , NULL, &sdhci_acpi_slot_int_sdio },
579 { "INT3436" , NULL, &sdhci_acpi_slot_int_sdio },
580 { "INT344D" , NULL, &sdhci_acpi_slot_int_sdio },
581 { "PNP0FFF" , "3" , &sdhci_acpi_slot_int_sd },
582 { "PNP0D40" },
583 { "QCOM8051", NULL, &sdhci_acpi_slot_qcom_sd_3v },
584 { "QCOM8052", NULL, &sdhci_acpi_slot_qcom_sd },
585 { "AMDI0040", NULL, &sdhci_acpi_slot_amd_emmc },
586 { },
587};
588
589static const struct acpi_device_id sdhci_acpi_ids[] = {
590 { "80865ACA" },
591 { "80865ACC" },
592 { "80865AD0" },
593 { "80860F14" },
594 { "80860F16" },
595 { "INT33BB" },
596 { "INT33C6" },
597 { "INT3436" },
598 { "INT344D" },
599 { "PNP0D40" },
600 { "QCOM8051" },
601 { "QCOM8052" },
602 { "AMDI0040" },
603 { },
604};
605MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
606
607static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid,
608 const char *uid)
609{
610 const struct sdhci_acpi_uid_slot *u;
611
612 for (u = sdhci_acpi_uids; u->hid; u++) {
613 if (strcmp(u->hid, hid))
614 continue;
615 if (!u->uid)
616 return u->slot;
617 if (uid && !strcmp(u->uid, uid))
618 return u->slot;
619 }
620 return NULL;
621}
622
623static int sdhci_acpi_probe(struct platform_device *pdev)
624{
625 struct device *dev = &pdev->dev;
626 const struct sdhci_acpi_slot *slot;
627 struct acpi_device *device, *child;
628 struct sdhci_acpi_host *c;
629 struct sdhci_host *host;
630 struct resource *iomem;
631 resource_size_t len;
632 size_t priv_size;
633 const char *hid;
634 const char *uid;
635 int err;
636
637 device = ACPI_COMPANION(dev);
638 if (!device)
639 return -ENODEV;
640
641 hid = acpi_device_hid(device);
642 uid = acpi_device_uid(device);
643
644 slot = sdhci_acpi_get_slot(hid, uid);
645
646 /* Power on the SDHCI controller and its children */
647 acpi_device_fix_up_power(device);
648 if (!sdhci_acpi_no_fixup_child_power(hid, uid)) {
649 list_for_each_entry(child, &device->children, node)
650 if (child->status.present && child->status.enabled)
651 acpi_device_fix_up_power(child);
652 }
653
654 if (sdhci_acpi_byt_defer(dev))
655 return -EPROBE_DEFER;
656
657 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
658 if (!iomem)
659 return -ENOMEM;
660
661 len = resource_size(iomem);
662 if (len < 0x100)
663 dev_err(dev, "Invalid iomem size!\n");
664
665 if (!devm_request_mem_region(dev, iomem->start, len, dev_name(dev)))
666 return -ENOMEM;
667
668 priv_size = slot ? slot->priv_size : 0;
669 host = sdhci_alloc_host(dev, sizeof(struct sdhci_acpi_host) + priv_size);
670 if (IS_ERR(host))
671 return PTR_ERR(host);
672
673 c = sdhci_priv(host);
674 c->host = host;
675 c->slot = slot;
676 c->pdev = pdev;
677 c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
678
679 platform_set_drvdata(pdev, c);
680
681 host->hw_name = "ACPI";
682 host->ops = &sdhci_acpi_ops_dflt;
683 host->irq = platform_get_irq(pdev, 0);
684 if (host->irq < 0) {
685 err = -EINVAL;
686 goto err_free;
687 }
688
689 host->ioaddr = devm_ioremap_nocache(dev, iomem->start,
690 resource_size(iomem));
691 if (host->ioaddr == NULL) {
692 err = -ENOMEM;
693 goto err_free;
694 }
695
696 if (c->slot) {
697 if (c->slot->probe_slot) {
698 err = c->slot->probe_slot(pdev, hid, uid);
699 if (err)
700 goto err_free;
701 }
702 if (c->slot->chip) {
703 host->ops = c->slot->chip->ops;
704 host->quirks |= c->slot->chip->quirks;
705 host->quirks2 |= c->slot->chip->quirks2;
706 host->mmc->caps |= c->slot->chip->caps;
707 host->mmc->caps2 |= c->slot->chip->caps2;
708 host->mmc->pm_caps |= c->slot->chip->pm_caps;
709 }
710 host->quirks |= c->slot->quirks;
711 host->quirks2 |= c->slot->quirks2;
712 host->mmc->caps |= c->slot->caps;
713 host->mmc->caps2 |= c->slot->caps2;
714 host->mmc->pm_caps |= c->slot->pm_caps;
715 }
716
717 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
718
719 if (sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD)) {
720 bool v = sdhci_acpi_flag(c, SDHCI_ACPI_SD_CD_OVERRIDE_LEVEL);
721
722 err = mmc_gpiod_request_cd(host->mmc, NULL, 0, v, 0, NULL);
723 if (err) {
724 if (err == -EPROBE_DEFER)
725 goto err_free;
726 dev_warn(dev, "failed to setup card detect gpio\n");
727 c->use_runtime_pm = false;
728 }
729 }
730
731 err = sdhci_setup_host(host);
732 if (err)
733 goto err_free;
734
735 if (c->slot && c->slot->setup_host) {
736 err = c->slot->setup_host(pdev);
737 if (err)
738 goto err_cleanup;
739 }
740
741 err = __sdhci_add_host(host);
742 if (err)
743 goto err_cleanup;
744
745 if (c->use_runtime_pm) {
746 pm_runtime_set_active(dev);
747 pm_suspend_ignore_children(dev, 1);
748 pm_runtime_set_autosuspend_delay(dev, 50);
749 pm_runtime_use_autosuspend(dev);
750 pm_runtime_enable(dev);
751 }
752
753 device_enable_async_suspend(dev);
754
755 return 0;
756
757err_cleanup:
758 sdhci_cleanup_host(c->host);
759err_free:
760 if (c->slot && c->slot->free_slot)
761 c->slot->free_slot(pdev);
762
763 sdhci_free_host(c->host);
764 return err;
765}
766
767static int sdhci_acpi_remove(struct platform_device *pdev)
768{
769 struct sdhci_acpi_host *c = platform_get_drvdata(pdev);
770 struct device *dev = &pdev->dev;
771 int dead;
772
773 if (c->use_runtime_pm) {
774 pm_runtime_get_sync(dev);
775 pm_runtime_disable(dev);
776 pm_runtime_put_noidle(dev);
777 }
778
779 if (c->slot && c->slot->remove_slot)
780 c->slot->remove_slot(pdev);
781
782 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0);
783 sdhci_remove_host(c->host, dead);
784
785 if (c->slot && c->slot->free_slot)
786 c->slot->free_slot(pdev);
787
788 sdhci_free_host(c->host);
789
790 return 0;
791}
792
793#ifdef CONFIG_PM_SLEEP
794
795static int sdhci_acpi_suspend(struct device *dev)
796{
797 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
798 struct sdhci_host *host = c->host;
799
800 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
801 mmc_retune_needed(host->mmc);
802
803 return sdhci_suspend_host(host);
804}
805
806static int sdhci_acpi_resume(struct device *dev)
807{
808 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
809
810 sdhci_acpi_byt_setting(&c->pdev->dev);
811
812 return sdhci_resume_host(c->host);
813}
814
815#endif
816
817#ifdef CONFIG_PM
818
819static int sdhci_acpi_runtime_suspend(struct device *dev)
820{
821 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
822 struct sdhci_host *host = c->host;
823
824 if (host->tuning_mode != SDHCI_TUNING_MODE_3)
825 mmc_retune_needed(host->mmc);
826
827 return sdhci_runtime_suspend_host(host);
828}
829
830static int sdhci_acpi_runtime_resume(struct device *dev)
831{
832 struct sdhci_acpi_host *c = dev_get_drvdata(dev);
833
834 sdhci_acpi_byt_setting(&c->pdev->dev);
835
836 return sdhci_runtime_resume_host(c->host);
837}
838
839#endif
840
841static const struct dev_pm_ops sdhci_acpi_pm_ops = {
842 SET_SYSTEM_SLEEP_PM_OPS(sdhci_acpi_suspend, sdhci_acpi_resume)
843 SET_RUNTIME_PM_OPS(sdhci_acpi_runtime_suspend,
844 sdhci_acpi_runtime_resume, NULL)
845};
846
847static struct platform_driver sdhci_acpi_driver = {
848 .driver = {
849 .name = "sdhci-acpi",
850 .acpi_match_table = sdhci_acpi_ids,
851 .pm = &sdhci_acpi_pm_ops,
852 },
853 .probe = sdhci_acpi_probe,
854 .remove = sdhci_acpi_remove,
855};
856
857module_platform_driver(sdhci_acpi_driver);
858
859MODULE_DESCRIPTION("Secure Digital Host Controller Interface ACPI driver");
860MODULE_AUTHOR("Adrian Hunter");
861MODULE_LICENSE("GPL v2");