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review.trustedfirmware.org / hafnium / third_party / linux.git / b4b6d4a02fa8aa8187d426b508fb7f3b69df0dcc / . / drivers / infiniband / hw / mlx5 / main.c
blob: 50be240df331bf043f833775e58e7d19c94f2579 [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame^]1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/debugfs.h>
34#include <linux/highmem.h>
35#include <linux/module.h>
36#include <linux/init.h>
37#include <linux/errno.h>
38#include <linux/pci.h>
39#include <linux/dma-mapping.h>
40#include <linux/slab.h>
41#include <linux/bitmap.h>
42#if defined(CONFIG_X86)
43#include <asm/pat.h>
44#endif
45#include <linux/sched.h>
46#include <linux/sched/mm.h>
47#include <linux/sched/task.h>
48#include <linux/delay.h>
49#include <rdma/ib_user_verbs.h>
50#include <rdma/ib_addr.h>
51#include <rdma/ib_cache.h>
52#include <linux/mlx5/port.h>
53#include <linux/mlx5/vport.h>
54#include <linux/mlx5/fs.h>
55#include <linux/list.h>
56#include <rdma/ib_smi.h>
57#include <rdma/ib_umem.h>
58#include <linux/in.h>
59#include <linux/etherdevice.h>
60#include "mlx5_ib.h"
61#include "ib_rep.h"
62#include "cmd.h"
63#include <linux/mlx5/fs_helpers.h>
64#include <linux/mlx5/accel.h>
65#include <rdma/uverbs_std_types.h>
66#include <rdma/mlx5_user_ioctl_verbs.h>
67#include <rdma/mlx5_user_ioctl_cmds.h>
68
69#define UVERBS_MODULE_NAME mlx5_ib
70#include <rdma/uverbs_named_ioctl.h>
71
72#define DRIVER_NAME "mlx5_ib"
73#define DRIVER_VERSION "5.0-0"
74
75MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77MODULE_LICENSE("Dual BSD/GPL");
78
79static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
81 DRIVER_VERSION "\n";
82
83struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89};
90
91enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93};
94
95static struct workqueue_struct *mlx5_ib_event_wq;
96static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97static LIST_HEAD(mlx5_ib_dev_list);
98/*
99 * This mutex should be held when accessing either of the above lists
100 */
101static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
103/* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106static unsigned long xlt_emergency_page;
107static struct mutex xlt_emergency_page_mutex;
108
109struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110{
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117}
118
119static enum rdma_link_layer
120mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
121{
122 switch (port_type_cap) {
123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130}
131
132static enum rdma_link_layer
133mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134{
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139}
140
141static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144{
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
149 ret = ibdev->query_port(ibdev, port_num, &attr);
150 if (!ret)
151 *state = attr.state;
152 return ret;
153}
154
155static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157{
158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
168
169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
172 write_lock(&roce->netdev_lock);
173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
181 NULL : ndev;
182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
186 write_unlock(&roce->netdev_lock);
187 break;
188
189 case NETDEV_CHANGE:
190 case NETDEV_UP:
191 case NETDEV_DOWN: {
192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
200 if ((upper == ndev || (!upper && ndev == roce->netdev))
201 && ibdev->ib_active) {
202 struct ib_event ibev = { };
203 enum ib_port_state port_state;
204
205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
208
209 if (roce->last_port_state == port_state)
210 goto done;
211
212 roce->last_port_state = port_state;
213 ibev.device = &ibdev->ib_dev;
214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
219 goto done;
220
221 ibev.element.port_num = port_num;
222 ib_dispatch_event(&ibev);
223 }
224 break;
225 }
226
227 default:
228 break;
229 }
230done:
231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
232 return NOTIFY_DONE;
233}
234
235static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237{
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
245
246 ndev = mlx5_lag_get_roce_netdev(mdev);
247 if (ndev)
248 goto out;
249
250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
254 if (ndev)
255 dev_hold(ndev);
256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
257
258out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
260 return ndev;
261}
262
263struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266{
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
280 if (native_port_num)
281 *native_port_num = 1;
282
283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300}
301
302void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303{
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322out:
323 spin_unlock(&port->mp.mpi_lock);
324}
325
326static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328{
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382}
383
384static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
386{
387 struct mlx5_ib_dev *dev = to_mdev(device);
388 struct mlx5_core_dev *mdev;
389 struct net_device *ndev, *upper;
390 enum ib_mtu ndev_ib_mtu;
391 bool put_mdev = true;
392 u16 qkey_viol_cntr;
393 u32 eth_prot_oper;
394 u8 mdev_port_num;
395 int err;
396
397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
410 */
411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
413 if (err)
414 goto out;
415
416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
434 props->qkey_viol_cntr = qkey_viol_cntr;
435
436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
442 goto out;
443
444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
465out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
469}
470
471static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
474{
475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
490 }
491
492 switch (gid_type) {
493 case IB_GID_TYPE_IB:
494 roce_version = MLX5_ROCE_VERSION_1;
495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
502 break;
503
504 default:
505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
506 }
507
508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
510 vlan_id, port_num);
511}
512
513static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
514 __always_unused void **context)
515{
516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
517 attr->index, &attr->gid, attr);
518}
519
520static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
522{
523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
525}
526
527__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
529{
530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534}
535
536static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537{
538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
541}
542
543enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547};
548
549static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550{
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559}
560
561static void get_atomic_caps(struct mlx5_ib_dev *dev,
562 u8 atomic_size_qp,
563 struct ib_device_attr *props)
564{
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
567 u8 atomic_req_8B_endianness_mode =
568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581}
582
583static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585{
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589}
590
591static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593{
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597}
598
599bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600{
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605}
606static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608{
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
626
627 default:
628 return -EINVAL;
629 }
630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
636}
637
638static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640{
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657}
658
659static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661{
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675}
676
677static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679{
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
694
695 default:
696 return -EINVAL;
697 }
698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
703}
704
705struct mlx5_reg_node_desc {
706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
707};
708
709static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710{
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721}
722
723static int mlx5_ib_query_device(struct ib_device *ibdev,
724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
726{
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
728 struct mlx5_core_dev *mdev = dev->mdev;
729 int err = -ENOMEM;
730 int max_sq_desc;
731 int max_rq_sg;
732 int max_sq_sg;
733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
734 bool raw_support = !mlx5_core_mp_enabled(mdev);
735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
738
739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
746 return -EINVAL;
747
748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
753
754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
755 if (err)
756 return err;
757
758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
761
762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
768 IB_DEVICE_RC_RNR_NAK_GEN;
769
770 if (MLX5_CAP_GEN(mdev, pkv))
771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
772 if (MLX5_CAP_GEN(mdev, qkv))
773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
774 if (MLX5_CAP_GEN(mdev, apm))
775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
776 if (MLX5_CAP_GEN(mdev, xrc))
777 props->device_cap_flags |= IB_DEVICE_XRC;
778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
784 }
785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
786 if (MLX5_CAP_GEN(mdev, sho)) {
787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
797
798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
808
809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
843 }
844
845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
862 /* Legacy bit to support old userspace libraries */
863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
866
867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
880
881 props->max_mr_size = ~0ull;
882 props->page_size_cap = ~(min_page_size - 1);
883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
893 props->max_sge_rd = MLX5_MAX_SGE_RD;
894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
904 props->max_srq_sge = max_rq_sg - 1;
905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
907 get_atomic_caps_qp(dev, props);
908 props->masked_atomic_cap = IB_ATOMIC_NONE;
909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
914 props->max_ah = INT_MAX;
915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
917
918#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
919 if (MLX5_CAP_GEN(mdev, pg))
920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922#endif
923
924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
931 IB_LINK_LAYER_ETHERNET && raw_support) {
932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
949 }
950
951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
959 resp.response_length += sizeof(resp.cqe_comp_caps);
960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
973 }
974 }
975
976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
1010
1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1017 }
1018
1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1077 }
1078
1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1086 return 0;
1087}
1088
1089enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095};
1096
1097static void translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
1099{
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1101
1102 if (active_width & MLX5_IB_WIDTH_1X)
1103 *ib_width = IB_WIDTH_1X;
1104 else if (active_width & MLX5_IB_WIDTH_4X)
1105 *ib_width = IB_WIDTH_4X;
1106 else if (active_width & MLX5_IB_WIDTH_8X)
1107 *ib_width = IB_WIDTH_8X;
1108 else if (active_width & MLX5_IB_WIDTH_12X)
1109 *ib_width = IB_WIDTH_12X;
1110 else {
1111 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n",
1112 (int)active_width);
1113 *ib_width = IB_WIDTH_4X;
1114 }
1115
1116 return;
1117}
1118
1119static int mlx5_mtu_to_ib_mtu(int mtu)
1120{
1121 switch (mtu) {
1122 case 256: return 1;
1123 case 512: return 2;
1124 case 1024: return 3;
1125 case 2048: return 4;
1126 case 4096: return 5;
1127 default:
1128 pr_warn("invalid mtu\n");
1129 return -1;
1130 }
1131}
1132
1133enum ib_max_vl_num {
1134 __IB_MAX_VL_0 = 1,
1135 __IB_MAX_VL_0_1 = 2,
1136 __IB_MAX_VL_0_3 = 3,
1137 __IB_MAX_VL_0_7 = 4,
1138 __IB_MAX_VL_0_14 = 5,
1139};
1140
1141enum mlx5_vl_hw_cap {
1142 MLX5_VL_HW_0 = 1,
1143 MLX5_VL_HW_0_1 = 2,
1144 MLX5_VL_HW_0_2 = 3,
1145 MLX5_VL_HW_0_3 = 4,
1146 MLX5_VL_HW_0_4 = 5,
1147 MLX5_VL_HW_0_5 = 6,
1148 MLX5_VL_HW_0_6 = 7,
1149 MLX5_VL_HW_0_7 = 8,
1150 MLX5_VL_HW_0_14 = 15
1151};
1152
1153static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1154 u8 *max_vl_num)
1155{
1156 switch (vl_hw_cap) {
1157 case MLX5_VL_HW_0:
1158 *max_vl_num = __IB_MAX_VL_0;
1159 break;
1160 case MLX5_VL_HW_0_1:
1161 *max_vl_num = __IB_MAX_VL_0_1;
1162 break;
1163 case MLX5_VL_HW_0_3:
1164 *max_vl_num = __IB_MAX_VL_0_3;
1165 break;
1166 case MLX5_VL_HW_0_7:
1167 *max_vl_num = __IB_MAX_VL_0_7;
1168 break;
1169 case MLX5_VL_HW_0_14:
1170 *max_vl_num = __IB_MAX_VL_0_14;
1171 break;
1172
1173 default:
1174 return -EINVAL;
1175 }
1176
1177 return 0;
1178}
1179
1180static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1181 struct ib_port_attr *props)
1182{
1183 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1184 struct mlx5_core_dev *mdev = dev->mdev;
1185 struct mlx5_hca_vport_context *rep;
1186 u16 max_mtu;
1187 u16 oper_mtu;
1188 int err;
1189 u8 ib_link_width_oper;
1190 u8 vl_hw_cap;
1191
1192 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1193 if (!rep) {
1194 err = -ENOMEM;
1195 goto out;
1196 }
1197
1198 /* props being zeroed by the caller, avoid zeroing it here */
1199
1200 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1201 if (err)
1202 goto out;
1203
1204 props->lid = rep->lid;
1205 props->lmc = rep->lmc;
1206 props->sm_lid = rep->sm_lid;
1207 props->sm_sl = rep->sm_sl;
1208 props->state = rep->vport_state;
1209 props->phys_state = rep->port_physical_state;
1210 props->port_cap_flags = rep->cap_mask1;
1211 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1212 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1213 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1214 props->bad_pkey_cntr = rep->pkey_violation_counter;
1215 props->qkey_viol_cntr = rep->qkey_violation_counter;
1216 props->subnet_timeout = rep->subnet_timeout;
1217 props->init_type_reply = rep->init_type_reply;
1218
1219 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1220 if (err)
1221 goto out;
1222
1223 translate_active_width(ibdev, ib_link_width_oper, &props->active_width);
1224
1225 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1226 if (err)
1227 goto out;
1228
1229 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1230
1231 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1232
1233 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1234
1235 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1236
1237 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1238 if (err)
1239 goto out;
1240
1241 err = translate_max_vl_num(ibdev, vl_hw_cap,
1242 &props->max_vl_num);
1243out:
1244 kfree(rep);
1245 return err;
1246}
1247
1248int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1249 struct ib_port_attr *props)
1250{
1251 unsigned int count;
1252 int ret;
1253
1254 switch (mlx5_get_vport_access_method(ibdev)) {
1255 case MLX5_VPORT_ACCESS_METHOD_MAD:
1256 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1257 break;
1258
1259 case MLX5_VPORT_ACCESS_METHOD_HCA:
1260 ret = mlx5_query_hca_port(ibdev, port, props);
1261 break;
1262
1263 case MLX5_VPORT_ACCESS_METHOD_NIC:
1264 ret = mlx5_query_port_roce(ibdev, port, props);
1265 break;
1266
1267 default:
1268 ret = -EINVAL;
1269 }
1270
1271 if (!ret && props) {
1272 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1273 struct mlx5_core_dev *mdev;
1274 bool put_mdev = true;
1275
1276 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1277 if (!mdev) {
1278 /* If the port isn't affiliated yet query the master.
1279 * The master and slave will have the same values.
1280 */
1281 mdev = dev->mdev;
1282 port = 1;
1283 put_mdev = false;
1284 }
1285 count = mlx5_core_reserved_gids_count(mdev);
1286 if (put_mdev)
1287 mlx5_ib_put_native_port_mdev(dev, port);
1288 props->gid_tbl_len -= count;
1289 }
1290 return ret;
1291}
1292
1293static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1294 struct ib_port_attr *props)
1295{
1296 int ret;
1297
1298 /* Only link layer == ethernet is valid for representors */
1299 ret = mlx5_query_port_roce(ibdev, port, props);
1300 if (ret || !props)
1301 return ret;
1302
1303 /* We don't support GIDS */
1304 props->gid_tbl_len = 0;
1305
1306 return ret;
1307}
1308
1309static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1310 union ib_gid *gid)
1311{
1312 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1313 struct mlx5_core_dev *mdev = dev->mdev;
1314
1315 switch (mlx5_get_vport_access_method(ibdev)) {
1316 case MLX5_VPORT_ACCESS_METHOD_MAD:
1317 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1318
1319 case MLX5_VPORT_ACCESS_METHOD_HCA:
1320 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1321
1322 default:
1323 return -EINVAL;
1324 }
1325
1326}
1327
1328static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1329 u16 index, u16 *pkey)
1330{
1331 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1332 struct mlx5_core_dev *mdev;
1333 bool put_mdev = true;
1334 u8 mdev_port_num;
1335 int err;
1336
1337 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1338 if (!mdev) {
1339 /* The port isn't affiliated yet, get the PKey from the master
1340 * port. For RoCE the PKey tables will be the same.
1341 */
1342 put_mdev = false;
1343 mdev = dev->mdev;
1344 mdev_port_num = 1;
1345 }
1346
1347 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1348 index, pkey);
1349 if (put_mdev)
1350 mlx5_ib_put_native_port_mdev(dev, port);
1351
1352 return err;
1353}
1354
1355static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1356 u16 *pkey)
1357{
1358 switch (mlx5_get_vport_access_method(ibdev)) {
1359 case MLX5_VPORT_ACCESS_METHOD_MAD:
1360 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1361
1362 case MLX5_VPORT_ACCESS_METHOD_HCA:
1363 case MLX5_VPORT_ACCESS_METHOD_NIC:
1364 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1365 default:
1366 return -EINVAL;
1367 }
1368}
1369
1370static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1371 struct ib_device_modify *props)
1372{
1373 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1374 struct mlx5_reg_node_desc in;
1375 struct mlx5_reg_node_desc out;
1376 int err;
1377
1378 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1379 return -EOPNOTSUPP;
1380
1381 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1382 return 0;
1383
1384 /*
1385 * If possible, pass node desc to FW, so it can generate
1386 * a 144 trap. If cmd fails, just ignore.
1387 */
1388 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1389 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1390 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1391 if (err)
1392 return err;
1393
1394 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1395
1396 return err;
1397}
1398
1399static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1400 u32 value)
1401{
1402 struct mlx5_hca_vport_context ctx = {};
1403 struct mlx5_core_dev *mdev;
1404 u8 mdev_port_num;
1405 int err;
1406
1407 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1408 if (!mdev)
1409 return -ENODEV;
1410
1411 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1412 if (err)
1413 goto out;
1414
1415 if (~ctx.cap_mask1_perm & mask) {
1416 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1417 mask, ctx.cap_mask1_perm);
1418 err = -EINVAL;
1419 goto out;
1420 }
1421
1422 ctx.cap_mask1 = value;
1423 ctx.cap_mask1_perm = mask;
1424 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1425 0, &ctx);
1426
1427out:
1428 mlx5_ib_put_native_port_mdev(dev, port_num);
1429
1430 return err;
1431}
1432
1433static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1434 struct ib_port_modify *props)
1435{
1436 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1437 struct ib_port_attr attr;
1438 u32 tmp;
1439 int err;
1440 u32 change_mask;
1441 u32 value;
1442 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1443 IB_LINK_LAYER_INFINIBAND);
1444
1445 /* CM layer calls ib_modify_port() regardless of the link layer. For
1446 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1447 */
1448 if (!is_ib)
1449 return 0;
1450
1451 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1452 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1453 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1454 return set_port_caps_atomic(dev, port, change_mask, value);
1455 }
1456
1457 mutex_lock(&dev->cap_mask_mutex);
1458
1459 err = ib_query_port(ibdev, port, &attr);
1460 if (err)
1461 goto out;
1462
1463 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1464 ~props->clr_port_cap_mask;
1465
1466 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1467
1468out:
1469 mutex_unlock(&dev->cap_mask_mutex);
1470 return err;
1471}
1472
1473static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1474{
1475 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1476 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1477}
1478
1479static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1480{
1481 /* Large page with non 4k uar support might limit the dynamic size */
1482 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1483 return MLX5_MIN_DYN_BFREGS;
1484
1485 return MLX5_MAX_DYN_BFREGS;
1486}
1487
1488static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1489 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1490 struct mlx5_bfreg_info *bfregi)
1491{
1492 int uars_per_sys_page;
1493 int bfregs_per_sys_page;
1494 int ref_bfregs = req->total_num_bfregs;
1495
1496 if (req->total_num_bfregs == 0)
1497 return -EINVAL;
1498
1499 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1500 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1501
1502 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1503 return -ENOMEM;
1504
1505 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1506 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1507 /* This holds the required static allocation asked by the user */
1508 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1509 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1510 return -EINVAL;
1511
1512 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1513 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1514 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1515 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1516
1517 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1518 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1519 lib_uar_4k ? "yes" : "no", ref_bfregs,
1520 req->total_num_bfregs, bfregi->total_num_bfregs,
1521 bfregi->num_sys_pages);
1522
1523 return 0;
1524}
1525
1526static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1527{
1528 struct mlx5_bfreg_info *bfregi;
1529 int err;
1530 int i;
1531
1532 bfregi = &context->bfregi;
1533 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1534 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1535 if (err)
1536 goto error;
1537
1538 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1539 }
1540
1541 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1542 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1543
1544 return 0;
1545
1546error:
1547 for (--i; i >= 0; i--)
1548 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1549 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1550
1551 return err;
1552}
1553
1554static void deallocate_uars(struct mlx5_ib_dev *dev,
1555 struct mlx5_ib_ucontext *context)
1556{
1557 struct mlx5_bfreg_info *bfregi;
1558 int i;
1559
1560 bfregi = &context->bfregi;
1561 for (i = 0; i < bfregi->num_sys_pages; i++)
1562 if (i < bfregi->num_static_sys_pages ||
1563 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1564 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1565}
1566
1567static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1568{
1569 int err;
1570
1571 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1572 return 0;
1573
1574 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1575 if (err)
1576 return err;
1577
1578 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1579 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1580 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1581 return err;
1582
1583 mutex_lock(&dev->lb_mutex);
1584 dev->user_td++;
1585
1586 if (dev->user_td == 2)
1587 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1588
1589 mutex_unlock(&dev->lb_mutex);
1590 return err;
1591}
1592
1593static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1594{
1595 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1596 return;
1597
1598 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1599
1600 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1601 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1602 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1603 return;
1604
1605 mutex_lock(&dev->lb_mutex);
1606 dev->user_td--;
1607
1608 if (dev->user_td < 2)
1609 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1610
1611 mutex_unlock(&dev->lb_mutex);
1612}
1613
1614static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1615 struct ib_udata *udata)
1616{
1617 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1618 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1619 struct mlx5_ib_alloc_ucontext_resp resp = {};
1620 struct mlx5_core_dev *mdev = dev->mdev;
1621 struct mlx5_ib_ucontext *context;
1622 struct mlx5_bfreg_info *bfregi;
1623 int ver;
1624 int err;
1625 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1626 max_cqe_version);
1627 u32 dump_fill_mkey;
1628 bool lib_uar_4k;
1629
1630 if (!dev->ib_active)
1631 return ERR_PTR(-EAGAIN);
1632
1633 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1634 ver = 0;
1635 else if (udata->inlen >= min_req_v2)
1636 ver = 2;
1637 else
1638 return ERR_PTR(-EINVAL);
1639
1640 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1641 if (err)
1642 return ERR_PTR(err);
1643
1644 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1645 return ERR_PTR(-EOPNOTSUPP);
1646
1647 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1648 return ERR_PTR(-EOPNOTSUPP);
1649
1650 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1651 MLX5_NON_FP_BFREGS_PER_UAR);
1652 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1653 return ERR_PTR(-EINVAL);
1654
1655 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1656 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1657 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1658 resp.cache_line_size = cache_line_size();
1659 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1660 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1661 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1662 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1663 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1664 resp.cqe_version = min_t(__u8,
1665 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1666 req.max_cqe_version);
1667 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1668 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1669 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1670 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1671 resp.response_length = min(offsetof(typeof(resp), response_length) +
1672 sizeof(resp.response_length), udata->outlen);
1673
1674 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1675 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1676 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1677 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1678 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1679 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1680 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1682 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1683 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1684 }
1685
1686 context = kzalloc(sizeof(*context), GFP_KERNEL);
1687 if (!context)
1688 return ERR_PTR(-ENOMEM);
1689
1690 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1691 bfregi = &context->bfregi;
1692
1693 /* updates req->total_num_bfregs */
1694 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1695 if (err)
1696 goto out_ctx;
1697
1698 mutex_init(&bfregi->lock);
1699 bfregi->lib_uar_4k = lib_uar_4k;
1700 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1701 GFP_KERNEL);
1702 if (!bfregi->count) {
1703 err = -ENOMEM;
1704 goto out_ctx;
1705 }
1706
1707 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1708 sizeof(*bfregi->sys_pages),
1709 GFP_KERNEL);
1710 if (!bfregi->sys_pages) {
1711 err = -ENOMEM;
1712 goto out_count;
1713 }
1714
1715 err = allocate_uars(dev, context);
1716 if (err)
1717 goto out_sys_pages;
1718
1719#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1720 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1721#endif
1722
1723 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1724 if (err)
1725 goto out_uars;
1726
1727 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1728 /* Block DEVX on Infiniband as of SELinux */
1729 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1730 err = -EPERM;
1731 goto out_td;
1732 }
1733
1734 err = mlx5_ib_devx_create(dev, context);
1735 if (err)
1736 goto out_td;
1737 }
1738
1739 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1740 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1741 if (err)
1742 goto out_mdev;
1743 }
1744
1745 INIT_LIST_HEAD(&context->vma_private_list);
1746 mutex_init(&context->vma_private_list_mutex);
1747 INIT_LIST_HEAD(&context->db_page_list);
1748 mutex_init(&context->db_page_mutex);
1749
1750 resp.tot_bfregs = req.total_num_bfregs;
1751 resp.num_ports = dev->num_ports;
1752
1753 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1754 resp.response_length += sizeof(resp.cqe_version);
1755
1756 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1757 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1758 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1759 resp.response_length += sizeof(resp.cmds_supp_uhw);
1760 }
1761
1762 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1763 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1764 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1765 resp.eth_min_inline++;
1766 }
1767 resp.response_length += sizeof(resp.eth_min_inline);
1768 }
1769
1770 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1771 if (mdev->clock_info)
1772 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1773 resp.response_length += sizeof(resp.clock_info_versions);
1774 }
1775
1776 /*
1777 * We don't want to expose information from the PCI bar that is located
1778 * after 4096 bytes, so if the arch only supports larger pages, let's
1779 * pretend we don't support reading the HCA's core clock. This is also
1780 * forced by mmap function.
1781 */
1782 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1783 if (PAGE_SIZE <= 4096) {
1784 resp.comp_mask |=
1785 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1786 resp.hca_core_clock_offset =
1787 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1788 }
1789 resp.response_length += sizeof(resp.hca_core_clock_offset);
1790 }
1791
1792 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1793 resp.response_length += sizeof(resp.log_uar_size);
1794
1795 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1796 resp.response_length += sizeof(resp.num_uars_per_page);
1797
1798 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1799 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1800 resp.response_length += sizeof(resp.num_dyn_bfregs);
1801 }
1802
1803 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1804 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1805 resp.dump_fill_mkey = dump_fill_mkey;
1806 resp.comp_mask |=
1807 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1808 }
1809 resp.response_length += sizeof(resp.dump_fill_mkey);
1810 }
1811
1812 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1813 if (err)
1814 goto out_mdev;
1815
1816 bfregi->ver = ver;
1817 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1818 context->cqe_version = resp.cqe_version;
1819 context->lib_caps = req.lib_caps;
1820 print_lib_caps(dev, context->lib_caps);
1821
1822 return &context->ibucontext;
1823
1824out_mdev:
1825 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1826 mlx5_ib_devx_destroy(dev, context);
1827out_td:
1828 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1829
1830out_uars:
1831 deallocate_uars(dev, context);
1832
1833out_sys_pages:
1834 kfree(bfregi->sys_pages);
1835
1836out_count:
1837 kfree(bfregi->count);
1838
1839out_ctx:
1840 kfree(context);
1841
1842 return ERR_PTR(err);
1843}
1844
1845static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1846{
1847 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1848 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1849 struct mlx5_bfreg_info *bfregi;
1850
1851 if (context->devx_uid)
1852 mlx5_ib_devx_destroy(dev, context);
1853
1854 bfregi = &context->bfregi;
1855 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1856
1857 deallocate_uars(dev, context);
1858 kfree(bfregi->sys_pages);
1859 kfree(bfregi->count);
1860 kfree(context);
1861
1862 return 0;
1863}
1864
1865static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1866 int uar_idx)
1867{
1868 int fw_uars_per_page;
1869
1870 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1871
1872 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1873}
1874
1875static int get_command(unsigned long offset)
1876{
1877 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1878}
1879
1880static int get_arg(unsigned long offset)
1881{
1882 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1883}
1884
1885static int get_index(unsigned long offset)
1886{
1887 return get_arg(offset);
1888}
1889
1890/* Index resides in an extra byte to enable larger values than 255 */
1891static int get_extended_index(unsigned long offset)
1892{
1893 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1894}
1895
1896static void mlx5_ib_vma_open(struct vm_area_struct *area)
1897{
1898 /* vma_open is called when a new VMA is created on top of our VMA. This
1899 * is done through either mremap flow or split_vma (usually due to
1900 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1901 * as this VMA is strongly hardware related. Therefore we set the
1902 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1903 * calling us again and trying to do incorrect actions. We assume that
1904 * the original VMA size is exactly a single page, and therefore all
1905 * "splitting" operation will not happen to it.
1906 */
1907 area->vm_ops = NULL;
1908}
1909
1910static void mlx5_ib_vma_close(struct vm_area_struct *area)
1911{
1912 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1913
1914 /* It's guaranteed that all VMAs opened on a FD are closed before the
1915 * file itself is closed, therefore no sync is needed with the regular
1916 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1917 * However need a sync with accessing the vma as part of
1918 * mlx5_ib_disassociate_ucontext.
1919 * The close operation is usually called under mm->mmap_sem except when
1920 * process is exiting.
1921 * The exiting case is handled explicitly as part of
1922 * mlx5_ib_disassociate_ucontext.
1923 */
1924 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1925
1926 /* setting the vma context pointer to null in the mlx5_ib driver's
1927 * private data, to protect a race condition in
1928 * mlx5_ib_disassociate_ucontext().
1929 */
1930 mlx5_ib_vma_priv_data->vma = NULL;
1931 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1932 list_del(&mlx5_ib_vma_priv_data->list);
1933 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1934 kfree(mlx5_ib_vma_priv_data);
1935}
1936
1937static const struct vm_operations_struct mlx5_ib_vm_ops = {
1938 .open = mlx5_ib_vma_open,
1939 .close = mlx5_ib_vma_close
1940};
1941
1942static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1943 struct mlx5_ib_ucontext *ctx)
1944{
1945 struct mlx5_ib_vma_private_data *vma_prv;
1946 struct list_head *vma_head = &ctx->vma_private_list;
1947
1948 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1949 if (!vma_prv)
1950 return -ENOMEM;
1951
1952 vma_prv->vma = vma;
1953 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1954 vma->vm_private_data = vma_prv;
1955 vma->vm_ops = &mlx5_ib_vm_ops;
1956
1957 mutex_lock(&ctx->vma_private_list_mutex);
1958 list_add(&vma_prv->list, vma_head);
1959 mutex_unlock(&ctx->vma_private_list_mutex);
1960
1961 return 0;
1962}
1963
1964static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1965{
1966 struct vm_area_struct *vma;
1967 struct mlx5_ib_vma_private_data *vma_private, *n;
1968 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1969
1970 mutex_lock(&context->vma_private_list_mutex);
1971 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1972 list) {
1973 vma = vma_private->vma;
1974 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
1975 /* context going to be destroyed, should
1976 * not access ops any more.
1977 */
1978 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1979 vma->vm_ops = NULL;
1980 list_del(&vma_private->list);
1981 kfree(vma_private);
1982 }
1983 mutex_unlock(&context->vma_private_list_mutex);
1984}
1985
1986static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1987{
1988 switch (cmd) {
1989 case MLX5_IB_MMAP_WC_PAGE:
1990 return "WC";
1991 case MLX5_IB_MMAP_REGULAR_PAGE:
1992 return "best effort WC";
1993 case MLX5_IB_MMAP_NC_PAGE:
1994 return "NC";
1995 case MLX5_IB_MMAP_DEVICE_MEM:
1996 return "Device Memory";
1997 default:
1998 return NULL;
1999 }
2000}
2001
2002static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2003 struct vm_area_struct *vma,
2004 struct mlx5_ib_ucontext *context)
2005{
2006 phys_addr_t pfn;
2007 int err;
2008
2009 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2010 return -EINVAL;
2011
2012 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2013 return -EOPNOTSUPP;
2014
2015 if (vma->vm_flags & VM_WRITE)
2016 return -EPERM;
2017
2018 if (!dev->mdev->clock_info_page)
2019 return -EOPNOTSUPP;
2020
2021 pfn = page_to_pfn(dev->mdev->clock_info_page);
2022 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2023 vma->vm_page_prot);
2024 if (err)
2025 return err;
2026
2027 return mlx5_ib_set_vma_data(vma, context);
2028}
2029
2030static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2031 struct vm_area_struct *vma,
2032 struct mlx5_ib_ucontext *context)
2033{
2034 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2035 int err;
2036 unsigned long idx;
2037 phys_addr_t pfn;
2038 pgprot_t prot;
2039 u32 bfreg_dyn_idx = 0;
2040 u32 uar_index;
2041 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2042 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2043 bfregi->num_static_sys_pages;
2044
2045 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2046 return -EINVAL;
2047
2048 if (dyn_uar)
2049 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2050 else
2051 idx = get_index(vma->vm_pgoff);
2052
2053 if (idx >= max_valid_idx) {
2054 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2055 idx, max_valid_idx);
2056 return -EINVAL;
2057 }
2058
2059 switch (cmd) {
2060 case MLX5_IB_MMAP_WC_PAGE:
2061 case MLX5_IB_MMAP_ALLOC_WC:
2062/* Some architectures don't support WC memory */
2063#if defined(CONFIG_X86)
2064 if (!pat_enabled())
2065 return -EPERM;
2066#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2067 return -EPERM;
2068#endif
2069 /* fall through */
2070 case MLX5_IB_MMAP_REGULAR_PAGE:
2071 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2072 prot = pgprot_writecombine(vma->vm_page_prot);
2073 break;
2074 case MLX5_IB_MMAP_NC_PAGE:
2075 prot = pgprot_noncached(vma->vm_page_prot);
2076 break;
2077 default:
2078 return -EINVAL;
2079 }
2080
2081 if (dyn_uar) {
2082 int uars_per_page;
2083
2084 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2085 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2086 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2087 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2088 bfreg_dyn_idx, bfregi->total_num_bfregs);
2089 return -EINVAL;
2090 }
2091
2092 mutex_lock(&bfregi->lock);
2093 /* Fail if uar already allocated, first bfreg index of each
2094 * page holds its count.
2095 */
2096 if (bfregi->count[bfreg_dyn_idx]) {
2097 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2098 mutex_unlock(&bfregi->lock);
2099 return -EINVAL;
2100 }
2101
2102 bfregi->count[bfreg_dyn_idx]++;
2103 mutex_unlock(&bfregi->lock);
2104
2105 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2106 if (err) {
2107 mlx5_ib_warn(dev, "UAR alloc failed\n");
2108 goto free_bfreg;
2109 }
2110 } else {
2111 uar_index = bfregi->sys_pages[idx];
2112 }
2113
2114 pfn = uar_index2pfn(dev, uar_index);
2115 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2116
2117 vma->vm_page_prot = prot;
2118 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2119 PAGE_SIZE, vma->vm_page_prot);
2120 if (err) {
2121 mlx5_ib_err(dev,
2122 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2123 err, mmap_cmd2str(cmd));
2124 err = -EAGAIN;
2125 goto err;
2126 }
2127
2128 err = mlx5_ib_set_vma_data(vma, context);
2129 if (err)
2130 goto err;
2131
2132 if (dyn_uar)
2133 bfregi->sys_pages[idx] = uar_index;
2134 return 0;
2135
2136err:
2137 if (!dyn_uar)
2138 return err;
2139
2140 mlx5_cmd_free_uar(dev->mdev, idx);
2141
2142free_bfreg:
2143 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2144
2145 return err;
2146}
2147
2148static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2149{
2150 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2151 struct mlx5_ib_dev *dev = to_mdev(context->device);
2152 u16 page_idx = get_extended_index(vma->vm_pgoff);
2153 size_t map_size = vma->vm_end - vma->vm_start;
2154 u32 npages = map_size >> PAGE_SHIFT;
2155 phys_addr_t pfn;
2156 pgprot_t prot;
2157
2158 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2159 page_idx + npages)
2160 return -EINVAL;
2161
2162 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2163 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2164 PAGE_SHIFT) +
2165 page_idx;
2166 prot = pgprot_writecombine(vma->vm_page_prot);
2167 vma->vm_page_prot = prot;
2168
2169 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2170 vma->vm_page_prot))
2171 return -EAGAIN;
2172
2173 return mlx5_ib_set_vma_data(vma, mctx);
2174}
2175
2176static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2177{
2178 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2179 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2180 unsigned long command;
2181 phys_addr_t pfn;
2182
2183 command = get_command(vma->vm_pgoff);
2184 switch (command) {
2185 case MLX5_IB_MMAP_WC_PAGE:
2186 case MLX5_IB_MMAP_NC_PAGE:
2187 case MLX5_IB_MMAP_REGULAR_PAGE:
2188 case MLX5_IB_MMAP_ALLOC_WC:
2189 return uar_mmap(dev, command, vma, context);
2190
2191 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2192 return -ENOSYS;
2193
2194 case MLX5_IB_MMAP_CORE_CLOCK:
2195 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2196 return -EINVAL;
2197
2198 if (vma->vm_flags & VM_WRITE)
2199 return -EPERM;
2200
2201 /* Don't expose to user-space information it shouldn't have */
2202 if (PAGE_SIZE > 4096)
2203 return -EOPNOTSUPP;
2204
2205 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2206 pfn = (dev->mdev->iseg_base +
2207 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2208 PAGE_SHIFT;
2209 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2210 PAGE_SIZE, vma->vm_page_prot))
2211 return -EAGAIN;
2212 break;
2213 case MLX5_IB_MMAP_CLOCK_INFO:
2214 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2215
2216 case MLX5_IB_MMAP_DEVICE_MEM:
2217 return dm_mmap(ibcontext, vma);
2218
2219 default:
2220 return -EINVAL;
2221 }
2222
2223 return 0;
2224}
2225
2226struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2227 struct ib_ucontext *context,
2228 struct ib_dm_alloc_attr *attr,
2229 struct uverbs_attr_bundle *attrs)
2230{
2231 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2232 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2233 phys_addr_t memic_addr;
2234 struct mlx5_ib_dm *dm;
2235 u64 start_offset;
2236 u32 page_idx;
2237 int err;
2238
2239 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2240 if (!dm)
2241 return ERR_PTR(-ENOMEM);
2242
2243 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2244 attr->length, act_size, attr->alignment);
2245
2246 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2247 act_size, attr->alignment);
2248 if (err)
2249 goto err_free;
2250
2251 start_offset = memic_addr & ~PAGE_MASK;
2252 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2253 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2254 PAGE_SHIFT;
2255
2256 err = uverbs_copy_to(attrs,
2257 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2258 &start_offset, sizeof(start_offset));
2259 if (err)
2260 goto err_dealloc;
2261
2262 err = uverbs_copy_to(attrs,
2263 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2264 &page_idx, sizeof(page_idx));
2265 if (err)
2266 goto err_dealloc;
2267
2268 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2269 DIV_ROUND_UP(act_size, PAGE_SIZE));
2270
2271 dm->dev_addr = memic_addr;
2272
2273 return &dm->ibdm;
2274
2275err_dealloc:
2276 mlx5_cmd_dealloc_memic(memic, memic_addr,
2277 act_size);
2278err_free:
2279 kfree(dm);
2280 return ERR_PTR(err);
2281}
2282
2283int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2284{
2285 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2286 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2287 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2288 u32 page_idx;
2289 int ret;
2290
2291 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2292 if (ret)
2293 return ret;
2294
2295 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2296 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2297 PAGE_SHIFT;
2298 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2299 page_idx,
2300 DIV_ROUND_UP(act_size, PAGE_SIZE));
2301
2302 kfree(dm);
2303
2304 return 0;
2305}
2306
2307static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2308 struct ib_ucontext *context,
2309 struct ib_udata *udata)
2310{
2311 struct mlx5_ib_alloc_pd_resp resp;
2312 struct mlx5_ib_pd *pd;
2313 int err;
2314
2315 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2316 if (!pd)
2317 return ERR_PTR(-ENOMEM);
2318
2319 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2320 if (err) {
2321 kfree(pd);
2322 return ERR_PTR(err);
2323 }
2324
2325 if (context) {
2326 resp.pdn = pd->pdn;
2327 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2328 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2329 kfree(pd);
2330 return ERR_PTR(-EFAULT);
2331 }
2332 }
2333
2334 return &pd->ibpd;
2335}
2336
2337static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2338{
2339 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2340 struct mlx5_ib_pd *mpd = to_mpd(pd);
2341
2342 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2343 kfree(mpd);
2344
2345 return 0;
2346}
2347
2348enum {
2349 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2350 MATCH_CRITERIA_ENABLE_MISC_BIT,
2351 MATCH_CRITERIA_ENABLE_INNER_BIT,
2352 MATCH_CRITERIA_ENABLE_MISC2_BIT
2353};
2354
2355#define HEADER_IS_ZERO(match_criteria, headers) \
2356 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2357 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2358
2359static u8 get_match_criteria_enable(u32 *match_criteria)
2360{
2361 u8 match_criteria_enable;
2362
2363 match_criteria_enable =
2364 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2365 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2366 match_criteria_enable |=
2367 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2368 MATCH_CRITERIA_ENABLE_MISC_BIT;
2369 match_criteria_enable |=
2370 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2371 MATCH_CRITERIA_ENABLE_INNER_BIT;
2372 match_criteria_enable |=
2373 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2374 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2375
2376 return match_criteria_enable;
2377}
2378
2379static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2380{
2381 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2382 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2383}
2384
2385static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2386 bool inner)
2387{
2388 if (inner) {
2389 MLX5_SET(fte_match_set_misc,
2390 misc_c, inner_ipv6_flow_label, mask);
2391 MLX5_SET(fte_match_set_misc,
2392 misc_v, inner_ipv6_flow_label, val);
2393 } else {
2394 MLX5_SET(fte_match_set_misc,
2395 misc_c, outer_ipv6_flow_label, mask);
2396 MLX5_SET(fte_match_set_misc,
2397 misc_v, outer_ipv6_flow_label, val);
2398 }
2399}
2400
2401static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2402{
2403 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2404 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2405 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2406 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2407}
2408
2409static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2410{
2411 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2412 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2413 return -EOPNOTSUPP;
2414
2415 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2416 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2417 return -EOPNOTSUPP;
2418
2419 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2420 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2421 return -EOPNOTSUPP;
2422
2423 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2424 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2425 return -EOPNOTSUPP;
2426
2427 return 0;
2428}
2429
2430#define LAST_ETH_FIELD vlan_tag
2431#define LAST_IB_FIELD sl
2432#define LAST_IPV4_FIELD tos
2433#define LAST_IPV6_FIELD traffic_class
2434#define LAST_TCP_UDP_FIELD src_port
2435#define LAST_TUNNEL_FIELD tunnel_id
2436#define LAST_FLOW_TAG_FIELD tag_id
2437#define LAST_DROP_FIELD size
2438#define LAST_COUNTERS_FIELD counters
2439
2440/* Field is the last supported field */
2441#define FIELDS_NOT_SUPPORTED(filter, field)\
2442 memchr_inv((void *)&filter.field +\
2443 sizeof(filter.field), 0,\
2444 sizeof(filter) -\
2445 offsetof(typeof(filter), field) -\
2446 sizeof(filter.field))
2447
2448static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2449 const struct ib_flow_attr *flow_attr,
2450 struct mlx5_flow_act *action)
2451{
2452 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2453
2454 switch (maction->ib_action.type) {
2455 case IB_FLOW_ACTION_ESP:
2456 /* Currently only AES_GCM keymat is supported by the driver */
2457 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2458 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2459 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2460 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2461 return 0;
2462 default:
2463 return -EOPNOTSUPP;
2464 }
2465}
2466
2467static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2468 u32 *match_v, const union ib_flow_spec *ib_spec,
2469 const struct ib_flow_attr *flow_attr,
2470 struct mlx5_flow_act *action, u32 prev_type)
2471{
2472 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2473 misc_parameters);
2474 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2475 misc_parameters);
2476 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2477 misc_parameters_2);
2478 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2479 misc_parameters_2);
2480 void *headers_c;
2481 void *headers_v;
2482 int match_ipv;
2483 int ret;
2484
2485 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2486 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2487 inner_headers);
2488 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2489 inner_headers);
2490 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2491 ft_field_support.inner_ip_version);
2492 } else {
2493 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2494 outer_headers);
2495 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2496 outer_headers);
2497 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2498 ft_field_support.outer_ip_version);
2499 }
2500
2501 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2502 case IB_FLOW_SPEC_ETH:
2503 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2504 return -EOPNOTSUPP;
2505
2506 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2507 dmac_47_16),
2508 ib_spec->eth.mask.dst_mac);
2509 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2510 dmac_47_16),
2511 ib_spec->eth.val.dst_mac);
2512
2513 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2514 smac_47_16),
2515 ib_spec->eth.mask.src_mac);
2516 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2517 smac_47_16),
2518 ib_spec->eth.val.src_mac);
2519
2520 if (ib_spec->eth.mask.vlan_tag) {
2521 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2522 cvlan_tag, 1);
2523 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2524 cvlan_tag, 1);
2525
2526 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2527 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2529 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2530
2531 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2532 first_cfi,
2533 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2534 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2535 first_cfi,
2536 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2537
2538 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2539 first_prio,
2540 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2541 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2542 first_prio,
2543 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2544 }
2545 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2546 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2547 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2548 ethertype, ntohs(ib_spec->eth.val.ether_type));
2549 break;
2550 case IB_FLOW_SPEC_IPV4:
2551 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2552 return -EOPNOTSUPP;
2553
2554 if (match_ipv) {
2555 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2556 ip_version, 0xf);
2557 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2558 ip_version, MLX5_FS_IPV4_VERSION);
2559 } else {
2560 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2561 ethertype, 0xffff);
2562 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2563 ethertype, ETH_P_IP);
2564 }
2565
2566 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2567 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2568 &ib_spec->ipv4.mask.src_ip,
2569 sizeof(ib_spec->ipv4.mask.src_ip));
2570 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2571 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2572 &ib_spec->ipv4.val.src_ip,
2573 sizeof(ib_spec->ipv4.val.src_ip));
2574 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2575 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2576 &ib_spec->ipv4.mask.dst_ip,
2577 sizeof(ib_spec->ipv4.mask.dst_ip));
2578 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2579 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2580 &ib_spec->ipv4.val.dst_ip,
2581 sizeof(ib_spec->ipv4.val.dst_ip));
2582
2583 set_tos(headers_c, headers_v,
2584 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2585
2586 set_proto(headers_c, headers_v,
2587 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2588 break;
2589 case IB_FLOW_SPEC_IPV6:
2590 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2591 return -EOPNOTSUPP;
2592
2593 if (match_ipv) {
2594 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2595 ip_version, 0xf);
2596 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2597 ip_version, MLX5_FS_IPV6_VERSION);
2598 } else {
2599 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2600 ethertype, 0xffff);
2601 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2602 ethertype, ETH_P_IPV6);
2603 }
2604
2605 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2606 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2607 &ib_spec->ipv6.mask.src_ip,
2608 sizeof(ib_spec->ipv6.mask.src_ip));
2609 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2610 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2611 &ib_spec->ipv6.val.src_ip,
2612 sizeof(ib_spec->ipv6.val.src_ip));
2613 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2614 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2615 &ib_spec->ipv6.mask.dst_ip,
2616 sizeof(ib_spec->ipv6.mask.dst_ip));
2617 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2618 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2619 &ib_spec->ipv6.val.dst_ip,
2620 sizeof(ib_spec->ipv6.val.dst_ip));
2621
2622 set_tos(headers_c, headers_v,
2623 ib_spec->ipv6.mask.traffic_class,
2624 ib_spec->ipv6.val.traffic_class);
2625
2626 set_proto(headers_c, headers_v,
2627 ib_spec->ipv6.mask.next_hdr,
2628 ib_spec->ipv6.val.next_hdr);
2629
2630 set_flow_label(misc_params_c, misc_params_v,
2631 ntohl(ib_spec->ipv6.mask.flow_label),
2632 ntohl(ib_spec->ipv6.val.flow_label),
2633 ib_spec->type & IB_FLOW_SPEC_INNER);
2634 break;
2635 case IB_FLOW_SPEC_ESP:
2636 if (ib_spec->esp.mask.seq)
2637 return -EOPNOTSUPP;
2638
2639 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2640 ntohl(ib_spec->esp.mask.spi));
2641 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2642 ntohl(ib_spec->esp.val.spi));
2643 break;
2644 case IB_FLOW_SPEC_TCP:
2645 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2646 LAST_TCP_UDP_FIELD))
2647 return -EOPNOTSUPP;
2648
2649 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2650 0xff);
2651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2652 IPPROTO_TCP);
2653
2654 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2655 ntohs(ib_spec->tcp_udp.mask.src_port));
2656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2657 ntohs(ib_spec->tcp_udp.val.src_port));
2658
2659 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2660 ntohs(ib_spec->tcp_udp.mask.dst_port));
2661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2662 ntohs(ib_spec->tcp_udp.val.dst_port));
2663 break;
2664 case IB_FLOW_SPEC_UDP:
2665 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2666 LAST_TCP_UDP_FIELD))
2667 return -EOPNOTSUPP;
2668
2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2670 0xff);
2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2672 IPPROTO_UDP);
2673
2674 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2675 ntohs(ib_spec->tcp_udp.mask.src_port));
2676 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2677 ntohs(ib_spec->tcp_udp.val.src_port));
2678
2679 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2680 ntohs(ib_spec->tcp_udp.mask.dst_port));
2681 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2682 ntohs(ib_spec->tcp_udp.val.dst_port));
2683 break;
2684 case IB_FLOW_SPEC_GRE:
2685 if (ib_spec->gre.mask.c_ks_res0_ver)
2686 return -EOPNOTSUPP;
2687
2688 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2689 0xff);
2690 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2691 IPPROTO_GRE);
2692
2693 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2694 ntohs(ib_spec->gre.mask.protocol));
2695 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2696 ntohs(ib_spec->gre.val.protocol));
2697
2698 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2699 gre_key_h),
2700 &ib_spec->gre.mask.key,
2701 sizeof(ib_spec->gre.mask.key));
2702 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2703 gre_key_h),
2704 &ib_spec->gre.val.key,
2705 sizeof(ib_spec->gre.val.key));
2706 break;
2707 case IB_FLOW_SPEC_MPLS:
2708 switch (prev_type) {
2709 case IB_FLOW_SPEC_UDP:
2710 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2711 ft_field_support.outer_first_mpls_over_udp),
2712 &ib_spec->mpls.mask.tag))
2713 return -EOPNOTSUPP;
2714
2715 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2716 outer_first_mpls_over_udp),
2717 &ib_spec->mpls.val.tag,
2718 sizeof(ib_spec->mpls.val.tag));
2719 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2720 outer_first_mpls_over_udp),
2721 &ib_spec->mpls.mask.tag,
2722 sizeof(ib_spec->mpls.mask.tag));
2723 break;
2724 case IB_FLOW_SPEC_GRE:
2725 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2726 ft_field_support.outer_first_mpls_over_gre),
2727 &ib_spec->mpls.mask.tag))
2728 return -EOPNOTSUPP;
2729
2730 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2731 outer_first_mpls_over_gre),
2732 &ib_spec->mpls.val.tag,
2733 sizeof(ib_spec->mpls.val.tag));
2734 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2735 outer_first_mpls_over_gre),
2736 &ib_spec->mpls.mask.tag,
2737 sizeof(ib_spec->mpls.mask.tag));
2738 break;
2739 default:
2740 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2741 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2742 ft_field_support.inner_first_mpls),
2743 &ib_spec->mpls.mask.tag))
2744 return -EOPNOTSUPP;
2745
2746 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2747 inner_first_mpls),
2748 &ib_spec->mpls.val.tag,
2749 sizeof(ib_spec->mpls.val.tag));
2750 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2751 inner_first_mpls),
2752 &ib_spec->mpls.mask.tag,
2753 sizeof(ib_spec->mpls.mask.tag));
2754 } else {
2755 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2756 ft_field_support.outer_first_mpls),
2757 &ib_spec->mpls.mask.tag))
2758 return -EOPNOTSUPP;
2759
2760 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2761 outer_first_mpls),
2762 &ib_spec->mpls.val.tag,
2763 sizeof(ib_spec->mpls.val.tag));
2764 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2765 outer_first_mpls),
2766 &ib_spec->mpls.mask.tag,
2767 sizeof(ib_spec->mpls.mask.tag));
2768 }
2769 }
2770 break;
2771 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2772 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2773 LAST_TUNNEL_FIELD))
2774 return -EOPNOTSUPP;
2775
2776 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2777 ntohl(ib_spec->tunnel.mask.tunnel_id));
2778 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2779 ntohl(ib_spec->tunnel.val.tunnel_id));
2780 break;
2781 case IB_FLOW_SPEC_ACTION_TAG:
2782 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2783 LAST_FLOW_TAG_FIELD))
2784 return -EOPNOTSUPP;
2785 if (ib_spec->flow_tag.tag_id >= BIT(24))
2786 return -EINVAL;
2787
2788 action->flow_tag = ib_spec->flow_tag.tag_id;
2789 action->has_flow_tag = true;
2790 break;
2791 case IB_FLOW_SPEC_ACTION_DROP:
2792 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2793 LAST_DROP_FIELD))
2794 return -EOPNOTSUPP;
2795 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2796 break;
2797 case IB_FLOW_SPEC_ACTION_HANDLE:
2798 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2799 if (ret)
2800 return ret;
2801 break;
2802 case IB_FLOW_SPEC_ACTION_COUNT:
2803 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2804 LAST_COUNTERS_FIELD))
2805 return -EOPNOTSUPP;
2806
2807 /* for now support only one counters spec per flow */
2808 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2809 return -EINVAL;
2810
2811 action->counters = ib_spec->flow_count.counters;
2812 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2813 break;
2814 default:
2815 return -EINVAL;
2816 }
2817
2818 return 0;
2819}
2820
2821/* If a flow could catch both multicast and unicast packets,
2822 * it won't fall into the multicast flow steering table and this rule
2823 * could steal other multicast packets.
2824 */
2825static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2826{
2827 union ib_flow_spec *flow_spec;
2828
2829 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2830 ib_attr->num_of_specs < 1)
2831 return false;
2832
2833 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2834 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2835 struct ib_flow_spec_ipv4 *ipv4_spec;
2836
2837 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2838 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2839 return true;
2840
2841 return false;
2842 }
2843
2844 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2845 struct ib_flow_spec_eth *eth_spec;
2846
2847 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2848 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2849 is_multicast_ether_addr(eth_spec->val.dst_mac);
2850 }
2851
2852 return false;
2853}
2854
2855enum valid_spec {
2856 VALID_SPEC_INVALID,
2857 VALID_SPEC_VALID,
2858 VALID_SPEC_NA,
2859};
2860
2861static enum valid_spec
2862is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2863 const struct mlx5_flow_spec *spec,
2864 const struct mlx5_flow_act *flow_act,
2865 bool egress)
2866{
2867 const u32 *match_c = spec->match_criteria;
2868 bool is_crypto =
2869 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2870 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2871 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2872 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2873
2874 /*
2875 * Currently only crypto is supported in egress, when regular egress
2876 * rules would be supported, always return VALID_SPEC_NA.
2877 */
2878 if (!is_crypto)
2879 return egress ? VALID_SPEC_INVALID : VALID_SPEC_NA;
2880
2881 return is_crypto && is_ipsec &&
2882 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2883 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2884}
2885
2886static bool is_valid_spec(struct mlx5_core_dev *mdev,
2887 const struct mlx5_flow_spec *spec,
2888 const struct mlx5_flow_act *flow_act,
2889 bool egress)
2890{
2891 /* We curretly only support ipsec egress flow */
2892 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2893}
2894
2895static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2896 const struct ib_flow_attr *flow_attr,
2897 bool check_inner)
2898{
2899 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2900 int match_ipv = check_inner ?
2901 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2902 ft_field_support.inner_ip_version) :
2903 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2904 ft_field_support.outer_ip_version);
2905 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2906 bool ipv4_spec_valid, ipv6_spec_valid;
2907 unsigned int ip_spec_type = 0;
2908 bool has_ethertype = false;
2909 unsigned int spec_index;
2910 bool mask_valid = true;
2911 u16 eth_type = 0;
2912 bool type_valid;
2913
2914 /* Validate that ethertype is correct */
2915 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2916 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2917 ib_spec->eth.mask.ether_type) {
2918 mask_valid = (ib_spec->eth.mask.ether_type ==
2919 htons(0xffff));
2920 has_ethertype = true;
2921 eth_type = ntohs(ib_spec->eth.val.ether_type);
2922 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2923 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2924 ip_spec_type = ib_spec->type;
2925 }
2926 ib_spec = (void *)ib_spec + ib_spec->size;
2927 }
2928
2929 type_valid = (!has_ethertype) || (!ip_spec_type);
2930 if (!type_valid && mask_valid) {
2931 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2932 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2933 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2934 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2935
2936 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2937 (((eth_type == ETH_P_MPLS_UC) ||
2938 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2939 }
2940
2941 return type_valid;
2942}
2943
2944static bool is_valid_attr(struct mlx5_core_dev *mdev,
2945 const struct ib_flow_attr *flow_attr)
2946{
2947 return is_valid_ethertype(mdev, flow_attr, false) &&
2948 is_valid_ethertype(mdev, flow_attr, true);
2949}
2950
2951static void put_flow_table(struct mlx5_ib_dev *dev,
2952 struct mlx5_ib_flow_prio *prio, bool ft_added)
2953{
2954 prio->refcount -= !!ft_added;
2955 if (!prio->refcount) {
2956 mlx5_destroy_flow_table(prio->flow_table);
2957 prio->flow_table = NULL;
2958 }
2959}
2960
2961static void counters_clear_description(struct ib_counters *counters)
2962{
2963 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2964
2965 mutex_lock(&mcounters->mcntrs_mutex);
2966 kfree(mcounters->counters_data);
2967 mcounters->counters_data = NULL;
2968 mcounters->cntrs_max_index = 0;
2969 mutex_unlock(&mcounters->mcntrs_mutex);
2970}
2971
2972static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2973{
2974 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2975 struct mlx5_ib_flow_handler,
2976 ibflow);
2977 struct mlx5_ib_flow_handler *iter, *tmp;
2978 struct mlx5_ib_dev *dev = handler->dev;
2979
2980 mutex_lock(&dev->flow_db->lock);
2981
2982 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2983 mlx5_del_flow_rules(iter->rule);
2984 put_flow_table(dev, iter->prio, true);
2985 list_del(&iter->list);
2986 kfree(iter);
2987 }
2988
2989 mlx5_del_flow_rules(handler->rule);
2990 put_flow_table(dev, handler->prio, true);
2991 if (handler->ibcounters &&
2992 atomic_read(&handler->ibcounters->usecnt) == 1)
2993 counters_clear_description(handler->ibcounters);
2994
2995 mutex_unlock(&dev->flow_db->lock);
2996 if (handler->flow_matcher)
2997 atomic_dec(&handler->flow_matcher->usecnt);
2998 kfree(handler);
2999
3000 return 0;
3001}
3002
3003static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3004{
3005 priority *= 2;
3006 if (!dont_trap)
3007 priority++;
3008 return priority;
3009}
3010
3011enum flow_table_type {
3012 MLX5_IB_FT_RX,
3013 MLX5_IB_FT_TX
3014};
3015
3016#define MLX5_FS_MAX_TYPES 6
3017#define MLX5_FS_MAX_ENTRIES BIT(16)
3018
3019static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3020 struct mlx5_ib_flow_prio *prio,
3021 int priority,
3022 int num_entries, int num_groups)
3023{
3024 struct mlx5_flow_table *ft;
3025
3026 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3027 num_entries,
3028 num_groups,
3029 0, 0);
3030 if (IS_ERR(ft))
3031 return ERR_CAST(ft);
3032
3033 prio->flow_table = ft;
3034 prio->refcount = 0;
3035 return prio;
3036}
3037
3038static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3039 struct ib_flow_attr *flow_attr,
3040 enum flow_table_type ft_type)
3041{
3042 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3043 struct mlx5_flow_namespace *ns = NULL;
3044 struct mlx5_ib_flow_prio *prio;
3045 struct mlx5_flow_table *ft;
3046 int max_table_size;
3047 int num_entries;
3048 int num_groups;
3049 int priority;
3050
3051 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3052 log_max_ft_size));
3053 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3054 if (ft_type == MLX5_IB_FT_TX)
3055 priority = 0;
3056 else if (flow_is_multicast_only(flow_attr) &&
3057 !dont_trap)
3058 priority = MLX5_IB_FLOW_MCAST_PRIO;
3059 else
3060 priority = ib_prio_to_core_prio(flow_attr->priority,
3061 dont_trap);
3062 ns = mlx5_get_flow_namespace(dev->mdev,
3063 ft_type == MLX5_IB_FT_TX ?
3064 MLX5_FLOW_NAMESPACE_EGRESS :
3065 MLX5_FLOW_NAMESPACE_BYPASS);
3066 num_entries = MLX5_FS_MAX_ENTRIES;
3067 num_groups = MLX5_FS_MAX_TYPES;
3068 prio = &dev->flow_db->prios[priority];
3069 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3070 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3071 ns = mlx5_get_flow_namespace(dev->mdev,
3072 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3073 build_leftovers_ft_param(&priority,
3074 &num_entries,
3075 &num_groups);
3076 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3077 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3078 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3079 allow_sniffer_and_nic_rx_shared_tir))
3080 return ERR_PTR(-ENOTSUPP);
3081
3082 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3083 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3084 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3085
3086 prio = &dev->flow_db->sniffer[ft_type];
3087 priority = 0;
3088 num_entries = 1;
3089 num_groups = 1;
3090 }
3091
3092 if (!ns)
3093 return ERR_PTR(-ENOTSUPP);
3094
3095 if (num_entries > max_table_size)
3096 return ERR_PTR(-ENOMEM);
3097
3098 ft = prio->flow_table;
3099 if (!ft)
3100 return _get_prio(ns, prio, priority, num_entries, num_groups);
3101
3102 return prio;
3103}
3104
3105static void set_underlay_qp(struct mlx5_ib_dev *dev,
3106 struct mlx5_flow_spec *spec,
3107 u32 underlay_qpn)
3108{
3109 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3110 spec->match_criteria,
3111 misc_parameters);
3112 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3113 misc_parameters);
3114
3115 if (underlay_qpn &&
3116 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3117 ft_field_support.bth_dst_qp)) {
3118 MLX5_SET(fte_match_set_misc,
3119 misc_params_v, bth_dst_qp, underlay_qpn);
3120 MLX5_SET(fte_match_set_misc,
3121 misc_params_c, bth_dst_qp, 0xffffff);
3122 }
3123}
3124
3125static int read_flow_counters(struct ib_device *ibdev,
3126 struct mlx5_read_counters_attr *read_attr)
3127{
3128 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3129 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3130
3131 return mlx5_fc_query(dev->mdev, fc,
3132 &read_attr->out[IB_COUNTER_PACKETS],
3133 &read_attr->out[IB_COUNTER_BYTES]);
3134}
3135
3136/* flow counters currently expose two counters packets and bytes */
3137#define FLOW_COUNTERS_NUM 2
3138static int counters_set_description(struct ib_counters *counters,
3139 enum mlx5_ib_counters_type counters_type,
3140 struct mlx5_ib_flow_counters_desc *desc_data,
3141 u32 ncounters)
3142{
3143 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3144 u32 cntrs_max_index = 0;
3145 int i;
3146
3147 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3148 return -EINVAL;
3149
3150 /* init the fields for the object */
3151 mcounters->type = counters_type;
3152 mcounters->read_counters = read_flow_counters;
3153 mcounters->counters_num = FLOW_COUNTERS_NUM;
3154 mcounters->ncounters = ncounters;
3155 /* each counter entry have both description and index pair */
3156 for (i = 0; i < ncounters; i++) {
3157 if (desc_data[i].description > IB_COUNTER_BYTES)
3158 return -EINVAL;
3159
3160 if (cntrs_max_index <= desc_data[i].index)
3161 cntrs_max_index = desc_data[i].index + 1;
3162 }
3163
3164 mutex_lock(&mcounters->mcntrs_mutex);
3165 mcounters->counters_data = desc_data;
3166 mcounters->cntrs_max_index = cntrs_max_index;
3167 mutex_unlock(&mcounters->mcntrs_mutex);
3168
3169 return 0;
3170}
3171
3172#define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3173static int flow_counters_set_data(struct ib_counters *ibcounters,
3174 struct mlx5_ib_create_flow *ucmd)
3175{
3176 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3177 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3178 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3179 bool hw_hndl = false;
3180 int ret = 0;
3181
3182 if (ucmd && ucmd->ncounters_data != 0) {
3183 cntrs_data = ucmd->data;
3184 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3185 return -EINVAL;
3186
3187 desc_data = kcalloc(cntrs_data->ncounters,
3188 sizeof(*desc_data),
3189 GFP_KERNEL);
3190 if (!desc_data)
3191 return -ENOMEM;
3192
3193 if (copy_from_user(desc_data,
3194 u64_to_user_ptr(cntrs_data->counters_data),
3195 sizeof(*desc_data) * cntrs_data->ncounters)) {
3196 ret = -EFAULT;
3197 goto free;
3198 }
3199 }
3200
3201 if (!mcounters->hw_cntrs_hndl) {
3202 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3203 to_mdev(ibcounters->device)->mdev, false);
3204 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3205 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3206 goto free;
3207 }
3208 hw_hndl = true;
3209 }
3210
3211 if (desc_data) {
3212 /* counters already bound to at least one flow */
3213 if (mcounters->cntrs_max_index) {
3214 ret = -EINVAL;
3215 goto free_hndl;
3216 }
3217
3218 ret = counters_set_description(ibcounters,
3219 MLX5_IB_COUNTERS_FLOW,
3220 desc_data,
3221 cntrs_data->ncounters);
3222 if (ret)
3223 goto free_hndl;
3224
3225 } else if (!mcounters->cntrs_max_index) {
3226 /* counters not bound yet, must have udata passed */
3227 ret = -EINVAL;
3228 goto free_hndl;
3229 }
3230
3231 return 0;
3232
3233free_hndl:
3234 if (hw_hndl) {
3235 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3236 mcounters->hw_cntrs_hndl);
3237 mcounters->hw_cntrs_hndl = NULL;
3238 }
3239free:
3240 kfree(desc_data);
3241 return ret;
3242}
3243
3244static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3245 struct mlx5_ib_flow_prio *ft_prio,
3246 const struct ib_flow_attr *flow_attr,
3247 struct mlx5_flow_destination *dst,
3248 u32 underlay_qpn,
3249 struct mlx5_ib_create_flow *ucmd)
3250{
3251 struct mlx5_flow_table *ft = ft_prio->flow_table;
3252 struct mlx5_ib_flow_handler *handler;
3253 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3254 struct mlx5_flow_spec *spec;
3255 struct mlx5_flow_destination dest_arr[2] = {};
3256 struct mlx5_flow_destination *rule_dst = dest_arr;
3257 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3258 unsigned int spec_index;
3259 u32 prev_type = 0;
3260 int err = 0;
3261 int dest_num = 0;
3262 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3263
3264 if (!is_valid_attr(dev->mdev, flow_attr))
3265 return ERR_PTR(-EINVAL);
3266
3267 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3268 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3269 if (!handler || !spec) {
3270 err = -ENOMEM;
3271 goto free;
3272 }
3273
3274 INIT_LIST_HEAD(&handler->list);
3275 if (dst) {
3276 memcpy(&dest_arr[0], dst, sizeof(*dst));
3277 dest_num++;
3278 }
3279
3280 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3281 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3282 spec->match_value,
3283 ib_flow, flow_attr, &flow_act,
3284 prev_type);
3285 if (err < 0)
3286 goto free;
3287
3288 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3289 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3290 }
3291
3292 if (!flow_is_multicast_only(flow_attr))
3293 set_underlay_qp(dev, spec, underlay_qpn);
3294
3295 if (dev->rep) {
3296 void *misc;
3297
3298 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3299 misc_parameters);
3300 MLX5_SET(fte_match_set_misc, misc, source_port,
3301 dev->rep->vport);
3302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3303 misc_parameters);
3304 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3305 }
3306
3307 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3308
3309 if (is_egress &&
3310 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3311 err = -EINVAL;
3312 goto free;
3313 }
3314
3315 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3316 err = flow_counters_set_data(flow_act.counters, ucmd);
3317 if (err)
3318 goto free;
3319
3320 handler->ibcounters = flow_act.counters;
3321 dest_arr[dest_num].type =
3322 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3323 dest_arr[dest_num].counter =
3324 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3325 dest_num++;
3326 }
3327
3328 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3329 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3330 rule_dst = NULL;
3331 dest_num = 0;
3332 }
3333 } else {
3334 if (is_egress)
3335 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3336 else
3337 flow_act.action |=
3338 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3339 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3340 }
3341
3342 if (flow_act.has_flow_tag &&
3343 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3344 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3345 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3346 flow_act.flow_tag, flow_attr->type);
3347 err = -EINVAL;
3348 goto free;
3349 }
3350 handler->rule = mlx5_add_flow_rules(ft, spec,
3351 &flow_act,
3352 rule_dst, dest_num);
3353
3354 if (IS_ERR(handler->rule)) {
3355 err = PTR_ERR(handler->rule);
3356 goto free;
3357 }
3358
3359 ft_prio->refcount++;
3360 handler->prio = ft_prio;
3361 handler->dev = dev;
3362
3363 ft_prio->flow_table = ft;
3364free:
3365 if (err && handler) {
3366 if (handler->ibcounters &&
3367 atomic_read(&handler->ibcounters->usecnt) == 1)
3368 counters_clear_description(handler->ibcounters);
3369 kfree(handler);
3370 }
3371 kvfree(spec);
3372 return err ? ERR_PTR(err) : handler;
3373}
3374
3375static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3376 struct mlx5_ib_flow_prio *ft_prio,
3377 const struct ib_flow_attr *flow_attr,
3378 struct mlx5_flow_destination *dst)
3379{
3380 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3381}
3382
3383static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3384 struct mlx5_ib_flow_prio *ft_prio,
3385 struct ib_flow_attr *flow_attr,
3386 struct mlx5_flow_destination *dst)
3387{
3388 struct mlx5_ib_flow_handler *handler_dst = NULL;
3389 struct mlx5_ib_flow_handler *handler = NULL;
3390
3391 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3392 if (!IS_ERR(handler)) {
3393 handler_dst = create_flow_rule(dev, ft_prio,
3394 flow_attr, dst);
3395 if (IS_ERR(handler_dst)) {
3396 mlx5_del_flow_rules(handler->rule);
3397 ft_prio->refcount--;
3398 kfree(handler);
3399 handler = handler_dst;
3400 } else {
3401 list_add(&handler_dst->list, &handler->list);
3402 }
3403 }
3404
3405 return handler;
3406}
3407enum {
3408 LEFTOVERS_MC,
3409 LEFTOVERS_UC,
3410};
3411
3412static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3413 struct mlx5_ib_flow_prio *ft_prio,
3414 struct ib_flow_attr *flow_attr,
3415 struct mlx5_flow_destination *dst)
3416{
3417 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3418 struct mlx5_ib_flow_handler *handler = NULL;
3419
3420 static struct {
3421 struct ib_flow_attr flow_attr;
3422 struct ib_flow_spec_eth eth_flow;
3423 } leftovers_specs[] = {
3424 [LEFTOVERS_MC] = {
3425 .flow_attr = {
3426 .num_of_specs = 1,
3427 .size = sizeof(leftovers_specs[0])
3428 },
3429 .eth_flow = {
3430 .type = IB_FLOW_SPEC_ETH,
3431 .size = sizeof(struct ib_flow_spec_eth),
3432 .mask = {.dst_mac = {0x1} },
3433 .val = {.dst_mac = {0x1} }
3434 }
3435 },
3436 [LEFTOVERS_UC] = {
3437 .flow_attr = {
3438 .num_of_specs = 1,
3439 .size = sizeof(leftovers_specs[0])
3440 },
3441 .eth_flow = {
3442 .type = IB_FLOW_SPEC_ETH,
3443 .size = sizeof(struct ib_flow_spec_eth),
3444 .mask = {.dst_mac = {0x1} },
3445 .val = {.dst_mac = {} }
3446 }
3447 }
3448 };
3449
3450 handler = create_flow_rule(dev, ft_prio,
3451 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3452 dst);
3453 if (!IS_ERR(handler) &&
3454 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3455 handler_ucast = create_flow_rule(dev, ft_prio,
3456 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3457 dst);
3458 if (IS_ERR(handler_ucast)) {
3459 mlx5_del_flow_rules(handler->rule);
3460 ft_prio->refcount--;
3461 kfree(handler);
3462 handler = handler_ucast;
3463 } else {
3464 list_add(&handler_ucast->list, &handler->list);
3465 }
3466 }
3467
3468 return handler;
3469}
3470
3471static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3472 struct mlx5_ib_flow_prio *ft_rx,
3473 struct mlx5_ib_flow_prio *ft_tx,
3474 struct mlx5_flow_destination *dst)
3475{
3476 struct mlx5_ib_flow_handler *handler_rx;
3477 struct mlx5_ib_flow_handler *handler_tx;
3478 int err;
3479 static const struct ib_flow_attr flow_attr = {
3480 .num_of_specs = 0,
3481 .size = sizeof(flow_attr)
3482 };
3483
3484 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3485 if (IS_ERR(handler_rx)) {
3486 err = PTR_ERR(handler_rx);
3487 goto err;
3488 }
3489
3490 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3491 if (IS_ERR(handler_tx)) {
3492 err = PTR_ERR(handler_tx);
3493 goto err_tx;
3494 }
3495
3496 list_add(&handler_tx->list, &handler_rx->list);
3497
3498 return handler_rx;
3499
3500err_tx:
3501 mlx5_del_flow_rules(handler_rx->rule);
3502 ft_rx->refcount--;
3503 kfree(handler_rx);
3504err:
3505 return ERR_PTR(err);
3506}
3507
3508static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3509 struct ib_flow_attr *flow_attr,
3510 int domain,
3511 struct ib_udata *udata)
3512{
3513 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3514 struct mlx5_ib_qp *mqp = to_mqp(qp);
3515 struct mlx5_ib_flow_handler *handler = NULL;
3516 struct mlx5_flow_destination *dst = NULL;
3517 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3518 struct mlx5_ib_flow_prio *ft_prio;
3519 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3520 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3521 size_t min_ucmd_sz, required_ucmd_sz;
3522 int err;
3523 int underlay_qpn;
3524
3525 if (udata && udata->inlen) {
3526 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3527 sizeof(ucmd_hdr.reserved);
3528 if (udata->inlen < min_ucmd_sz)
3529 return ERR_PTR(-EOPNOTSUPP);
3530
3531 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3532 if (err)
3533 return ERR_PTR(err);
3534
3535 /* currently supports only one counters data */
3536 if (ucmd_hdr.ncounters_data > 1)
3537 return ERR_PTR(-EINVAL);
3538
3539 required_ucmd_sz = min_ucmd_sz +
3540 sizeof(struct mlx5_ib_flow_counters_data) *
3541 ucmd_hdr.ncounters_data;
3542 if (udata->inlen > required_ucmd_sz &&
3543 !ib_is_udata_cleared(udata, required_ucmd_sz,
3544 udata->inlen - required_ucmd_sz))
3545 return ERR_PTR(-EOPNOTSUPP);
3546
3547 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3548 if (!ucmd)
3549 return ERR_PTR(-ENOMEM);
3550
3551 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3552 if (err)
3553 goto free_ucmd;
3554 }
3555
3556 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3557 err = -ENOMEM;
3558 goto free_ucmd;
3559 }
3560
3561 if (domain != IB_FLOW_DOMAIN_USER ||
3562 flow_attr->port > dev->num_ports ||
3563 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3564 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3565 err = -EINVAL;
3566 goto free_ucmd;
3567 }
3568
3569 if (is_egress &&
3570 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3571 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3572 err = -EINVAL;
3573 goto free_ucmd;
3574 }
3575
3576 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3577 if (!dst) {
3578 err = -ENOMEM;
3579 goto free_ucmd;
3580 }
3581
3582 mutex_lock(&dev->flow_db->lock);
3583
3584 ft_prio = get_flow_table(dev, flow_attr,
3585 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3586 if (IS_ERR(ft_prio)) {
3587 err = PTR_ERR(ft_prio);
3588 goto unlock;
3589 }
3590 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3591 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3592 if (IS_ERR(ft_prio_tx)) {
3593 err = PTR_ERR(ft_prio_tx);
3594 ft_prio_tx = NULL;
3595 goto destroy_ft;
3596 }
3597 }
3598
3599 if (is_egress) {
3600 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3601 } else {
3602 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3603 if (mqp->flags & MLX5_IB_QP_RSS)
3604 dst->tir_num = mqp->rss_qp.tirn;
3605 else
3606 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3607 }
3608
3609 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3610 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3611 handler = create_dont_trap_rule(dev, ft_prio,
3612 flow_attr, dst);
3613 } else {
3614 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3615 mqp->underlay_qpn : 0;
3616 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3617 dst, underlay_qpn, ucmd);
3618 }
3619 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3620 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3621 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3622 dst);
3623 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3624 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3625 } else {
3626 err = -EINVAL;
3627 goto destroy_ft;
3628 }
3629
3630 if (IS_ERR(handler)) {
3631 err = PTR_ERR(handler);
3632 handler = NULL;
3633 goto destroy_ft;
3634 }
3635
3636 mutex_unlock(&dev->flow_db->lock);
3637 kfree(dst);
3638 kfree(ucmd);
3639
3640 return &handler->ibflow;
3641
3642destroy_ft:
3643 put_flow_table(dev, ft_prio, false);
3644 if (ft_prio_tx)
3645 put_flow_table(dev, ft_prio_tx, false);
3646unlock:
3647 mutex_unlock(&dev->flow_db->lock);
3648 kfree(dst);
3649free_ucmd:
3650 kfree(ucmd);
3651 return ERR_PTR(err);
3652}
3653
3654static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3655 int priority, bool mcast)
3656{
3657 int max_table_size;
3658 struct mlx5_flow_namespace *ns = NULL;
3659 struct mlx5_ib_flow_prio *prio;
3660
3661 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3662 log_max_ft_size));
3663 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3664 return ERR_PTR(-ENOMEM);
3665
3666 if (mcast)
3667 priority = MLX5_IB_FLOW_MCAST_PRIO;
3668 else
3669 priority = ib_prio_to_core_prio(priority, false);
3670
3671 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3672 if (!ns)
3673 return ERR_PTR(-ENOTSUPP);
3674
3675 prio = &dev->flow_db->prios[priority];
3676
3677 if (prio->flow_table)
3678 return prio;
3679
3680 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3681 MLX5_FS_MAX_TYPES);
3682}
3683
3684static struct mlx5_ib_flow_handler *
3685_create_raw_flow_rule(struct mlx5_ib_dev *dev,
3686 struct mlx5_ib_flow_prio *ft_prio,
3687 struct mlx5_flow_destination *dst,
3688 struct mlx5_ib_flow_matcher *fs_matcher,
3689 void *cmd_in, int inlen)
3690{
3691 struct mlx5_ib_flow_handler *handler;
3692 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3693 struct mlx5_flow_spec *spec;
3694 struct mlx5_flow_table *ft = ft_prio->flow_table;
3695 int err = 0;
3696
3697 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3698 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3699 if (!handler || !spec) {
3700 err = -ENOMEM;
3701 goto free;
3702 }
3703
3704 INIT_LIST_HEAD(&handler->list);
3705
3706 memcpy(spec->match_value, cmd_in, inlen);
3707 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3708 fs_matcher->mask_len);
3709 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3710
3711 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3712 handler->rule = mlx5_add_flow_rules(ft, spec,
3713 &flow_act, dst, 1);
3714
3715 if (IS_ERR(handler->rule)) {
3716 err = PTR_ERR(handler->rule);
3717 goto free;
3718 }
3719
3720 ft_prio->refcount++;
3721 handler->prio = ft_prio;
3722 handler->dev = dev;
3723 ft_prio->flow_table = ft;
3724
3725free:
3726 if (err)
3727 kfree(handler);
3728 kvfree(spec);
3729 return err ? ERR_PTR(err) : handler;
3730}
3731
3732static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3733 void *match_v)
3734{
3735 void *match_c;
3736 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3737 void *dmac, *dmac_mask;
3738 void *ipv4, *ipv4_mask;
3739
3740 if (!(fs_matcher->match_criteria_enable &
3741 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3742 return false;
3743
3744 match_c = fs_matcher->matcher_mask.match_params;
3745 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3746 outer_headers);
3747 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3748 outer_headers);
3749
3750 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3751 dmac_47_16);
3752 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3753 dmac_47_16);
3754
3755 if (is_multicast_ether_addr(dmac) &&
3756 is_multicast_ether_addr(dmac_mask))
3757 return true;
3758
3759 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3760 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3761
3762 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3763 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3764
3765 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3766 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3767 return true;
3768
3769 return false;
3770}
3771
3772struct mlx5_ib_flow_handler *
3773mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3774 struct mlx5_ib_flow_matcher *fs_matcher,
3775 void *cmd_in, int inlen, int dest_id,
3776 int dest_type)
3777{
3778 struct mlx5_flow_destination *dst;
3779 struct mlx5_ib_flow_prio *ft_prio;
3780 int priority = fs_matcher->priority;
3781 struct mlx5_ib_flow_handler *handler;
3782 bool mcast;
3783 int err;
3784
3785 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3786 return ERR_PTR(-EOPNOTSUPP);
3787
3788 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3789 return ERR_PTR(-ENOMEM);
3790
3791 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3792 if (!dst)
3793 return ERR_PTR(-ENOMEM);
3794
3795 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3796 mutex_lock(&dev->flow_db->lock);
3797
3798 ft_prio = _get_flow_table(dev, priority, mcast);
3799 if (IS_ERR(ft_prio)) {
3800 err = PTR_ERR(ft_prio);
3801 goto unlock;
3802 }
3803
3804 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3805 dst->type = dest_type;
3806 dst->tir_num = dest_id;
3807 } else {
3808 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3809 dst->ft_num = dest_id;
3810 }
3811
3812 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3813 inlen);
3814
3815 if (IS_ERR(handler)) {
3816 err = PTR_ERR(handler);
3817 goto destroy_ft;
3818 }
3819
3820 mutex_unlock(&dev->flow_db->lock);
3821 atomic_inc(&fs_matcher->usecnt);
3822 handler->flow_matcher = fs_matcher;
3823
3824 kfree(dst);
3825
3826 return handler;
3827
3828destroy_ft:
3829 put_flow_table(dev, ft_prio, false);
3830unlock:
3831 mutex_unlock(&dev->flow_db->lock);
3832 kfree(dst);
3833
3834 return ERR_PTR(err);
3835}
3836
3837static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3838{
3839 u32 flags = 0;
3840
3841 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3842 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3843
3844 return flags;
3845}
3846
3847#define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3848static struct ib_flow_action *
3849mlx5_ib_create_flow_action_esp(struct ib_device *device,
3850 const struct ib_flow_action_attrs_esp *attr,
3851 struct uverbs_attr_bundle *attrs)
3852{
3853 struct mlx5_ib_dev *mdev = to_mdev(device);
3854 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3855 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3856 struct mlx5_ib_flow_action *action;
3857 u64 action_flags;
3858 u64 flags;
3859 int err = 0;
3860
3861 err = uverbs_get_flags64(
3862 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3863 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3864 if (err)
3865 return ERR_PTR(err);
3866
3867 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3868
3869 /* We current only support a subset of the standard features. Only a
3870 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3871 * (with overlap). Full offload mode isn't supported.
3872 */
3873 if (!attr->keymat || attr->replay || attr->encap ||
3874 attr->spi || attr->seq || attr->tfc_pad ||
3875 attr->hard_limit_pkts ||
3876 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3877 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3878 return ERR_PTR(-EOPNOTSUPP);
3879
3880 if (attr->keymat->protocol !=
3881 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3882 return ERR_PTR(-EOPNOTSUPP);
3883
3884 aes_gcm = &attr->keymat->keymat.aes_gcm;
3885
3886 if (aes_gcm->icv_len != 16 ||
3887 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3888 return ERR_PTR(-EOPNOTSUPP);
3889
3890 action = kmalloc(sizeof(*action), GFP_KERNEL);
3891 if (!action)
3892 return ERR_PTR(-ENOMEM);
3893
3894 action->esp_aes_gcm.ib_flags = attr->flags;
3895 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3896 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3897 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3898 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3899 sizeof(accel_attrs.keymat.aes_gcm.salt));
3900 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3901 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3902 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3903 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3904 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3905
3906 accel_attrs.esn = attr->esn;
3907 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3908 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3909 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3910 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3911
3912 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3913 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3914
3915 action->esp_aes_gcm.ctx =
3916 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3917 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3918 err = PTR_ERR(action->esp_aes_gcm.ctx);
3919 goto err_parse;
3920 }
3921
3922 action->esp_aes_gcm.ib_flags = attr->flags;
3923
3924 return &action->ib_action;
3925
3926err_parse:
3927 kfree(action);
3928 return ERR_PTR(err);
3929}
3930
3931static int
3932mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3933 const struct ib_flow_action_attrs_esp *attr,
3934 struct uverbs_attr_bundle *attrs)
3935{
3936 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3937 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3938 int err = 0;
3939
3940 if (attr->keymat || attr->replay || attr->encap ||
3941 attr->spi || attr->seq || attr->tfc_pad ||
3942 attr->hard_limit_pkts ||
3943 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3944 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3945 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3946 return -EOPNOTSUPP;
3947
3948 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3949 * be modified.
3950 */
3951 if (!(maction->esp_aes_gcm.ib_flags &
3952 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3953 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3954 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3955 return -EINVAL;
3956
3957 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3958 sizeof(accel_attrs));
3959
3960 accel_attrs.esn = attr->esn;
3961 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3962 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3963 else
3964 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3965
3966 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3967 &accel_attrs);
3968 if (err)
3969 return err;
3970
3971 maction->esp_aes_gcm.ib_flags &=
3972 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3973 maction->esp_aes_gcm.ib_flags |=
3974 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
3975
3976 return 0;
3977}
3978
3979static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
3980{
3981 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3982
3983 switch (action->type) {
3984 case IB_FLOW_ACTION_ESP:
3985 /*
3986 * We only support aes_gcm by now, so we implicitly know this is
3987 * the underline crypto.
3988 */
3989 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
3990 break;
3991 default:
3992 WARN_ON(true);
3993 break;
3994 }
3995
3996 kfree(maction);
3997 return 0;
3998}
3999
4000static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4001{
4002 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4003 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4004 int err;
4005
4006 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4007 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4008 return -EOPNOTSUPP;
4009 }
4010
4011 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
4012 if (err)
4013 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4014 ibqp->qp_num, gid->raw);
4015
4016 return err;
4017}
4018
4019static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4020{
4021 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4022 int err;
4023
4024 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
4025 if (err)
4026 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4027 ibqp->qp_num, gid->raw);
4028
4029 return err;
4030}
4031
4032static int init_node_data(struct mlx5_ib_dev *dev)
4033{
4034 int err;
4035
4036 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4037 if (err)
4038 return err;
4039
4040 dev->mdev->rev_id = dev->mdev->pdev->revision;
4041
4042 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4043}
4044
4045static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4046 char *buf)
4047{
4048 struct mlx5_ib_dev *dev =
4049 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4050
4051 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4052}
4053
4054static ssize_t show_reg_pages(struct device *device,
4055 struct device_attribute *attr, char *buf)
4056{
4057 struct mlx5_ib_dev *dev =
4058 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4059
4060 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4061}
4062
4063static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4064 char *buf)
4065{
4066 struct mlx5_ib_dev *dev =
4067 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4068 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4069}
4070
4071static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4072 char *buf)
4073{
4074 struct mlx5_ib_dev *dev =
4075 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4076 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4077}
4078
4079static ssize_t show_board(struct device *device, struct device_attribute *attr,
4080 char *buf)
4081{
4082 struct mlx5_ib_dev *dev =
4083 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4084 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4085 dev->mdev->board_id);
4086}
4087
4088static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
4089static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4090static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4091static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4092static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4093
4094static struct device_attribute *mlx5_class_attributes[] = {
4095 &dev_attr_hw_rev,
4096 &dev_attr_hca_type,
4097 &dev_attr_board_id,
4098 &dev_attr_fw_pages,
4099 &dev_attr_reg_pages,
4100};
4101
4102static void pkey_change_handler(struct work_struct *work)
4103{
4104 struct mlx5_ib_port_resources *ports =
4105 container_of(work, struct mlx5_ib_port_resources,
4106 pkey_change_work);
4107
4108 mutex_lock(&ports->devr->mutex);
4109 mlx5_ib_gsi_pkey_change(ports->gsi);
4110 mutex_unlock(&ports->devr->mutex);
4111}
4112
4113static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4114{
4115 struct mlx5_ib_qp *mqp;
4116 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4117 struct mlx5_core_cq *mcq;
4118 struct list_head cq_armed_list;
4119 unsigned long flags_qp;
4120 unsigned long flags_cq;
4121 unsigned long flags;
4122
4123 INIT_LIST_HEAD(&cq_armed_list);
4124
4125 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4126 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4127 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4128 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4129 if (mqp->sq.tail != mqp->sq.head) {
4130 send_mcq = to_mcq(mqp->ibqp.send_cq);
4131 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4132 if (send_mcq->mcq.comp &&
4133 mqp->ibqp.send_cq->comp_handler) {
4134 if (!send_mcq->mcq.reset_notify_added) {
4135 send_mcq->mcq.reset_notify_added = 1;
4136 list_add_tail(&send_mcq->mcq.reset_notify,
4137 &cq_armed_list);
4138 }
4139 }
4140 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4141 }
4142 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4143 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4144 /* no handling is needed for SRQ */
4145 if (!mqp->ibqp.srq) {
4146 if (mqp->rq.tail != mqp->rq.head) {
4147 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4148 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4149 if (recv_mcq->mcq.comp &&
4150 mqp->ibqp.recv_cq->comp_handler) {
4151 if (!recv_mcq->mcq.reset_notify_added) {
4152 recv_mcq->mcq.reset_notify_added = 1;
4153 list_add_tail(&recv_mcq->mcq.reset_notify,
4154 &cq_armed_list);
4155 }
4156 }
4157 spin_unlock_irqrestore(&recv_mcq->lock,
4158 flags_cq);
4159 }
4160 }
4161 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4162 }
4163 /*At that point all inflight post send were put to be executed as of we
4164 * lock/unlock above locks Now need to arm all involved CQs.
4165 */
4166 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4167 mcq->comp(mcq);
4168 }
4169 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4170}
4171
4172static void delay_drop_handler(struct work_struct *work)
4173{
4174 int err;
4175 struct mlx5_ib_delay_drop *delay_drop =
4176 container_of(work, struct mlx5_ib_delay_drop,
4177 delay_drop_work);
4178
4179 atomic_inc(&delay_drop->events_cnt);
4180
4181 mutex_lock(&delay_drop->lock);
4182 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4183 delay_drop->timeout);
4184 if (err) {
4185 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4186 delay_drop->timeout);
4187 delay_drop->activate = false;
4188 }
4189 mutex_unlock(&delay_drop->lock);
4190}
4191
4192static void mlx5_ib_handle_event(struct work_struct *_work)
4193{
4194 struct mlx5_ib_event_work *work =
4195 container_of(_work, struct mlx5_ib_event_work, work);
4196 struct mlx5_ib_dev *ibdev;
4197 struct ib_event ibev;
4198 bool fatal = false;
4199 u8 port = (u8)work->param;
4200
4201 if (mlx5_core_is_mp_slave(work->dev)) {
4202 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4203 if (!ibdev)
4204 goto out;
4205 } else {
4206 ibdev = work->context;
4207 }
4208
4209 switch (work->event) {
4210 case MLX5_DEV_EVENT_SYS_ERROR:
4211 ibev.event = IB_EVENT_DEVICE_FATAL;
4212 mlx5_ib_handle_internal_error(ibdev);
4213 fatal = true;
4214 break;
4215
4216 case MLX5_DEV_EVENT_PORT_UP:
4217 case MLX5_DEV_EVENT_PORT_DOWN:
4218 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4219 /* In RoCE, port up/down events are handled in
4220 * mlx5_netdev_event().
4221 */
4222 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4223 IB_LINK_LAYER_ETHERNET)
4224 goto out;
4225
4226 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4227 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4228 break;
4229
4230 case MLX5_DEV_EVENT_LID_CHANGE:
4231 ibev.event = IB_EVENT_LID_CHANGE;
4232 break;
4233
4234 case MLX5_DEV_EVENT_PKEY_CHANGE:
4235 ibev.event = IB_EVENT_PKEY_CHANGE;
4236 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4237 break;
4238
4239 case MLX5_DEV_EVENT_GUID_CHANGE:
4240 ibev.event = IB_EVENT_GID_CHANGE;
4241 break;
4242
4243 case MLX5_DEV_EVENT_CLIENT_REREG:
4244 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4245 break;
4246 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4247 schedule_work(&ibdev->delay_drop.delay_drop_work);
4248 goto out;
4249 default:
4250 goto out;
4251 }
4252
4253 ibev.device = &ibdev->ib_dev;
4254 ibev.element.port_num = port;
4255
4256 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4257 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4258 goto out;
4259 }
4260
4261 if (ibdev->ib_active)
4262 ib_dispatch_event(&ibev);
4263
4264 if (fatal)
4265 ibdev->ib_active = false;
4266out:
4267 kfree(work);
4268}
4269
4270static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4271 enum mlx5_dev_event event, unsigned long param)
4272{
4273 struct mlx5_ib_event_work *work;
4274
4275 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4276 if (!work)
4277 return;
4278
4279 INIT_WORK(&work->work, mlx5_ib_handle_event);
4280 work->dev = dev;
4281 work->param = param;
4282 work->context = context;
4283 work->event = event;
4284
4285 queue_work(mlx5_ib_event_wq, &work->work);
4286}
4287
4288static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4289{
4290 struct mlx5_hca_vport_context vport_ctx;
4291 int err;
4292 int port;
4293
4294 for (port = 1; port <= dev->num_ports; port++) {
4295 dev->mdev->port_caps[port - 1].has_smi = false;
4296 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4297 MLX5_CAP_PORT_TYPE_IB) {
4298 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4299 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4300 port, 0,
4301 &vport_ctx);
4302 if (err) {
4303 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4304 port, err);
4305 return err;
4306 }
4307 dev->mdev->port_caps[port - 1].has_smi =
4308 vport_ctx.has_smi;
4309 } else {
4310 dev->mdev->port_caps[port - 1].has_smi = true;
4311 }
4312 }
4313 }
4314 return 0;
4315}
4316
4317static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4318{
4319 int port;
4320
4321 for (port = 1; port <= dev->num_ports; port++)
4322 mlx5_query_ext_port_caps(dev, port);
4323}
4324
4325static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4326{
4327 struct ib_device_attr *dprops = NULL;
4328 struct ib_port_attr *pprops = NULL;
4329 int err = -ENOMEM;
4330 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4331
4332 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4333 if (!pprops)
4334 goto out;
4335
4336 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4337 if (!dprops)
4338 goto out;
4339
4340 err = set_has_smi_cap(dev);
4341 if (err)
4342 goto out;
4343
4344 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4345 if (err) {
4346 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4347 goto out;
4348 }
4349
4350 memset(pprops, 0, sizeof(*pprops));
4351 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4352 if (err) {
4353 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4354 port, err);
4355 goto out;
4356 }
4357
4358 dev->mdev->port_caps[port - 1].pkey_table_len =
4359 dprops->max_pkeys;
4360 dev->mdev->port_caps[port - 1].gid_table_len =
4361 pprops->gid_tbl_len;
4362 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4363 port, dprops->max_pkeys, pprops->gid_tbl_len);
4364
4365out:
4366 kfree(pprops);
4367 kfree(dprops);
4368
4369 return err;
4370}
4371
4372static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4373{
4374 int err;
4375
4376 err = mlx5_mr_cache_cleanup(dev);
4377 if (err)
4378 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4379
4380 if (dev->umrc.qp)
4381 mlx5_ib_destroy_qp(dev->umrc.qp);
4382 if (dev->umrc.cq)
4383 ib_free_cq(dev->umrc.cq);
4384 if (dev->umrc.pd)
4385 ib_dealloc_pd(dev->umrc.pd);
4386}
4387
4388enum {
4389 MAX_UMR_WR = 128,
4390};
4391
4392static int create_umr_res(struct mlx5_ib_dev *dev)
4393{
4394 struct ib_qp_init_attr *init_attr = NULL;
4395 struct ib_qp_attr *attr = NULL;
4396 struct ib_pd *pd;
4397 struct ib_cq *cq;
4398 struct ib_qp *qp;
4399 int ret;
4400
4401 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4402 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4403 if (!attr || !init_attr) {
4404 ret = -ENOMEM;
4405 goto error_0;
4406 }
4407
4408 pd = ib_alloc_pd(&dev->ib_dev, 0);
4409 if (IS_ERR(pd)) {
4410 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4411 ret = PTR_ERR(pd);
4412 goto error_0;
4413 }
4414
4415 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4416 if (IS_ERR(cq)) {
4417 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4418 ret = PTR_ERR(cq);
4419 goto error_2;
4420 }
4421
4422 init_attr->send_cq = cq;
4423 init_attr->recv_cq = cq;
4424 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4425 init_attr->cap.max_send_wr = MAX_UMR_WR;
4426 init_attr->cap.max_send_sge = 1;
4427 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4428 init_attr->port_num = 1;
4429 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4430 if (IS_ERR(qp)) {
4431 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4432 ret = PTR_ERR(qp);
4433 goto error_3;
4434 }
4435 qp->device = &dev->ib_dev;
4436 qp->real_qp = qp;
4437 qp->uobject = NULL;
4438 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4439 qp->send_cq = init_attr->send_cq;
4440 qp->recv_cq = init_attr->recv_cq;
4441
4442 attr->qp_state = IB_QPS_INIT;
4443 attr->port_num = 1;
4444 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4445 IB_QP_PORT, NULL);
4446 if (ret) {
4447 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4448 goto error_4;
4449 }
4450
4451 memset(attr, 0, sizeof(*attr));
4452 attr->qp_state = IB_QPS_RTR;
4453 attr->path_mtu = IB_MTU_256;
4454
4455 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4456 if (ret) {
4457 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4458 goto error_4;
4459 }
4460
4461 memset(attr, 0, sizeof(*attr));
4462 attr->qp_state = IB_QPS_RTS;
4463 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4464 if (ret) {
4465 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4466 goto error_4;
4467 }
4468
4469 dev->umrc.qp = qp;
4470 dev->umrc.cq = cq;
4471 dev->umrc.pd = pd;
4472
4473 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4474 ret = mlx5_mr_cache_init(dev);
4475 if (ret) {
4476 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4477 goto error_4;
4478 }
4479
4480 kfree(attr);
4481 kfree(init_attr);
4482
4483 return 0;
4484
4485error_4:
4486 mlx5_ib_destroy_qp(qp);
4487 dev->umrc.qp = NULL;
4488
4489error_3:
4490 ib_free_cq(cq);
4491 dev->umrc.cq = NULL;
4492
4493error_2:
4494 ib_dealloc_pd(pd);
4495 dev->umrc.pd = NULL;
4496
4497error_0:
4498 kfree(attr);
4499 kfree(init_attr);
4500 return ret;
4501}
4502
4503static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4504{
4505 switch (umr_fence_cap) {
4506 case MLX5_CAP_UMR_FENCE_NONE:
4507 return MLX5_FENCE_MODE_NONE;
4508 case MLX5_CAP_UMR_FENCE_SMALL:
4509 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4510 default:
4511 return MLX5_FENCE_MODE_STRONG_ORDERING;
4512 }
4513}
4514
4515static int create_dev_resources(struct mlx5_ib_resources *devr)
4516{
4517 struct ib_srq_init_attr attr;
4518 struct mlx5_ib_dev *dev;
4519 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4520 int port;
4521 int ret = 0;
4522
4523 dev = container_of(devr, struct mlx5_ib_dev, devr);
4524
4525 mutex_init(&devr->mutex);
4526
4527 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4528 if (IS_ERR(devr->p0)) {
4529 ret = PTR_ERR(devr->p0);
4530 goto error0;
4531 }
4532 devr->p0->device = &dev->ib_dev;
4533 devr->p0->uobject = NULL;
4534 atomic_set(&devr->p0->usecnt, 0);
4535
4536 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4537 if (IS_ERR(devr->c0)) {
4538 ret = PTR_ERR(devr->c0);
4539 goto error1;
4540 }
4541 devr->c0->device = &dev->ib_dev;
4542 devr->c0->uobject = NULL;
4543 devr->c0->comp_handler = NULL;
4544 devr->c0->event_handler = NULL;
4545 devr->c0->cq_context = NULL;
4546 atomic_set(&devr->c0->usecnt, 0);
4547
4548 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4549 if (IS_ERR(devr->x0)) {
4550 ret = PTR_ERR(devr->x0);
4551 goto error2;
4552 }
4553 devr->x0->device = &dev->ib_dev;
4554 devr->x0->inode = NULL;
4555 atomic_set(&devr->x0->usecnt, 0);
4556 mutex_init(&devr->x0->tgt_qp_mutex);
4557 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4558
4559 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4560 if (IS_ERR(devr->x1)) {
4561 ret = PTR_ERR(devr->x1);
4562 goto error3;
4563 }
4564 devr->x1->device = &dev->ib_dev;
4565 devr->x1->inode = NULL;
4566 atomic_set(&devr->x1->usecnt, 0);
4567 mutex_init(&devr->x1->tgt_qp_mutex);
4568 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4569
4570 memset(&attr, 0, sizeof(attr));
4571 attr.attr.max_sge = 1;
4572 attr.attr.max_wr = 1;
4573 attr.srq_type = IB_SRQT_XRC;
4574 attr.ext.cq = devr->c0;
4575 attr.ext.xrc.xrcd = devr->x0;
4576
4577 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4578 if (IS_ERR(devr->s0)) {
4579 ret = PTR_ERR(devr->s0);
4580 goto error4;
4581 }
4582 devr->s0->device = &dev->ib_dev;
4583 devr->s0->pd = devr->p0;
4584 devr->s0->uobject = NULL;
4585 devr->s0->event_handler = NULL;
4586 devr->s0->srq_context = NULL;
4587 devr->s0->srq_type = IB_SRQT_XRC;
4588 devr->s0->ext.xrc.xrcd = devr->x0;
4589 devr->s0->ext.cq = devr->c0;
4590 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4591 atomic_inc(&devr->s0->ext.cq->usecnt);
4592 atomic_inc(&devr->p0->usecnt);
4593 atomic_set(&devr->s0->usecnt, 0);
4594
4595 memset(&attr, 0, sizeof(attr));
4596 attr.attr.max_sge = 1;
4597 attr.attr.max_wr = 1;
4598 attr.srq_type = IB_SRQT_BASIC;
4599 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4600 if (IS_ERR(devr->s1)) {
4601 ret = PTR_ERR(devr->s1);
4602 goto error5;
4603 }
4604 devr->s1->device = &dev->ib_dev;
4605 devr->s1->pd = devr->p0;
4606 devr->s1->uobject = NULL;
4607 devr->s1->event_handler = NULL;
4608 devr->s1->srq_context = NULL;
4609 devr->s1->srq_type = IB_SRQT_BASIC;
4610 devr->s1->ext.cq = devr->c0;
4611 atomic_inc(&devr->p0->usecnt);
4612 atomic_set(&devr->s1->usecnt, 0);
4613
4614 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4615 INIT_WORK(&devr->ports[port].pkey_change_work,
4616 pkey_change_handler);
4617 devr->ports[port].devr = devr;
4618 }
4619
4620 return 0;
4621
4622error5:
4623 mlx5_ib_destroy_srq(devr->s0);
4624error4:
4625 mlx5_ib_dealloc_xrcd(devr->x1);
4626error3:
4627 mlx5_ib_dealloc_xrcd(devr->x0);
4628error2:
4629 mlx5_ib_destroy_cq(devr->c0);
4630error1:
4631 mlx5_ib_dealloc_pd(devr->p0);
4632error0:
4633 return ret;
4634}
4635
4636static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4637{
4638 struct mlx5_ib_dev *dev =
4639 container_of(devr, struct mlx5_ib_dev, devr);
4640 int port;
4641
4642 mlx5_ib_destroy_srq(devr->s1);
4643 mlx5_ib_destroy_srq(devr->s0);
4644 mlx5_ib_dealloc_xrcd(devr->x0);
4645 mlx5_ib_dealloc_xrcd(devr->x1);
4646 mlx5_ib_destroy_cq(devr->c0);
4647 mlx5_ib_dealloc_pd(devr->p0);
4648
4649 /* Make sure no change P_Key work items are still executing */
4650 for (port = 0; port < dev->num_ports; ++port)
4651 cancel_work_sync(&devr->ports[port].pkey_change_work);
4652}
4653
4654static u32 get_core_cap_flags(struct ib_device *ibdev,
4655 struct mlx5_hca_vport_context *rep)
4656{
4657 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4658 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4659 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4660 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4661 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4662 u32 ret = 0;
4663
4664 if (rep->grh_required)
4665 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4666
4667 if (ll == IB_LINK_LAYER_INFINIBAND)
4668 return ret | RDMA_CORE_PORT_IBA_IB;
4669
4670 if (raw_support)
4671 ret |= RDMA_CORE_PORT_RAW_PACKET;
4672
4673 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4674 return ret;
4675
4676 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4677 return ret;
4678
4679 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4680 ret |= RDMA_CORE_PORT_IBA_ROCE;
4681
4682 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4683 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4684
4685 return ret;
4686}
4687
4688static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4689 struct ib_port_immutable *immutable)
4690{
4691 struct ib_port_attr attr;
4692 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4693 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4694 struct mlx5_hca_vport_context rep = {0};
4695 int err;
4696
4697 err = ib_query_port(ibdev, port_num, &attr);
4698 if (err)
4699 return err;
4700
4701 if (ll == IB_LINK_LAYER_INFINIBAND) {
4702 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4703 &rep);
4704 if (err)
4705 return err;
4706 }
4707
4708 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4709 immutable->gid_tbl_len = attr.gid_tbl_len;
4710 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4711 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4712 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4713
4714 return 0;
4715}
4716
4717static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4718 struct ib_port_immutable *immutable)
4719{
4720 struct ib_port_attr attr;
4721 int err;
4722
4723 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4724
4725 err = ib_query_port(ibdev, port_num, &attr);
4726 if (err)
4727 return err;
4728
4729 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4730 immutable->gid_tbl_len = attr.gid_tbl_len;
4731 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4732
4733 return 0;
4734}
4735
4736static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4737{
4738 struct mlx5_ib_dev *dev =
4739 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4740 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4741 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4742 fw_rev_sub(dev->mdev));
4743}
4744
4745static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4746{
4747 struct mlx5_core_dev *mdev = dev->mdev;
4748 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4749 MLX5_FLOW_NAMESPACE_LAG);
4750 struct mlx5_flow_table *ft;
4751 int err;
4752
4753 if (!ns || !mlx5_lag_is_active(mdev))
4754 return 0;
4755
4756 err = mlx5_cmd_create_vport_lag(mdev);
4757 if (err)
4758 return err;
4759
4760 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4761 if (IS_ERR(ft)) {
4762 err = PTR_ERR(ft);
4763 goto err_destroy_vport_lag;
4764 }
4765
4766 dev->flow_db->lag_demux_ft = ft;
4767 return 0;
4768
4769err_destroy_vport_lag:
4770 mlx5_cmd_destroy_vport_lag(mdev);
4771 return err;
4772}
4773
4774static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4775{
4776 struct mlx5_core_dev *mdev = dev->mdev;
4777
4778 if (dev->flow_db->lag_demux_ft) {
4779 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4780 dev->flow_db->lag_demux_ft = NULL;
4781
4782 mlx5_cmd_destroy_vport_lag(mdev);
4783 }
4784}
4785
4786static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4787{
4788 int err;
4789
4790 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4791 err = register_netdevice_notifier(&dev->roce[port_num].nb);
4792 if (err) {
4793 dev->roce[port_num].nb.notifier_call = NULL;
4794 return err;
4795 }
4796
4797 return 0;
4798}
4799
4800static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4801{
4802 if (dev->roce[port_num].nb.notifier_call) {
4803 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4804 dev->roce[port_num].nb.notifier_call = NULL;
4805 }
4806}
4807
4808static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4809{
4810 int err;
4811
4812 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4813 err = mlx5_nic_vport_enable_roce(dev->mdev);
4814 if (err)
4815 return err;
4816 }
4817
4818 err = mlx5_eth_lag_init(dev);
4819 if (err)
4820 goto err_disable_roce;
4821
4822 return 0;
4823
4824err_disable_roce:
4825 if (MLX5_CAP_GEN(dev->mdev, roce))
4826 mlx5_nic_vport_disable_roce(dev->mdev);
4827
4828 return err;
4829}
4830
4831static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4832{
4833 mlx5_eth_lag_cleanup(dev);
4834 if (MLX5_CAP_GEN(dev->mdev, roce))
4835 mlx5_nic_vport_disable_roce(dev->mdev);
4836}
4837
4838struct mlx5_ib_counter {
4839 const char *name;
4840 size_t offset;
4841};
4842
4843#define INIT_Q_COUNTER(_name) \
4844 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4845
4846static const struct mlx5_ib_counter basic_q_cnts[] = {
4847 INIT_Q_COUNTER(rx_write_requests),
4848 INIT_Q_COUNTER(rx_read_requests),
4849 INIT_Q_COUNTER(rx_atomic_requests),
4850 INIT_Q_COUNTER(out_of_buffer),
4851};
4852
4853static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4854 INIT_Q_COUNTER(out_of_sequence),
4855};
4856
4857static const struct mlx5_ib_counter retrans_q_cnts[] = {
4858 INIT_Q_COUNTER(duplicate_request),
4859 INIT_Q_COUNTER(rnr_nak_retry_err),
4860 INIT_Q_COUNTER(packet_seq_err),
4861 INIT_Q_COUNTER(implied_nak_seq_err),
4862 INIT_Q_COUNTER(local_ack_timeout_err),
4863};
4864
4865#define INIT_CONG_COUNTER(_name) \
4866 { .name = #_name, .offset = \
4867 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4868
4869static const struct mlx5_ib_counter cong_cnts[] = {
4870 INIT_CONG_COUNTER(rp_cnp_ignored),
4871 INIT_CONG_COUNTER(rp_cnp_handled),
4872 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4873 INIT_CONG_COUNTER(np_cnp_sent),
4874};
4875
4876static const struct mlx5_ib_counter extended_err_cnts[] = {
4877 INIT_Q_COUNTER(resp_local_length_error),
4878 INIT_Q_COUNTER(resp_cqe_error),
4879 INIT_Q_COUNTER(req_cqe_error),
4880 INIT_Q_COUNTER(req_remote_invalid_request),
4881 INIT_Q_COUNTER(req_remote_access_errors),
4882 INIT_Q_COUNTER(resp_remote_access_errors),
4883 INIT_Q_COUNTER(resp_cqe_flush_error),
4884 INIT_Q_COUNTER(req_cqe_flush_error),
4885};
4886
4887#define INIT_EXT_PPCNT_COUNTER(_name) \
4888 { .name = #_name, .offset = \
4889 MLX5_BYTE_OFF(ppcnt_reg, \
4890 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4891
4892static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4893 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4894};
4895
4896static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4897{
4898 int i;
4899
4900 for (i = 0; i < dev->num_ports; i++) {
4901 if (dev->port[i].cnts.set_id_valid)
4902 mlx5_core_dealloc_q_counter(dev->mdev,
4903 dev->port[i].cnts.set_id);
4904 kfree(dev->port[i].cnts.names);
4905 kfree(dev->port[i].cnts.offsets);
4906 }
4907}
4908
4909static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4910 struct mlx5_ib_counters *cnts)
4911{
4912 u32 num_counters;
4913
4914 num_counters = ARRAY_SIZE(basic_q_cnts);
4915
4916 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4917 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4918
4919 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4920 num_counters += ARRAY_SIZE(retrans_q_cnts);
4921
4922 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4923 num_counters += ARRAY_SIZE(extended_err_cnts);
4924
4925 cnts->num_q_counters = num_counters;
4926
4927 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4928 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4929 num_counters += ARRAY_SIZE(cong_cnts);
4930 }
4931 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4932 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4933 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4934 }
4935 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4936 if (!cnts->names)
4937 return -ENOMEM;
4938
4939 cnts->offsets = kcalloc(num_counters,
4940 sizeof(cnts->offsets), GFP_KERNEL);
4941 if (!cnts->offsets)
4942 goto err_names;
4943
4944 return 0;
4945
4946err_names:
4947 kfree(cnts->names);
4948 cnts->names = NULL;
4949 return -ENOMEM;
4950}
4951
4952static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4953 const char **names,
4954 size_t *offsets)
4955{
4956 int i;
4957 int j = 0;
4958
4959 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4960 names[j] = basic_q_cnts[i].name;
4961 offsets[j] = basic_q_cnts[i].offset;
4962 }
4963
4964 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
4965 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
4966 names[j] = out_of_seq_q_cnts[i].name;
4967 offsets[j] = out_of_seq_q_cnts[i].offset;
4968 }
4969 }
4970
4971 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
4972 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
4973 names[j] = retrans_q_cnts[i].name;
4974 offsets[j] = retrans_q_cnts[i].offset;
4975 }
4976 }
4977
4978 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
4979 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
4980 names[j] = extended_err_cnts[i].name;
4981 offsets[j] = extended_err_cnts[i].offset;
4982 }
4983 }
4984
4985 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4986 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
4987 names[j] = cong_cnts[i].name;
4988 offsets[j] = cong_cnts[i].offset;
4989 }
4990 }
4991
4992 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4993 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
4994 names[j] = ext_ppcnt_cnts[i].name;
4995 offsets[j] = ext_ppcnt_cnts[i].offset;
4996 }
4997 }
4998}
4999
5000static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5001{
5002 int err = 0;
5003 int i;
5004
5005 for (i = 0; i < dev->num_ports; i++) {
5006 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5007 if (err)
5008 goto err_alloc;
5009
5010 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5011 dev->port[i].cnts.offsets);
5012
5013 err = mlx5_core_alloc_q_counter(dev->mdev,
5014 &dev->port[i].cnts.set_id);
5015 if (err) {
5016 mlx5_ib_warn(dev,
5017 "couldn't allocate queue counter for port %d, err %d\n",
5018 i + 1, err);
5019 goto err_alloc;
5020 }
5021 dev->port[i].cnts.set_id_valid = true;
5022 }
5023
5024 return 0;
5025
5026err_alloc:
5027 mlx5_ib_dealloc_counters(dev);
5028 return err;
5029}
5030
5031static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5032 u8 port_num)
5033{
5034 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5035 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5036
5037 /* We support only per port stats */
5038 if (port_num == 0)
5039 return NULL;
5040
5041 return rdma_alloc_hw_stats_struct(port->cnts.names,
5042 port->cnts.num_q_counters +
5043 port->cnts.num_cong_counters +
5044 port->cnts.num_ext_ppcnt_counters,
5045 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5046}
5047
5048static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5049 struct mlx5_ib_port *port,
5050 struct rdma_hw_stats *stats)
5051{
5052 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5053 void *out;
5054 __be32 val;
5055 int ret, i;
5056
5057 out = kvzalloc(outlen, GFP_KERNEL);
5058 if (!out)
5059 return -ENOMEM;
5060
5061 ret = mlx5_core_query_q_counter(mdev,
5062 port->cnts.set_id, 0,
5063 out, outlen);
5064 if (ret)
5065 goto free;
5066
5067 for (i = 0; i < port->cnts.num_q_counters; i++) {
5068 val = *(__be32 *)(out + port->cnts.offsets[i]);
5069 stats->value[i] = (u64)be32_to_cpu(val);
5070 }
5071
5072free:
5073 kvfree(out);
5074 return ret;
5075}
5076
5077static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5078 struct mlx5_ib_port *port,
5079 struct rdma_hw_stats *stats)
5080{
5081 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5082 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5083 int ret, i;
5084 void *out;
5085
5086 out = kvzalloc(sz, GFP_KERNEL);
5087 if (!out)
5088 return -ENOMEM;
5089
5090 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5091 if (ret)
5092 goto free;
5093
5094 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5095 stats->value[i + offset] =
5096 be64_to_cpup((__be64 *)(out +
5097 port->cnts.offsets[i + offset]));
5098 }
5099
5100free:
5101 kvfree(out);
5102 return ret;
5103}
5104
5105static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5106 struct rdma_hw_stats *stats,
5107 u8 port_num, int index)
5108{
5109 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5110 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5111 struct mlx5_core_dev *mdev;
5112 int ret, num_counters;
5113 u8 mdev_port_num;
5114
5115 if (!stats)
5116 return -EINVAL;
5117
5118 num_counters = port->cnts.num_q_counters +
5119 port->cnts.num_cong_counters +
5120 port->cnts.num_ext_ppcnt_counters;
5121
5122 /* q_counters are per IB device, query the master mdev */
5123 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5124 if (ret)
5125 return ret;
5126
5127 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5128 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5129 if (ret)
5130 return ret;
5131 }
5132
5133 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5134 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5135 &mdev_port_num);
5136 if (!mdev) {
5137 /* If port is not affiliated yet, its in down state
5138 * which doesn't have any counters yet, so it would be
5139 * zero. So no need to read from the HCA.
5140 */
5141 goto done;
5142 }
5143 ret = mlx5_lag_query_cong_counters(dev->mdev,
5144 stats->value +
5145 port->cnts.num_q_counters,
5146 port->cnts.num_cong_counters,
5147 port->cnts.offsets +
5148 port->cnts.num_q_counters);
5149
5150 mlx5_ib_put_native_port_mdev(dev, port_num);
5151 if (ret)
5152 return ret;
5153 }
5154
5155done:
5156 return num_counters;
5157}
5158
5159static struct net_device*
5160mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5161 u8 port_num,
5162 enum rdma_netdev_t type,
5163 const char *name,
5164 unsigned char name_assign_type,
5165 void (*setup)(struct net_device *))
5166{
5167 struct net_device *netdev;
5168
5169 if (type != RDMA_NETDEV_IPOIB)
5170 return ERR_PTR(-EOPNOTSUPP);
5171
5172 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5173 name, setup);
5174 return netdev;
5175}
5176
5177static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5178{
5179 if (!dev->delay_drop.dbg)
5180 return;
5181 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5182 kfree(dev->delay_drop.dbg);
5183 dev->delay_drop.dbg = NULL;
5184}
5185
5186static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5187{
5188 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5189 return;
5190
5191 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5192 delay_drop_debugfs_cleanup(dev);
5193}
5194
5195static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5196 size_t count, loff_t *pos)
5197{
5198 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5199 char lbuf[20];
5200 int len;
5201
5202 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5203 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5204}
5205
5206static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5207 size_t count, loff_t *pos)
5208{
5209 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5210 u32 timeout;
5211 u32 var;
5212
5213 if (kstrtouint_from_user(buf, count, 0, &var))
5214 return -EFAULT;
5215
5216 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5217 1000);
5218 if (timeout != var)
5219 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5220 timeout);
5221
5222 delay_drop->timeout = timeout;
5223
5224 return count;
5225}
5226
5227static const struct file_operations fops_delay_drop_timeout = {
5228 .owner = THIS_MODULE,
5229 .open = simple_open,
5230 .write = delay_drop_timeout_write,
5231 .read = delay_drop_timeout_read,
5232};
5233
5234static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5235{
5236 struct mlx5_ib_dbg_delay_drop *dbg;
5237
5238 if (!mlx5_debugfs_root)
5239 return 0;
5240
5241 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5242 if (!dbg)
5243 return -ENOMEM;
5244
5245 dev->delay_drop.dbg = dbg;
5246
5247 dbg->dir_debugfs =
5248 debugfs_create_dir("delay_drop",
5249 dev->mdev->priv.dbg_root);
5250 if (!dbg->dir_debugfs)
5251 goto out_debugfs;
5252
5253 dbg->events_cnt_debugfs =
5254 debugfs_create_atomic_t("num_timeout_events", 0400,
5255 dbg->dir_debugfs,
5256 &dev->delay_drop.events_cnt);
5257 if (!dbg->events_cnt_debugfs)
5258 goto out_debugfs;
5259
5260 dbg->rqs_cnt_debugfs =
5261 debugfs_create_atomic_t("num_rqs", 0400,
5262 dbg->dir_debugfs,
5263 &dev->delay_drop.rqs_cnt);
5264 if (!dbg->rqs_cnt_debugfs)
5265 goto out_debugfs;
5266
5267 dbg->timeout_debugfs =
5268 debugfs_create_file("timeout", 0600,
5269 dbg->dir_debugfs,
5270 &dev->delay_drop,
5271 &fops_delay_drop_timeout);
5272 if (!dbg->timeout_debugfs)
5273 goto out_debugfs;
5274
5275 return 0;
5276
5277out_debugfs:
5278 delay_drop_debugfs_cleanup(dev);
5279 return -ENOMEM;
5280}
5281
5282static void init_delay_drop(struct mlx5_ib_dev *dev)
5283{
5284 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5285 return;
5286
5287 mutex_init(&dev->delay_drop.lock);
5288 dev->delay_drop.dev = dev;
5289 dev->delay_drop.activate = false;
5290 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5291 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5292 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5293 atomic_set(&dev->delay_drop.events_cnt, 0);
5294
5295 if (delay_drop_debugfs_init(dev))
5296 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5297}
5298
5299static const struct cpumask *
5300mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5301{
5302 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5303
5304 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5305}
5306
5307/* The mlx5_ib_multiport_mutex should be held when calling this function */
5308static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5309 struct mlx5_ib_multiport_info *mpi)
5310{
5311 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5312 struct mlx5_ib_port *port = &ibdev->port[port_num];
5313 int comps;
5314 int err;
5315 int i;
5316
5317 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5318
5319 spin_lock(&port->mp.mpi_lock);
5320 if (!mpi->ibdev) {
5321 spin_unlock(&port->mp.mpi_lock);
5322 return;
5323 }
5324 mpi->ibdev = NULL;
5325
5326 spin_unlock(&port->mp.mpi_lock);
5327 mlx5_remove_netdev_notifier(ibdev, port_num);
5328 spin_lock(&port->mp.mpi_lock);
5329
5330 comps = mpi->mdev_refcnt;
5331 if (comps) {
5332 mpi->unaffiliate = true;
5333 init_completion(&mpi->unref_comp);
5334 spin_unlock(&port->mp.mpi_lock);
5335
5336 for (i = 0; i < comps; i++)
5337 wait_for_completion(&mpi->unref_comp);
5338
5339 spin_lock(&port->mp.mpi_lock);
5340 mpi->unaffiliate = false;
5341 }
5342
5343 port->mp.mpi = NULL;
5344
5345 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5346
5347 spin_unlock(&port->mp.mpi_lock);
5348
5349 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5350
5351 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5352 /* Log an error, still needed to cleanup the pointers and add
5353 * it back to the list.
5354 */
5355 if (err)
5356 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5357 port_num + 1);
5358
5359 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5360}
5361
5362/* The mlx5_ib_multiport_mutex should be held when calling this function */
5363static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5364 struct mlx5_ib_multiport_info *mpi)
5365{
5366 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5367 int err;
5368
5369 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5370 if (ibdev->port[port_num].mp.mpi) {
5371 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5372 port_num + 1);
5373 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5374 return false;
5375 }
5376
5377 ibdev->port[port_num].mp.mpi = mpi;
5378 mpi->ibdev = ibdev;
5379 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5380
5381 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5382 if (err)
5383 goto unbind;
5384
5385 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5386 if (err)
5387 goto unbind;
5388
5389 err = mlx5_add_netdev_notifier(ibdev, port_num);
5390 if (err) {
5391 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5392 port_num + 1);
5393 goto unbind;
5394 }
5395
5396 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5397 if (err)
5398 goto unbind;
5399
5400 return true;
5401
5402unbind:
5403 mlx5_ib_unbind_slave_port(ibdev, mpi);
5404 return false;
5405}
5406
5407static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5408{
5409 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5410 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5411 port_num + 1);
5412 struct mlx5_ib_multiport_info *mpi;
5413 int err;
5414 int i;
5415
5416 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5417 return 0;
5418
5419 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5420 &dev->sys_image_guid);
5421 if (err)
5422 return err;
5423
5424 err = mlx5_nic_vport_enable_roce(dev->mdev);
5425 if (err)
5426 return err;
5427
5428 mutex_lock(&mlx5_ib_multiport_mutex);
5429 for (i = 0; i < dev->num_ports; i++) {
5430 bool bound = false;
5431
5432 /* build a stub multiport info struct for the native port. */
5433 if (i == port_num) {
5434 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5435 if (!mpi) {
5436 mutex_unlock(&mlx5_ib_multiport_mutex);
5437 mlx5_nic_vport_disable_roce(dev->mdev);
5438 return -ENOMEM;
5439 }
5440
5441 mpi->is_master = true;
5442 mpi->mdev = dev->mdev;
5443 mpi->sys_image_guid = dev->sys_image_guid;
5444 dev->port[i].mp.mpi = mpi;
5445 mpi->ibdev = dev;
5446 mpi = NULL;
5447 continue;
5448 }
5449
5450 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5451 list) {
5452 if (dev->sys_image_guid == mpi->sys_image_guid &&
5453 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5454 bound = mlx5_ib_bind_slave_port(dev, mpi);
5455 }
5456
5457 if (bound) {
5458 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5459 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5460 list_del(&mpi->list);
5461 break;
5462 }
5463 }
5464 if (!bound) {
5465 get_port_caps(dev, i + 1);
5466 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5467 i + 1);
5468 }
5469 }
5470
5471 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5472 mutex_unlock(&mlx5_ib_multiport_mutex);
5473 return err;
5474}
5475
5476static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5477{
5478 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5479 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5480 port_num + 1);
5481 int i;
5482
5483 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5484 return;
5485
5486 mutex_lock(&mlx5_ib_multiport_mutex);
5487 for (i = 0; i < dev->num_ports; i++) {
5488 if (dev->port[i].mp.mpi) {
5489 /* Destroy the native port stub */
5490 if (i == port_num) {
5491 kfree(dev->port[i].mp.mpi);
5492 dev->port[i].mp.mpi = NULL;
5493 } else {
5494 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5495 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5496 }
5497 }
5498 }
5499
5500 mlx5_ib_dbg(dev, "removing from devlist\n");
5501 list_del(&dev->ib_dev_list);
5502 mutex_unlock(&mlx5_ib_multiport_mutex);
5503
5504 mlx5_nic_vport_disable_roce(dev->mdev);
5505}
5506
5507ADD_UVERBS_ATTRIBUTES_SIMPLE(
5508 mlx5_ib_dm,
5509 UVERBS_OBJECT_DM,
5510 UVERBS_METHOD_DM_ALLOC,
5511 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5512 UVERBS_ATTR_TYPE(u64),
5513 UA_MANDATORY),
5514 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5515 UVERBS_ATTR_TYPE(u16),
5516 UA_MANDATORY));
5517
5518ADD_UVERBS_ATTRIBUTES_SIMPLE(
5519 mlx5_ib_flow_action,
5520 UVERBS_OBJECT_FLOW_ACTION,
5521 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5522 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5523 enum mlx5_ib_uapi_flow_action_flags));
5524
5525static int populate_specs_root(struct mlx5_ib_dev *dev)
5526{
5527 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5528 size_t num_trees = 0;
5529
5530 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5531 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5532 trees[num_trees++] = &mlx5_ib_flow_action;
5533
5534 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5535 trees[num_trees++] = &mlx5_ib_dm;
5536
5537 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5538 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5539 trees[num_trees++] = mlx5_ib_get_devx_tree();
5540
5541 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5542
5543 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5544 trees[num_trees] = NULL;
5545 dev->ib_dev.driver_specs = trees;
5546
5547 return 0;
5548}
5549
5550static int mlx5_ib_read_counters(struct ib_counters *counters,
5551 struct ib_counters_read_attr *read_attr,
5552 struct uverbs_attr_bundle *attrs)
5553{
5554 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5555 struct mlx5_read_counters_attr mread_attr = {};
5556 struct mlx5_ib_flow_counters_desc *desc;
5557 int ret, i;
5558
5559 mutex_lock(&mcounters->mcntrs_mutex);
5560 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5561 ret = -EINVAL;
5562 goto err_bound;
5563 }
5564
5565 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5566 GFP_KERNEL);
5567 if (!mread_attr.out) {
5568 ret = -ENOMEM;
5569 goto err_bound;
5570 }
5571
5572 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5573 mread_attr.flags = read_attr->flags;
5574 ret = mcounters->read_counters(counters->device, &mread_attr);
5575 if (ret)
5576 goto err_read;
5577
5578 /* do the pass over the counters data array to assign according to the
5579 * descriptions and indexing pairs
5580 */
5581 desc = mcounters->counters_data;
5582 for (i = 0; i < mcounters->ncounters; i++)
5583 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5584
5585err_read:
5586 kfree(mread_attr.out);
5587err_bound:
5588 mutex_unlock(&mcounters->mcntrs_mutex);
5589 return ret;
5590}
5591
5592static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5593{
5594 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5595
5596 counters_clear_description(counters);
5597 if (mcounters->hw_cntrs_hndl)
5598 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5599 mcounters->hw_cntrs_hndl);
5600
5601 kfree(mcounters);
5602
5603 return 0;
5604}
5605
5606static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5607 struct uverbs_attr_bundle *attrs)
5608{
5609 struct mlx5_ib_mcounters *mcounters;
5610
5611 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5612 if (!mcounters)
5613 return ERR_PTR(-ENOMEM);
5614
5615 mutex_init(&mcounters->mcntrs_mutex);
5616
5617 return &mcounters->ibcntrs;
5618}
5619
5620void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5621{
5622 mlx5_ib_cleanup_multiport_master(dev);
5623#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5624 cleanup_srcu_struct(&dev->mr_srcu);
5625#endif
5626 kfree(dev->port);
5627}
5628
5629int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5630{
5631 struct mlx5_core_dev *mdev = dev->mdev;
5632 const char *name;
5633 int err;
5634 int i;
5635
5636 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5637 GFP_KERNEL);
5638 if (!dev->port)
5639 return -ENOMEM;
5640
5641 for (i = 0; i < dev->num_ports; i++) {
5642 spin_lock_init(&dev->port[i].mp.mpi_lock);
5643 rwlock_init(&dev->roce[i].netdev_lock);
5644 }
5645
5646 err = mlx5_ib_init_multiport_master(dev);
5647 if (err)
5648 goto err_free_port;
5649
5650 if (!mlx5_core_mp_enabled(mdev)) {
5651 for (i = 1; i <= dev->num_ports; i++) {
5652 err = get_port_caps(dev, i);
5653 if (err)
5654 break;
5655 }
5656 } else {
5657 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5658 }
5659 if (err)
5660 goto err_mp;
5661
5662 if (mlx5_use_mad_ifc(dev))
5663 get_ext_port_caps(dev);
5664
5665 if (!mlx5_lag_is_active(mdev))
5666 name = "mlx5_%d";
5667 else
5668 name = "mlx5_bond_%d";
5669
5670 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5671 dev->ib_dev.owner = THIS_MODULE;
5672 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
5673 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
5674 dev->ib_dev.phys_port_cnt = dev->num_ports;
5675 dev->ib_dev.num_comp_vectors =
5676 dev->mdev->priv.eq_table.num_comp_vectors;
5677 dev->ib_dev.dev.parent = &mdev->pdev->dev;
5678
5679 mutex_init(&dev->cap_mask_mutex);
5680 INIT_LIST_HEAD(&dev->qp_list);
5681 spin_lock_init(&dev->reset_flow_resource_lock);
5682
5683 spin_lock_init(&dev->memic.memic_lock);
5684 dev->memic.dev = mdev;
5685
5686#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5687 err = init_srcu_struct(&dev->mr_srcu);
5688 if (err)
5689 goto err_free_port;
5690#endif
5691
5692 return 0;
5693err_mp:
5694 mlx5_ib_cleanup_multiport_master(dev);
5695
5696err_free_port:
5697 kfree(dev->port);
5698
5699 return -ENOMEM;
5700}
5701
5702static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5703{
5704 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5705
5706 if (!dev->flow_db)
5707 return -ENOMEM;
5708
5709 mutex_init(&dev->flow_db->lock);
5710
5711 return 0;
5712}
5713
5714int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5715{
5716 struct mlx5_ib_dev *nic_dev;
5717
5718 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5719
5720 if (!nic_dev)
5721 return -EINVAL;
5722
5723 dev->flow_db = nic_dev->flow_db;
5724
5725 return 0;
5726}
5727
5728static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5729{
5730 kfree(dev->flow_db);
5731}
5732
5733int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5734{
5735 struct mlx5_core_dev *mdev = dev->mdev;
5736 int err;
5737
5738 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5739 dev->ib_dev.uverbs_cmd_mask =
5740 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5741 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5742 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5743 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5744 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
5745 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5746 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
5747 (1ull << IB_USER_VERBS_CMD_REG_MR) |
5748 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
5749 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5750 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5751 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5752 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5753 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5754 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5755 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5756 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5757 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5758 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5759 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5760 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5761 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5762 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5763 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5764 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5765 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5766 dev->ib_dev.uverbs_ex_cmd_mask =
5767 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5768 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
5769 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
5770 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5771 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5772
5773 dev->ib_dev.query_device = mlx5_ib_query_device;
5774 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
5775 dev->ib_dev.query_gid = mlx5_ib_query_gid;
5776 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5777 dev->ib_dev.del_gid = mlx5_ib_del_gid;
5778 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5779 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5780 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5781 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5782 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5783 dev->ib_dev.mmap = mlx5_ib_mmap;
5784 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5785 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5786 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5787 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5788 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5789 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5790 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5791 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5792 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5793 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5794 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5795 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5796 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5797 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5798 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5799 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
5800 dev->ib_dev.post_send = mlx5_ib_post_send;
5801 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5802 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5803 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5804 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5805 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5806 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5807 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5808 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5809 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
5810 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
5811 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5812 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5813 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5814 dev->ib_dev.process_mad = mlx5_ib_process_mad;
5815 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
5816 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
5817 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
5818 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
5819 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5820 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5821 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
5822
5823 if (mlx5_core_is_pf(mdev)) {
5824 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5825 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5826 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5827 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5828 }
5829
5830 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5831
5832 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5833
5834 if (MLX5_CAP_GEN(mdev, imaicl)) {
5835 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5836 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5837 dev->ib_dev.uverbs_cmd_mask |=
5838 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5839 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5840 }
5841
5842 if (MLX5_CAP_GEN(mdev, xrc)) {
5843 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5844 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5845 dev->ib_dev.uverbs_cmd_mask |=
5846 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5847 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5848 }
5849
5850 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5851 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5852 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5853 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5854 }
5855
5856 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5857 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5858 dev->ib_dev.uverbs_ex_cmd_mask |=
5859 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5860 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5861 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5862 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5863 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5864 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5865 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5866 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5867 dev->ib_dev.read_counters = mlx5_ib_read_counters;
5868
5869 err = init_node_data(dev);
5870 if (err)
5871 return err;
5872
5873 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5874 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5875 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5876 mutex_init(&dev->lb_mutex);
5877
5878 return 0;
5879}
5880
5881static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5882{
5883 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5884 dev->ib_dev.query_port = mlx5_ib_query_port;
5885
5886 return 0;
5887}
5888
5889int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5890{
5891 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5892 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5893
5894 return 0;
5895}
5896
5897static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5898{
5899 u8 port_num;
5900 int i;
5901
5902 for (i = 0; i < dev->num_ports; i++) {
5903 dev->roce[i].dev = dev;
5904 dev->roce[i].native_port_num = i + 1;
5905 dev->roce[i].last_port_state = IB_PORT_DOWN;
5906 }
5907
5908 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5909 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5910 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5911 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5912 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5913 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5914
5915 dev->ib_dev.uverbs_ex_cmd_mask |=
5916 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5917 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5918 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5919 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5920 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5921
5922 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5923
5924 return mlx5_add_netdev_notifier(dev, port_num);
5925}
5926
5927static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5928{
5929 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5930
5931 mlx5_remove_netdev_notifier(dev, port_num);
5932}
5933
5934int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5935{
5936 struct mlx5_core_dev *mdev = dev->mdev;
5937 enum rdma_link_layer ll;
5938 int port_type_cap;
5939 int err = 0;
5940
5941 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5942 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5943
5944 if (ll == IB_LINK_LAYER_ETHERNET)
5945 err = mlx5_ib_stage_common_roce_init(dev);
5946
5947 return err;
5948}
5949
5950void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5951{
5952 mlx5_ib_stage_common_roce_cleanup(dev);
5953}
5954
5955static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5956{
5957 struct mlx5_core_dev *mdev = dev->mdev;
5958 enum rdma_link_layer ll;
5959 int port_type_cap;
5960 int err;
5961
5962 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5963 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5964
5965 if (ll == IB_LINK_LAYER_ETHERNET) {
5966 err = mlx5_ib_stage_common_roce_init(dev);
5967 if (err)
5968 return err;
5969
5970 err = mlx5_enable_eth(dev);
5971 if (err)
5972 goto cleanup;
5973 }
5974
5975 return 0;
5976cleanup:
5977 mlx5_ib_stage_common_roce_cleanup(dev);
5978
5979 return err;
5980}
5981
5982static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
5983{
5984 struct mlx5_core_dev *mdev = dev->mdev;
5985 enum rdma_link_layer ll;
5986 int port_type_cap;
5987
5988 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5989 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5990
5991 if (ll == IB_LINK_LAYER_ETHERNET) {
5992 mlx5_disable_eth(dev);
5993 mlx5_ib_stage_common_roce_cleanup(dev);
5994 }
5995}
5996
5997int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
5998{
5999 return create_dev_resources(&dev->devr);
6000}
6001
6002void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6003{
6004 destroy_dev_resources(&dev->devr);
6005}
6006
6007static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6008{
6009 mlx5_ib_internal_fill_odp_caps(dev);
6010
6011 return mlx5_ib_odp_init_one(dev);
6012}
6013
6014int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6015{
6016 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6017 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6018 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6019
6020 return mlx5_ib_alloc_counters(dev);
6021 }
6022
6023 return 0;
6024}
6025
6026void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6027{
6028 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6029 mlx5_ib_dealloc_counters(dev);
6030}
6031
6032static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6033{
6034 return mlx5_ib_init_cong_debugfs(dev,
6035 mlx5_core_native_port_num(dev->mdev) - 1);
6036}
6037
6038static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6039{
6040 mlx5_ib_cleanup_cong_debugfs(dev,
6041 mlx5_core_native_port_num(dev->mdev) - 1);
6042}
6043
6044static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6045{
6046 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6047 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6048}
6049
6050static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6051{
6052 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6053}
6054
6055int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6056{
6057 int err;
6058
6059 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6060 if (err)
6061 return err;
6062
6063 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6064 if (err)
6065 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6066
6067 return err;
6068}
6069
6070void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6071{
6072 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6073 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6074}
6075
6076static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6077{
6078 return populate_specs_root(dev);
6079}
6080
6081int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6082{
6083 return ib_register_device(&dev->ib_dev, NULL);
6084}
6085
6086void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6087{
6088 destroy_umrc_res(dev);
6089}
6090
6091void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6092{
6093 ib_unregister_device(&dev->ib_dev);
6094}
6095
6096int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6097{
6098 return create_umr_res(dev);
6099}
6100
6101static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6102{
6103 init_delay_drop(dev);
6104
6105 return 0;
6106}
6107
6108static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6109{
6110 cancel_delay_drop(dev);
6111}
6112
6113int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
6114{
6115 int err;
6116 int i;
6117
6118 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
6119 err = device_create_file(&dev->ib_dev.dev,
6120 mlx5_class_attributes[i]);
6121 if (err)
6122 return err;
6123 }
6124
6125 return 0;
6126}
6127
6128static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6129{
6130 mlx5_ib_register_vport_reps(dev);
6131
6132 return 0;
6133}
6134
6135static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6136{
6137 mlx5_ib_unregister_vport_reps(dev);
6138}
6139
6140void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6141 const struct mlx5_ib_profile *profile,
6142 int stage)
6143{
6144 /* Number of stages to cleanup */
6145 while (stage) {
6146 stage--;
6147 if (profile->stage[stage].cleanup)
6148 profile->stage[stage].cleanup(dev);
6149 }
6150
6151 ib_dealloc_device((struct ib_device *)dev);
6152}
6153
6154void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6155 const struct mlx5_ib_profile *profile)
6156{
6157 int err;
6158 int i;
6159
6160 printk_once(KERN_INFO "%s", mlx5_version);
6161
6162 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6163 if (profile->stage[i].init) {
6164 err = profile->stage[i].init(dev);
6165 if (err)
6166 goto err_out;
6167 }
6168 }
6169
6170 dev->profile = profile;
6171 dev->ib_active = true;
6172
6173 return dev;
6174
6175err_out:
6176 __mlx5_ib_remove(dev, profile, i);
6177
6178 return NULL;
6179}
6180
6181static const struct mlx5_ib_profile pf_profile = {
6182 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6183 mlx5_ib_stage_init_init,
6184 mlx5_ib_stage_init_cleanup),
6185 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6186 mlx5_ib_stage_flow_db_init,
6187 mlx5_ib_stage_flow_db_cleanup),
6188 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6189 mlx5_ib_stage_caps_init,
6190 NULL),
6191 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6192 mlx5_ib_stage_non_default_cb,
6193 NULL),
6194 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6195 mlx5_ib_stage_roce_init,
6196 mlx5_ib_stage_roce_cleanup),
6197 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6198 mlx5_ib_stage_dev_res_init,
6199 mlx5_ib_stage_dev_res_cleanup),
6200 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6201 mlx5_ib_stage_odp_init,
6202 NULL),
6203 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6204 mlx5_ib_stage_counters_init,
6205 mlx5_ib_stage_counters_cleanup),
6206 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6207 mlx5_ib_stage_cong_debugfs_init,
6208 mlx5_ib_stage_cong_debugfs_cleanup),
6209 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6210 mlx5_ib_stage_uar_init,
6211 mlx5_ib_stage_uar_cleanup),
6212 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6213 mlx5_ib_stage_bfrag_init,
6214 mlx5_ib_stage_bfrag_cleanup),
6215 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6216 NULL,
6217 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6218 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6219 mlx5_ib_stage_populate_specs,
6220 NULL),
6221 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6222 mlx5_ib_stage_ib_reg_init,
6223 mlx5_ib_stage_ib_reg_cleanup),
6224 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6225 mlx5_ib_stage_post_ib_reg_umr_init,
6226 NULL),
6227 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6228 mlx5_ib_stage_delay_drop_init,
6229 mlx5_ib_stage_delay_drop_cleanup),
6230 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6231 mlx5_ib_stage_class_attr_init,
6232 NULL),
6233};
6234
6235static const struct mlx5_ib_profile nic_rep_profile = {
6236 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6237 mlx5_ib_stage_init_init,
6238 mlx5_ib_stage_init_cleanup),
6239 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6240 mlx5_ib_stage_flow_db_init,
6241 mlx5_ib_stage_flow_db_cleanup),
6242 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6243 mlx5_ib_stage_caps_init,
6244 NULL),
6245 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6246 mlx5_ib_stage_rep_non_default_cb,
6247 NULL),
6248 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6249 mlx5_ib_stage_rep_roce_init,
6250 mlx5_ib_stage_rep_roce_cleanup),
6251 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6252 mlx5_ib_stage_dev_res_init,
6253 mlx5_ib_stage_dev_res_cleanup),
6254 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6255 mlx5_ib_stage_counters_init,
6256 mlx5_ib_stage_counters_cleanup),
6257 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6258 mlx5_ib_stage_uar_init,
6259 mlx5_ib_stage_uar_cleanup),
6260 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6261 mlx5_ib_stage_bfrag_init,
6262 mlx5_ib_stage_bfrag_cleanup),
6263 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6264 NULL,
6265 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6266 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6267 mlx5_ib_stage_populate_specs,
6268 NULL),
6269 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6270 mlx5_ib_stage_ib_reg_init,
6271 mlx5_ib_stage_ib_reg_cleanup),
6272 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6273 mlx5_ib_stage_post_ib_reg_umr_init,
6274 NULL),
6275 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6276 mlx5_ib_stage_class_attr_init,
6277 NULL),
6278 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6279 mlx5_ib_stage_rep_reg_init,
6280 mlx5_ib_stage_rep_reg_cleanup),
6281};
6282
6283static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6284{
6285 struct mlx5_ib_multiport_info *mpi;
6286 struct mlx5_ib_dev *dev;
6287 bool bound = false;
6288 int err;
6289
6290 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6291 if (!mpi)
6292 return NULL;
6293
6294 mpi->mdev = mdev;
6295
6296 err = mlx5_query_nic_vport_system_image_guid(mdev,
6297 &mpi->sys_image_guid);
6298 if (err) {
6299 kfree(mpi);
6300 return NULL;
6301 }
6302
6303 mutex_lock(&mlx5_ib_multiport_mutex);
6304 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6305 if (dev->sys_image_guid == mpi->sys_image_guid)
6306 bound = mlx5_ib_bind_slave_port(dev, mpi);
6307
6308 if (bound) {
6309 rdma_roce_rescan_device(&dev->ib_dev);
6310 break;
6311 }
6312 }
6313
6314 if (!bound) {
6315 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6316 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6317 }
6318 mutex_unlock(&mlx5_ib_multiport_mutex);
6319
6320 return mpi;
6321}
6322
6323static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6324{
6325 enum rdma_link_layer ll;
6326 struct mlx5_ib_dev *dev;
6327 int port_type_cap;
6328
6329 printk_once(KERN_INFO "%s", mlx5_version);
6330
6331 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6332 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6333
6334 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6335 return mlx5_ib_add_slave_port(mdev);
6336
6337 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6338 if (!dev)
6339 return NULL;
6340
6341 dev->mdev = mdev;
6342 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6343 MLX5_CAP_GEN(mdev, num_vhca_ports));
6344
6345 if (MLX5_ESWITCH_MANAGER(mdev) &&
6346 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6347 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6348
6349 return __mlx5_ib_add(dev, &nic_rep_profile);
6350 }
6351
6352 return __mlx5_ib_add(dev, &pf_profile);
6353}
6354
6355static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6356{
6357 struct mlx5_ib_multiport_info *mpi;
6358 struct mlx5_ib_dev *dev;
6359
6360 if (mlx5_core_is_mp_slave(mdev)) {
6361 mpi = context;
6362 mutex_lock(&mlx5_ib_multiport_mutex);
6363 if (mpi->ibdev)
6364 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6365 list_del(&mpi->list);
6366 mutex_unlock(&mlx5_ib_multiport_mutex);
6367 return;
6368 }
6369
6370 dev = context;
6371 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6372}
6373
6374static struct mlx5_interface mlx5_ib_interface = {
6375 .add = mlx5_ib_add,
6376 .remove = mlx5_ib_remove,
6377 .event = mlx5_ib_event,
6378#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6379 .pfault = mlx5_ib_pfault,
6380#endif
6381 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6382};
6383
6384unsigned long mlx5_ib_get_xlt_emergency_page(void)
6385{
6386 mutex_lock(&xlt_emergency_page_mutex);
6387 return xlt_emergency_page;
6388}
6389
6390void mlx5_ib_put_xlt_emergency_page(void)
6391{
6392 mutex_unlock(&xlt_emergency_page_mutex);
6393}
6394
6395static int __init mlx5_ib_init(void)
6396{
6397 int err;
6398
6399 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6400 if (!xlt_emergency_page)
6401 return -ENOMEM;
6402
6403 mutex_init(&xlt_emergency_page_mutex);
6404
6405 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6406 if (!mlx5_ib_event_wq) {
6407 free_page(xlt_emergency_page);
6408 return -ENOMEM;
6409 }
6410
6411 mlx5_ib_odp_init();
6412
6413 err = mlx5_register_interface(&mlx5_ib_interface);
6414
6415 return err;
6416}
6417
6418static void __exit mlx5_ib_cleanup(void)
6419{
6420 mlx5_unregister_interface(&mlx5_ib_interface);
6421 destroy_workqueue(mlx5_ib_event_wq);
6422 mutex_destroy(&xlt_emergency_page_mutex);
6423 free_page(xlt_emergency_page);
6424}
6425
6426module_init(mlx5_ib_init);
6427module_exit(mlx5_ib_cleanup);