Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * i.MX IPUv3 Graphics driver |
| 3 | * |
| 4 | * Copyright (C) 2011 Sascha Hauer, Pengutronix |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | #include <linux/component.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/export.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <drm/drmP.h> |
| 21 | #include <drm/drm_atomic.h> |
| 22 | #include <drm/drm_atomic_helper.h> |
| 23 | #include <drm/drm_crtc_helper.h> |
| 24 | #include <linux/clk.h> |
| 25 | #include <linux/errno.h> |
| 26 | #include <drm/drm_gem_cma_helper.h> |
| 27 | #include <drm/drm_fb_cma_helper.h> |
| 28 | |
| 29 | #include <video/imx-ipu-v3.h> |
| 30 | #include "imx-drm.h" |
| 31 | #include "ipuv3-plane.h" |
| 32 | |
| 33 | #define DRIVER_DESC "i.MX IPUv3 Graphics" |
| 34 | |
| 35 | struct ipu_crtc { |
| 36 | struct device *dev; |
| 37 | struct drm_crtc base; |
| 38 | |
| 39 | /* plane[0] is the full plane, plane[1] is the partial plane */ |
| 40 | struct ipu_plane *plane[2]; |
| 41 | |
| 42 | struct ipu_dc *dc; |
| 43 | struct ipu_di *di; |
| 44 | int irq; |
| 45 | }; |
| 46 | |
| 47 | static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc) |
| 48 | { |
| 49 | return container_of(crtc, struct ipu_crtc, base); |
| 50 | } |
| 51 | |
| 52 | static void ipu_crtc_atomic_enable(struct drm_crtc *crtc, |
| 53 | struct drm_crtc_state *old_state) |
| 54 | { |
| 55 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 56 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
| 57 | |
| 58 | ipu_prg_enable(ipu); |
| 59 | ipu_dc_enable(ipu); |
| 60 | ipu_dc_enable_channel(ipu_crtc->dc); |
| 61 | ipu_di_enable(ipu_crtc->di); |
| 62 | } |
| 63 | |
| 64 | static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc, |
| 65 | struct drm_crtc_state *old_crtc_state) |
| 66 | { |
| 67 | bool disable_partial = false; |
| 68 | bool disable_full = false; |
| 69 | struct drm_plane *plane; |
| 70 | |
| 71 | drm_atomic_crtc_state_for_each_plane(plane, old_crtc_state) { |
| 72 | if (plane == &ipu_crtc->plane[0]->base) |
| 73 | disable_full = true; |
| 74 | if (&ipu_crtc->plane[1] && plane == &ipu_crtc->plane[1]->base) |
| 75 | disable_partial = true; |
| 76 | } |
| 77 | |
| 78 | if (disable_partial) |
| 79 | ipu_plane_disable(ipu_crtc->plane[1], true); |
| 80 | if (disable_full) |
| 81 | ipu_plane_disable(ipu_crtc->plane[0], false); |
| 82 | } |
| 83 | |
| 84 | static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, |
| 85 | struct drm_crtc_state *old_crtc_state) |
| 86 | { |
| 87 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 88 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
| 89 | |
| 90 | ipu_dc_disable_channel(ipu_crtc->dc); |
| 91 | ipu_di_disable(ipu_crtc->di); |
| 92 | /* |
| 93 | * Planes must be disabled before DC clock is removed, as otherwise the |
| 94 | * attached IDMACs will be left in undefined state, possibly hanging |
| 95 | * the IPU or even system. |
| 96 | */ |
| 97 | ipu_crtc_disable_planes(ipu_crtc, old_crtc_state); |
| 98 | ipu_dc_disable(ipu); |
| 99 | ipu_prg_disable(ipu); |
| 100 | |
| 101 | spin_lock_irq(&crtc->dev->event_lock); |
| 102 | if (crtc->state->event) { |
| 103 | drm_crtc_send_vblank_event(crtc, crtc->state->event); |
| 104 | crtc->state->event = NULL; |
| 105 | } |
| 106 | spin_unlock_irq(&crtc->dev->event_lock); |
| 107 | |
| 108 | drm_crtc_vblank_off(crtc); |
| 109 | } |
| 110 | |
| 111 | static void imx_drm_crtc_reset(struct drm_crtc *crtc) |
| 112 | { |
| 113 | struct imx_crtc_state *state; |
| 114 | |
| 115 | if (crtc->state) { |
| 116 | if (crtc->state->mode_blob) |
| 117 | drm_property_blob_put(crtc->state->mode_blob); |
| 118 | |
| 119 | state = to_imx_crtc_state(crtc->state); |
| 120 | memset(state, 0, sizeof(*state)); |
| 121 | } else { |
| 122 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 123 | if (!state) |
| 124 | return; |
| 125 | crtc->state = &state->base; |
| 126 | } |
| 127 | |
| 128 | state->base.crtc = crtc; |
| 129 | } |
| 130 | |
| 131 | static struct drm_crtc_state *imx_drm_crtc_duplicate_state(struct drm_crtc *crtc) |
| 132 | { |
| 133 | struct imx_crtc_state *state; |
| 134 | |
| 135 | state = kzalloc(sizeof(*state), GFP_KERNEL); |
| 136 | if (!state) |
| 137 | return NULL; |
| 138 | |
| 139 | __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); |
| 140 | |
| 141 | WARN_ON(state->base.crtc != crtc); |
| 142 | state->base.crtc = crtc; |
| 143 | |
| 144 | return &state->base; |
| 145 | } |
| 146 | |
| 147 | static void imx_drm_crtc_destroy_state(struct drm_crtc *crtc, |
| 148 | struct drm_crtc_state *state) |
| 149 | { |
| 150 | __drm_atomic_helper_crtc_destroy_state(state); |
| 151 | kfree(to_imx_crtc_state(state)); |
| 152 | } |
| 153 | |
| 154 | static int ipu_enable_vblank(struct drm_crtc *crtc) |
| 155 | { |
| 156 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 157 | |
| 158 | enable_irq(ipu_crtc->irq); |
| 159 | |
| 160 | return 0; |
| 161 | } |
| 162 | |
| 163 | static void ipu_disable_vblank(struct drm_crtc *crtc) |
| 164 | { |
| 165 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 166 | |
| 167 | disable_irq_nosync(ipu_crtc->irq); |
| 168 | } |
| 169 | |
| 170 | static const struct drm_crtc_funcs ipu_crtc_funcs = { |
| 171 | .set_config = drm_atomic_helper_set_config, |
| 172 | .destroy = drm_crtc_cleanup, |
| 173 | .page_flip = drm_atomic_helper_page_flip, |
| 174 | .reset = imx_drm_crtc_reset, |
| 175 | .atomic_duplicate_state = imx_drm_crtc_duplicate_state, |
| 176 | .atomic_destroy_state = imx_drm_crtc_destroy_state, |
| 177 | .enable_vblank = ipu_enable_vblank, |
| 178 | .disable_vblank = ipu_disable_vblank, |
| 179 | }; |
| 180 | |
| 181 | static irqreturn_t ipu_irq_handler(int irq, void *dev_id) |
| 182 | { |
| 183 | struct ipu_crtc *ipu_crtc = dev_id; |
| 184 | |
| 185 | drm_crtc_handle_vblank(&ipu_crtc->base); |
| 186 | |
| 187 | return IRQ_HANDLED; |
| 188 | } |
| 189 | |
| 190 | static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, |
| 191 | const struct drm_display_mode *mode, |
| 192 | struct drm_display_mode *adjusted_mode) |
| 193 | { |
| 194 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 195 | struct videomode vm; |
| 196 | int ret; |
| 197 | |
| 198 | drm_display_mode_to_videomode(adjusted_mode, &vm); |
| 199 | |
| 200 | ret = ipu_di_adjust_videomode(ipu_crtc->di, &vm); |
| 201 | if (ret) |
| 202 | return false; |
| 203 | |
| 204 | if ((vm.vsync_len == 0) || (vm.hsync_len == 0)) |
| 205 | return false; |
| 206 | |
| 207 | drm_display_mode_from_videomode(&vm, adjusted_mode); |
| 208 | |
| 209 | return true; |
| 210 | } |
| 211 | |
| 212 | static int ipu_crtc_atomic_check(struct drm_crtc *crtc, |
| 213 | struct drm_crtc_state *state) |
| 214 | { |
| 215 | u32 primary_plane_mask = drm_plane_mask(crtc->primary); |
| 216 | |
| 217 | if (state->active && (primary_plane_mask & state->plane_mask) == 0) |
| 218 | return -EINVAL; |
| 219 | |
| 220 | return 0; |
| 221 | } |
| 222 | |
| 223 | static void ipu_crtc_atomic_begin(struct drm_crtc *crtc, |
| 224 | struct drm_crtc_state *old_crtc_state) |
| 225 | { |
| 226 | drm_crtc_vblank_on(crtc); |
| 227 | } |
| 228 | |
| 229 | static void ipu_crtc_atomic_flush(struct drm_crtc *crtc, |
| 230 | struct drm_crtc_state *old_crtc_state) |
| 231 | { |
| 232 | spin_lock_irq(&crtc->dev->event_lock); |
| 233 | if (crtc->state->event) { |
| 234 | WARN_ON(drm_crtc_vblank_get(crtc)); |
| 235 | drm_crtc_arm_vblank_event(crtc, crtc->state->event); |
| 236 | crtc->state->event = NULL; |
| 237 | } |
| 238 | spin_unlock_irq(&crtc->dev->event_lock); |
| 239 | } |
| 240 | |
| 241 | static void ipu_crtc_mode_set_nofb(struct drm_crtc *crtc) |
| 242 | { |
| 243 | struct drm_device *dev = crtc->dev; |
| 244 | struct drm_encoder *encoder; |
| 245 | struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); |
| 246 | struct drm_display_mode *mode = &crtc->state->adjusted_mode; |
| 247 | struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc->state); |
| 248 | struct ipu_di_signal_cfg sig_cfg = {}; |
| 249 | unsigned long encoder_types = 0; |
| 250 | |
| 251 | dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__, |
| 252 | mode->hdisplay); |
| 253 | dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__, |
| 254 | mode->vdisplay); |
| 255 | |
| 256 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 257 | if (encoder->crtc == crtc) |
| 258 | encoder_types |= BIT(encoder->encoder_type); |
| 259 | } |
| 260 | |
| 261 | dev_dbg(ipu_crtc->dev, "%s: attached to encoder types 0x%lx\n", |
| 262 | __func__, encoder_types); |
| 263 | |
| 264 | /* |
| 265 | * If we have DAC or LDB, then we need the IPU DI clock to be |
| 266 | * the same as the LDB DI clock. For TVDAC, derive the IPU DI |
| 267 | * clock from 27 MHz TVE_DI clock, but allow to divide it. |
| 268 | */ |
| 269 | if (encoder_types & (BIT(DRM_MODE_ENCODER_DAC) | |
| 270 | BIT(DRM_MODE_ENCODER_LVDS))) |
| 271 | sig_cfg.clkflags = IPU_DI_CLKMODE_SYNC | IPU_DI_CLKMODE_EXT; |
| 272 | else if (encoder_types & BIT(DRM_MODE_ENCODER_TVDAC)) |
| 273 | sig_cfg.clkflags = IPU_DI_CLKMODE_EXT; |
| 274 | else |
| 275 | sig_cfg.clkflags = 0; |
| 276 | |
| 277 | sig_cfg.enable_pol = !(imx_crtc_state->bus_flags & DRM_BUS_FLAG_DE_LOW); |
| 278 | /* Default to driving pixel data on negative clock edges */ |
| 279 | sig_cfg.clk_pol = !!(imx_crtc_state->bus_flags & |
| 280 | DRM_BUS_FLAG_PIXDATA_POSEDGE); |
| 281 | sig_cfg.bus_format = imx_crtc_state->bus_format; |
| 282 | sig_cfg.v_to_h_sync = 0; |
| 283 | sig_cfg.hsync_pin = imx_crtc_state->di_hsync_pin; |
| 284 | sig_cfg.vsync_pin = imx_crtc_state->di_vsync_pin; |
| 285 | |
| 286 | drm_display_mode_to_videomode(mode, &sig_cfg.mode); |
| 287 | |
| 288 | ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, |
| 289 | mode->flags & DRM_MODE_FLAG_INTERLACE, |
| 290 | imx_crtc_state->bus_format, mode->hdisplay); |
| 291 | ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg); |
| 292 | } |
| 293 | |
| 294 | static const struct drm_crtc_helper_funcs ipu_helper_funcs = { |
| 295 | .mode_fixup = ipu_crtc_mode_fixup, |
| 296 | .mode_set_nofb = ipu_crtc_mode_set_nofb, |
| 297 | .atomic_check = ipu_crtc_atomic_check, |
| 298 | .atomic_begin = ipu_crtc_atomic_begin, |
| 299 | .atomic_flush = ipu_crtc_atomic_flush, |
| 300 | .atomic_disable = ipu_crtc_atomic_disable, |
| 301 | .atomic_enable = ipu_crtc_atomic_enable, |
| 302 | }; |
| 303 | |
| 304 | static void ipu_put_resources(struct ipu_crtc *ipu_crtc) |
| 305 | { |
| 306 | if (!IS_ERR_OR_NULL(ipu_crtc->dc)) |
| 307 | ipu_dc_put(ipu_crtc->dc); |
| 308 | if (!IS_ERR_OR_NULL(ipu_crtc->di)) |
| 309 | ipu_di_put(ipu_crtc->di); |
| 310 | } |
| 311 | |
| 312 | static int ipu_get_resources(struct ipu_crtc *ipu_crtc, |
| 313 | struct ipu_client_platformdata *pdata) |
| 314 | { |
| 315 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
| 316 | int ret; |
| 317 | |
| 318 | ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc); |
| 319 | if (IS_ERR(ipu_crtc->dc)) { |
| 320 | ret = PTR_ERR(ipu_crtc->dc); |
| 321 | goto err_out; |
| 322 | } |
| 323 | |
| 324 | ipu_crtc->di = ipu_di_get(ipu, pdata->di); |
| 325 | if (IS_ERR(ipu_crtc->di)) { |
| 326 | ret = PTR_ERR(ipu_crtc->di); |
| 327 | goto err_out; |
| 328 | } |
| 329 | |
| 330 | return 0; |
| 331 | err_out: |
| 332 | ipu_put_resources(ipu_crtc); |
| 333 | |
| 334 | return ret; |
| 335 | } |
| 336 | |
| 337 | static int ipu_crtc_init(struct ipu_crtc *ipu_crtc, |
| 338 | struct ipu_client_platformdata *pdata, struct drm_device *drm) |
| 339 | { |
| 340 | struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); |
| 341 | struct drm_crtc *crtc = &ipu_crtc->base; |
| 342 | int dp = -EINVAL; |
| 343 | int ret; |
| 344 | |
| 345 | ret = ipu_get_resources(ipu_crtc, pdata); |
| 346 | if (ret) { |
| 347 | dev_err(ipu_crtc->dev, "getting resources failed with %d.\n", |
| 348 | ret); |
| 349 | return ret; |
| 350 | } |
| 351 | |
| 352 | if (pdata->dp >= 0) |
| 353 | dp = IPU_DP_FLOW_SYNC_BG; |
| 354 | ipu_crtc->plane[0] = ipu_plane_init(drm, ipu, pdata->dma[0], dp, 0, |
| 355 | DRM_PLANE_TYPE_PRIMARY); |
| 356 | if (IS_ERR(ipu_crtc->plane[0])) { |
| 357 | ret = PTR_ERR(ipu_crtc->plane[0]); |
| 358 | goto err_put_resources; |
| 359 | } |
| 360 | |
| 361 | crtc->port = pdata->of_node; |
| 362 | drm_crtc_helper_add(crtc, &ipu_helper_funcs); |
| 363 | drm_crtc_init_with_planes(drm, crtc, &ipu_crtc->plane[0]->base, NULL, |
| 364 | &ipu_crtc_funcs, NULL); |
| 365 | |
| 366 | ret = ipu_plane_get_resources(ipu_crtc->plane[0]); |
| 367 | if (ret) { |
| 368 | dev_err(ipu_crtc->dev, "getting plane 0 resources failed with %d.\n", |
| 369 | ret); |
| 370 | goto err_put_resources; |
| 371 | } |
| 372 | |
| 373 | /* If this crtc is using the DP, add an overlay plane */ |
| 374 | if (pdata->dp >= 0 && pdata->dma[1] > 0) { |
| 375 | ipu_crtc->plane[1] = ipu_plane_init(drm, ipu, pdata->dma[1], |
| 376 | IPU_DP_FLOW_SYNC_FG, |
| 377 | drm_crtc_mask(&ipu_crtc->base), |
| 378 | DRM_PLANE_TYPE_OVERLAY); |
| 379 | if (IS_ERR(ipu_crtc->plane[1])) { |
| 380 | ipu_crtc->plane[1] = NULL; |
| 381 | } else { |
| 382 | ret = ipu_plane_get_resources(ipu_crtc->plane[1]); |
| 383 | if (ret) { |
| 384 | dev_err(ipu_crtc->dev, "getting plane 1 " |
| 385 | "resources failed with %d.\n", ret); |
| 386 | goto err_put_plane0_res; |
| 387 | } |
| 388 | } |
| 389 | } |
| 390 | |
| 391 | ipu_crtc->irq = ipu_plane_irq(ipu_crtc->plane[0]); |
| 392 | ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0, |
| 393 | "imx_drm", ipu_crtc); |
| 394 | if (ret < 0) { |
| 395 | dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret); |
| 396 | goto err_put_plane1_res; |
| 397 | } |
| 398 | /* Only enable IRQ when we actually need it to trigger work. */ |
| 399 | disable_irq(ipu_crtc->irq); |
| 400 | |
| 401 | return 0; |
| 402 | |
| 403 | err_put_plane1_res: |
| 404 | if (ipu_crtc->plane[1]) |
| 405 | ipu_plane_put_resources(ipu_crtc->plane[1]); |
| 406 | err_put_plane0_res: |
| 407 | ipu_plane_put_resources(ipu_crtc->plane[0]); |
| 408 | err_put_resources: |
| 409 | ipu_put_resources(ipu_crtc); |
| 410 | |
| 411 | return ret; |
| 412 | } |
| 413 | |
| 414 | static int ipu_drm_bind(struct device *dev, struct device *master, void *data) |
| 415 | { |
| 416 | struct ipu_client_platformdata *pdata = dev->platform_data; |
| 417 | struct drm_device *drm = data; |
| 418 | struct ipu_crtc *ipu_crtc; |
| 419 | int ret; |
| 420 | |
| 421 | ipu_crtc = devm_kzalloc(dev, sizeof(*ipu_crtc), GFP_KERNEL); |
| 422 | if (!ipu_crtc) |
| 423 | return -ENOMEM; |
| 424 | |
| 425 | ipu_crtc->dev = dev; |
| 426 | |
| 427 | ret = ipu_crtc_init(ipu_crtc, pdata, drm); |
| 428 | if (ret) |
| 429 | return ret; |
| 430 | |
| 431 | dev_set_drvdata(dev, ipu_crtc); |
| 432 | |
| 433 | return 0; |
| 434 | } |
| 435 | |
| 436 | static void ipu_drm_unbind(struct device *dev, struct device *master, |
| 437 | void *data) |
| 438 | { |
| 439 | struct ipu_crtc *ipu_crtc = dev_get_drvdata(dev); |
| 440 | |
| 441 | ipu_put_resources(ipu_crtc); |
| 442 | if (ipu_crtc->plane[1]) |
| 443 | ipu_plane_put_resources(ipu_crtc->plane[1]); |
| 444 | ipu_plane_put_resources(ipu_crtc->plane[0]); |
| 445 | } |
| 446 | |
| 447 | static const struct component_ops ipu_crtc_ops = { |
| 448 | .bind = ipu_drm_bind, |
| 449 | .unbind = ipu_drm_unbind, |
| 450 | }; |
| 451 | |
| 452 | static int ipu_drm_probe(struct platform_device *pdev) |
| 453 | { |
| 454 | struct device *dev = &pdev->dev; |
| 455 | int ret; |
| 456 | |
| 457 | if (!dev->platform_data) |
| 458 | return -EINVAL; |
| 459 | |
| 460 | ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); |
| 461 | if (ret) |
| 462 | return ret; |
| 463 | |
| 464 | return component_add(dev, &ipu_crtc_ops); |
| 465 | } |
| 466 | |
| 467 | static int ipu_drm_remove(struct platform_device *pdev) |
| 468 | { |
| 469 | component_del(&pdev->dev, &ipu_crtc_ops); |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | struct platform_driver ipu_drm_driver = { |
| 474 | .driver = { |
| 475 | .name = "imx-ipuv3-crtc", |
| 476 | }, |
| 477 | .probe = ipu_drm_probe, |
| 478 | .remove = ipu_drm_remove, |
| 479 | }; |