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review.trustedfirmware.org / hafnium / third_party / linux.git / b4b6d4a02fa8aa8187d426b508fb7f3b69df0dcc / . / arch / arm / boot / dts / am335x-evm.dts
blob: c87d01297a013b60b8752594b13b89392ce95e7a [file] [log] [blame]
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame^]1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "am33xx.dtsi"
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 model = "TI AM335x EVM";
15 compatible = "ti,am335x-evm", "ti,am33xx";
16
17 cpus {
18 cpu@0 {
19 cpu0-supply = <&vdd1_reg>;
20 };
21 };
22
23 memory@80000000 {
24 device_type = "memory";
25 reg = <0x80000000 0x10000000>; /* 256 MB */
26 };
27
28 chosen {
29 stdout-path = &uart0;
30 };
31
32 vbat: fixedregulator0 {
33 compatible = "regulator-fixed";
34 regulator-name = "vbat";
35 regulator-min-microvolt = <5000000>;
36 regulator-max-microvolt = <5000000>;
37 regulator-boot-on;
38 };
39
40 lis3_reg: fixedregulator1 {
41 compatible = "regulator-fixed";
42 regulator-name = "lis3_reg";
43 regulator-boot-on;
44 };
45
46 wlan_en_reg: fixedregulator2 {
47 compatible = "regulator-fixed";
48 regulator-name = "wlan-en-regulator";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51
52 /* WLAN_EN GPIO for this board - Bank1, pin16 */
53 gpio = <&gpio1 16 0>;
54
55 /* WLAN card specific delay */
56 startup-delay-us = <70000>;
57 enable-active-high;
58 };
59
60 matrix_keypad: matrix_keypad0 {
61 compatible = "gpio-matrix-keypad";
62 debounce-delay-ms = <5>;
63 col-scan-delay-us = <2>;
64
65 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
66 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
67 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
68
69 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
70 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
71
72 linux,keymap = <0x0000008b /* MENU */
73 0x0100009e /* BACK */
74 0x02000069 /* LEFT */
75 0x0001006a /* RIGHT */
76 0x0101001c /* ENTER */
77 0x0201006c>; /* DOWN */
78 };
79
80 gpio_keys: volume_keys0 {
81 compatible = "gpio-keys";
82 #address-cells = <1>;
83 #size-cells = <0>;
84 autorepeat;
85
86 switch9 {
87 label = "volume-up";
88 linux,code = <115>;
89 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
90 wakeup-source;
91 };
92
93 switch10 {
94 label = "volume-down";
95 linux,code = <114>;
96 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
97 wakeup-source;
98 };
99 };
100
101 backlight {
102 compatible = "pwm-backlight";
103 pwms = <&ecap0 0 50000 0>;
104 brightness-levels = <0 51 53 56 62 75 101 152 255>;
105 default-brightness-level = <8>;
106 };
107
108 panel {
109 compatible = "ti,tilcdc,panel";
110 status = "okay";
111 pinctrl-names = "default";
112 pinctrl-0 = <&lcd_pins_s0>;
113 panel-info {
114 ac-bias = <255>;
115 ac-bias-intrpt = <0>;
116 dma-burst-sz = <16>;
117 bpp = <32>;
118 fdd = <0x80>;
119 sync-edge = <0>;
120 sync-ctrl = <1>;
121 raster-order = <0>;
122 fifo-th = <0>;
123 };
124
125 display-timings {
126 800x480p62 {
127 clock-frequency = <30000000>;
128 hactive = <800>;
129 vactive = <480>;
130 hfront-porch = <39>;
131 hback-porch = <39>;
132 hsync-len = <47>;
133 vback-porch = <29>;
134 vfront-porch = <13>;
135 vsync-len = <2>;
136 hsync-active = <1>;
137 vsync-active = <1>;
138 };
139 };
140 };
141
142 sound {
143 compatible = "simple-audio-card";
144 simple-audio-card,name = "AM335x-EVM";
145 simple-audio-card,widgets =
146 "Headphone", "Headphone Jack",
147 "Line", "Line In";
148 simple-audio-card,routing =
149 "Headphone Jack", "HPLOUT",
150 "Headphone Jack", "HPROUT",
151 "LINE1L", "Line In",
152 "LINE1R", "Line In";
153 simple-audio-card,format = "dsp_b";
154 simple-audio-card,bitclock-master = <&sound_master>;
155 simple-audio-card,frame-master = <&sound_master>;
156 simple-audio-card,bitclock-inversion;
157
158 simple-audio-card,cpu {
159 sound-dai = <&mcasp1>;
160 };
161
162 sound_master: simple-audio-card,codec {
163 sound-dai = <&tlv320aic3106>;
164 system-clock-frequency = <12000000>;
165 };
166 };
167};
168
169&am33xx_pinmux {
170 pinctrl-names = "default";
171 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
172
173 matrix_keypad_s0: matrix_keypad_s0 {
174 pinctrl-single,pins = <
175 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
176 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
177 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
178 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
179 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
180 >;
181 };
182
183 volume_keys_s0: volume_keys_s0 {
184 pinctrl-single,pins = <
185 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
186 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
187 >;
188 };
189
190 i2c0_pins: pinmux_i2c0_pins {
191 pinctrl-single,pins = <
192 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
193 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
194 >;
195 };
196
197 i2c1_pins: pinmux_i2c1_pins {
198 pinctrl-single,pins = <
199 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
200 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
201 >;
202 };
203
204 uart0_pins: pinmux_uart0_pins {
205 pinctrl-single,pins = <
206 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
207 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
208 >;
209 };
210
211 uart1_pins: pinmux_uart1_pins {
212 pinctrl-single,pins = <
213 AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
214 AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
215 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
216 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
217 >;
218 };
219
220 clkout2_pin: pinmux_clkout2_pin {
221 pinctrl-single,pins = <
222 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
223 >;
224 };
225
226 nandflash_pins_s0: nandflash_pins_s0 {
227 pinctrl-single,pins = <
228 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
229 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
230 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
231 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
232 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
233 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
234 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
235 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
236 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
237 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
238 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
239 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
240 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
241 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
242 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
243 >;
244 };
245
246 ecap0_pins: backlight_pins {
247 pinctrl-single,pins = <
248 AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
249 >;
250 };
251
252 cpsw_default: cpsw_default {
253 pinctrl-single,pins = <
254 /* Slave 1 */
255 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
256 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
257 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
258 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
259 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
260 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
261 AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
262 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
263 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
264 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
265 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
266 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
267 >;
268 };
269
270 cpsw_sleep: cpsw_sleep {
271 pinctrl-single,pins = <
272 /* Slave 1 reset value */
273 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
274 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
275 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
276 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
277 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
278 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
279 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
280 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
281 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
282 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
283 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
284 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
285 >;
286 };
287
288 davinci_mdio_default: davinci_mdio_default {
289 pinctrl-single,pins = <
290 /* MDIO */
291 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
292 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
293 >;
294 };
295
296 davinci_mdio_sleep: davinci_mdio_sleep {
297 pinctrl-single,pins = <
298 /* MDIO reset value */
299 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
300 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
301 >;
302 };
303
304 mmc1_pins: pinmux_mmc1_pins {
305 pinctrl-single,pins = <
306 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
307 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
308 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
309 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
310 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
311 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
312 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
313 AM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */
314 >;
315 };
316
317 mmc3_pins: pinmux_mmc3_pins {
318 pinctrl-single,pins = <
319 AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
320 AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
321 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
322 AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
323 AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
324 AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
325 >;
326 };
327
328 wlan_pins: pinmux_wlan_pins {
329 pinctrl-single,pins = <
330 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
331 AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
332 AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
333 >;
334 };
335
336 lcd_pins_s0: lcd_pins_s0 {
337 pinctrl-single,pins = <
338 AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
339 AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
340 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
341 AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
342 AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
343 AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
344 AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
345 AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
346 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
347 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
348 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
349 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
350 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
351 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
352 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
353 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
354 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
355 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
356 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
357 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
358 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
359 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
360 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
361 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
362 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
363 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
364 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
365 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
366 >;
367 };
368
369 mcasp1_pins: mcasp1_pins {
370 pinctrl-single,pins = <
371 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
372 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
373 AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
374 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
375 >;
376 };
377
378 mcasp1_pins_sleep: mcasp1_pins_sleep {
379 pinctrl-single,pins = <
380 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
381 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
382 AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
383 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
384 >;
385 };
386
387 dcan1_pins_default: dcan1_pins_default {
388 pinctrl-single,pins = <
389 AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
390 AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
391 >;
392 };
393};
394
395&uart0 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart0_pins>;
398
399 status = "okay";
400};
401
402&uart1 {
403 pinctrl-names = "default";
404 pinctrl-0 = <&uart1_pins>;
405
406 status = "okay";
407};
408
409&i2c0 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&i2c0_pins>;
412
413 status = "okay";
414 clock-frequency = <400000>;
415
416 tps: tps@2d {
417 reg = <0x2d>;
418 };
419};
420
421&usb {
422 status = "okay";
423};
424
425&usb_ctrl_mod {
426 status = "okay";
427};
428
429&usb0_phy {
430 status = "okay";
431};
432
433&usb1_phy {
434 status = "okay";
435};
436
437&usb0 {
438 status = "okay";
439};
440
441&usb1 {
442 status = "okay";
443 dr_mode = "host";
444};
445
446&cppi41dma {
447 status = "okay";
448};
449
450&i2c1 {
451 pinctrl-names = "default";
452 pinctrl-0 = <&i2c1_pins>;
453
454 status = "okay";
455 clock-frequency = <100000>;
456
457 lis331dlh: lis331dlh@18 {
458 compatible = "st,lis331dlh", "st,lis3lv02d";
459 reg = <0x18>;
460 Vdd-supply = <&lis3_reg>;
461 Vdd_IO-supply = <&lis3_reg>;
462
463 st,click-single-x;
464 st,click-single-y;
465 st,click-single-z;
466 st,click-thresh-x = <10>;
467 st,click-thresh-y = <10>;
468 st,click-thresh-z = <10>;
469 st,irq1-click;
470 st,irq2-click;
471 st,wakeup-x-lo;
472 st,wakeup-x-hi;
473 st,wakeup-y-lo;
474 st,wakeup-y-hi;
475 st,wakeup-z-lo;
476 st,wakeup-z-hi;
477 st,min-limit-x = <120>;
478 st,min-limit-y = <120>;
479 st,min-limit-z = <140>;
480 st,max-limit-x = <550>;
481 st,max-limit-y = <550>;
482 st,max-limit-z = <750>;
483 };
484
485 tsl2550: tsl2550@39 {
486 compatible = "taos,tsl2550";
487 reg = <0x39>;
488 };
489
490 tmp275: tmp275@48 {
491 compatible = "ti,tmp275";
492 reg = <0x48>;
493 };
494
495 tlv320aic3106: tlv320aic3106@1b {
496 #sound-dai-cells = <0>;
497 compatible = "ti,tlv320aic3106";
498 reg = <0x1b>;
499 status = "okay";
500
501 /* Regulators */
502 AVDD-supply = <&vaux2_reg>;
503 IOVDD-supply = <&vaux2_reg>;
504 DRVDD-supply = <&vaux2_reg>;
505 DVDD-supply = <&vbat>;
506 };
507};
508
509&lcdc {
510 status = "okay";
511
512 blue-and-red-wiring = "crossed";
513};
514
515&elm {
516 status = "okay";
517};
518
519&epwmss0 {
520 status = "okay";
521
522 ecap0: ecap@48300100 {
523 status = "okay";
524 pinctrl-names = "default";
525 pinctrl-0 = <&ecap0_pins>;
526 };
527};
528
529&gpmc {
530 status = "okay";
531 pinctrl-names = "default";
532 pinctrl-0 = <&nandflash_pins_s0>;
533 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
534 nand@0,0 {
535 compatible = "ti,omap2-nand";
536 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
537 interrupt-parent = <&gpmc>;
538 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
539 <1 IRQ_TYPE_NONE>; /* termcount */
540 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
541 ti,nand-xfer-type = "prefetch-dma";
542 ti,nand-ecc-opt = "bch8";
543 ti,elm-id = <&elm>;
544 nand-bus-width = <8>;
545 gpmc,device-width = <1>;
546 gpmc,sync-clk-ps = <0>;
547 gpmc,cs-on-ns = <0>;
548 gpmc,cs-rd-off-ns = <44>;
549 gpmc,cs-wr-off-ns = <44>;
550 gpmc,adv-on-ns = <6>;
551 gpmc,adv-rd-off-ns = <34>;
552 gpmc,adv-wr-off-ns = <44>;
553 gpmc,we-on-ns = <0>;
554 gpmc,we-off-ns = <40>;
555 gpmc,oe-on-ns = <0>;
556 gpmc,oe-off-ns = <54>;
557 gpmc,access-ns = <64>;
558 gpmc,rd-cycle-ns = <82>;
559 gpmc,wr-cycle-ns = <82>;
560 gpmc,bus-turnaround-ns = <0>;
561 gpmc,cycle2cycle-delay-ns = <0>;
562 gpmc,clk-activation-ns = <0>;
563 gpmc,wr-access-ns = <40>;
564 gpmc,wr-data-mux-bus-ns = <0>;
565 /* MTD partition table */
566 /* All SPL-* partitions are sized to minimal length
567 * which can be independently programmable. For
568 * NAND flash this is equal to size of erase-block */
569 #address-cells = <1>;
570 #size-cells = <1>;
571 partition@0 {
572 label = "NAND.SPL";
573 reg = <0x00000000 0x000020000>;
574 };
575 partition@1 {
576 label = "NAND.SPL.backup1";
577 reg = <0x00020000 0x00020000>;
578 };
579 partition@2 {
580 label = "NAND.SPL.backup2";
581 reg = <0x00040000 0x00020000>;
582 };
583 partition@3 {
584 label = "NAND.SPL.backup3";
585 reg = <0x00060000 0x00020000>;
586 };
587 partition@4 {
588 label = "NAND.u-boot-spl-os";
589 reg = <0x00080000 0x00040000>;
590 };
591 partition@5 {
592 label = "NAND.u-boot";
593 reg = <0x000C0000 0x00100000>;
594 };
595 partition@6 {
596 label = "NAND.u-boot-env";
597 reg = <0x001C0000 0x00020000>;
598 };
599 partition@7 {
600 label = "NAND.u-boot-env.backup1";
601 reg = <0x001E0000 0x00020000>;
602 };
603 partition@8 {
604 label = "NAND.kernel";
605 reg = <0x00200000 0x00800000>;
606 };
607 partition@9 {
608 label = "NAND.file-system";
609 reg = <0x00A00000 0x0F600000>;
610 };
611 };
612};
613
614#include "tps65910.dtsi"
615
616&mcasp1 {
617 #sound-dai-cells = <0>;
618 pinctrl-names = "default", "sleep";
619 pinctrl-0 = <&mcasp1_pins>;
620 pinctrl-1 = <&mcasp1_pins_sleep>;
621
622 status = "okay";
623
624 op-mode = <0>; /* MCASP_IIS_MODE */
625 tdm-slots = <2>;
626 /* 4 serializers */
627 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
628 0 0 1 2
629 >;
630 tx-num-evt = <32>;
631 rx-num-evt = <32>;
632};
633
634&tps {
635 vcc1-supply = <&vbat>;
636 vcc2-supply = <&vbat>;
637 vcc3-supply = <&vbat>;
638 vcc4-supply = <&vbat>;
639 vcc5-supply = <&vbat>;
640 vcc6-supply = <&vbat>;
641 vcc7-supply = <&vbat>;
642 vccio-supply = <&vbat>;
643
644 regulators {
645 vrtc_reg: regulator@0 {
646 regulator-always-on;
647 };
648
649 vio_reg: regulator@1 {
650 regulator-always-on;
651 };
652
653 vdd1_reg: regulator@2 {
654 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
655 regulator-name = "vdd_mpu";
656 regulator-min-microvolt = <912500>;
657 regulator-max-microvolt = <1351500>;
658 regulator-boot-on;
659 regulator-always-on;
660 };
661
662 vdd2_reg: regulator@3 {
663 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
664 regulator-name = "vdd_core";
665 regulator-min-microvolt = <912500>;
666 regulator-max-microvolt = <1150000>;
667 regulator-boot-on;
668 regulator-always-on;
669 };
670
671 vdd3_reg: regulator@4 {
672 regulator-always-on;
673 };
674
675 vdig1_reg: regulator@5 {
676 regulator-always-on;
677 };
678
679 vdig2_reg: regulator@6 {
680 regulator-always-on;
681 };
682
683 vpll_reg: regulator@7 {
684 regulator-always-on;
685 };
686
687 vdac_reg: regulator@8 {
688 regulator-always-on;
689 };
690
691 vaux1_reg: regulator@9 {
692 regulator-always-on;
693 };
694
695 vaux2_reg: regulator@10 {
696 regulator-always-on;
697 };
698
699 vaux33_reg: regulator@11 {
700 regulator-always-on;
701 };
702
703 vmmc_reg: regulator@12 {
704 regulator-min-microvolt = <1800000>;
705 regulator-max-microvolt = <3300000>;
706 regulator-always-on;
707 };
708 };
709};
710
711&mac {
712 pinctrl-names = "default", "sleep";
713 pinctrl-0 = <&cpsw_default>;
714 pinctrl-1 = <&cpsw_sleep>;
715 status = "okay";
716};
717
718&davinci_mdio {
719 pinctrl-names = "default", "sleep";
720 pinctrl-0 = <&davinci_mdio_default>;
721 pinctrl-1 = <&davinci_mdio_sleep>;
722 status = "okay";
723};
724
725&cpsw_emac0 {
726 phy_id = <&davinci_mdio>, <0>;
727 phy-mode = "rgmii-txid";
728};
729
730&cpsw_emac1 {
731 phy_id = <&davinci_mdio>, <1>;
732 phy-mode = "rgmii-txid";
733};
734
735&tscadc {
736 status = "okay";
737 tsc {
738 ti,wires = <4>;
739 ti,x-plate-resistance = <200>;
740 ti,coordinate-readouts = <5>;
741 ti,wire-config = <0x00 0x11 0x22 0x33>;
742 ti,charge-delay = <0x400>;
743 };
744
745 adc {
746 ti,adc-channels = <4 5 6 7>;
747 };
748};
749
750&mmc1 {
751 status = "okay";
752 vmmc-supply = <&vmmc_reg>;
753 bus-width = <4>;
754 pinctrl-names = "default";
755 pinctrl-0 = <&mmc1_pins>;
756 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
757};
758
759&mmc3 {
760 /* these are on the crossbar and are outlined in the
761 xbar-event-map element */
762 dmas = <&edma_xbar 12 0 1
763 &edma_xbar 13 0 2>;
764 dma-names = "tx", "rx";
765 status = "okay";
766 vmmc-supply = <&wlan_en_reg>;
767 bus-width = <4>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&mmc3_pins &wlan_pins>;
770 ti,non-removable;
771 ti,needs-special-hs-handling;
772 cap-power-off-card;
773 keep-power-in-suspend;
774
775 #address-cells = <1>;
776 #size-cells = <0>;
777 wlcore: wlcore@0 {
778 compatible = "ti,wl1835";
779 reg = <2>;
780 interrupt-parent = <&gpio3>;
781 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
782 };
783};
784
785&sham {
786 status = "okay";
787};
788
789&aes {
790 status = "okay";
791};
792
793&dcan1 {
794 status = "disabled"; /* Enable only if Profile 1 is selected */
795 pinctrl-names = "default";
796 pinctrl-0 = <&dcan1_pins_default>;
797};
798
799&rtc {
800 clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
801 clock-names = "ext-clk", "int-clk";
802};