| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * R-Car Generation 2 Power management support |
| 3 | * |
| 4 | * Copyright (C) 2013 - 2015 Renesas Electronics Corporation |
| 5 | * Copyright (C) 2011 Renesas Solutions Corp. |
| 6 | * Copyright (C) 2011 Magnus Damm |
| 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file "COPYING" in the main directory of this archive |
| 10 | * for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/of.h> |
| 16 | #include <linux/of_address.h> |
| 17 | #include <linux/smp.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <asm/cputype.h> |
| 20 | #include "common.h" |
| 21 | #include "rcar-gen2.h" |
| 22 | |
| 23 | /* RST */ |
| 24 | #define RST 0xe6160000 |
| 25 | |
| 26 | #define CA15BAR 0x0020 /* CA15 Boot Address Register */ |
| 27 | #define CA7BAR 0x0030 /* CA7 Boot Address Register */ |
| 28 | #define CA15RESCNT 0x0040 /* CA15 Reset Control Register */ |
| 29 | #define CA7RESCNT 0x0044 /* CA7 Reset Control Register */ |
| 30 | |
| 31 | /* SYS Boot Address Register */ |
| 32 | #define SBAR_BAREN BIT(4) /* SBAR is valid */ |
| 33 | |
| 34 | /* Reset Control Registers */ |
| 35 | #define CA15RESCNT_CODE 0xa5a50000 |
| 36 | #define CA15RESCNT_CPUS 0xf /* CPU0-3 */ |
| 37 | #define CA7RESCNT_CODE 0x5a5a0000 |
| 38 | #define CA7RESCNT_CPUS 0xf /* CPU0-3 */ |
| 39 | |
| 40 | /* On-chip RAM */ |
| 41 | #define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */ |
| 42 | |
| 43 | static inline u32 phys_to_sbar(phys_addr_t addr) |
| 44 | { |
| 45 | return (addr >> 8) & 0xfffffc00; |
| 46 | } |
| 47 | |
| 48 | void __init rcar_gen2_pm_init(void) |
| 49 | { |
| 50 | void __iomem *p; |
| 51 | u32 bar; |
| 52 | static int once; |
| 53 | struct device_node *np, *cpus; |
| 54 | bool has_a7 = false; |
| 55 | bool has_a15 = false; |
| 56 | struct resource res; |
| 57 | int error; |
| 58 | |
| 59 | if (once++) |
| 60 | return; |
| 61 | |
| 62 | cpus = of_find_node_by_path("/cpus"); |
| 63 | if (!cpus) |
| 64 | return; |
| 65 | |
| 66 | for_each_child_of_node(cpus, np) { |
| 67 | if (of_device_is_compatible(np, "arm,cortex-a15")) |
| 68 | has_a15 = true; |
| 69 | else if (of_device_is_compatible(np, "arm,cortex-a7")) |
| 70 | has_a7 = true; |
| 71 | } |
| 72 | |
| 73 | np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram"); |
| 74 | if (!np) { |
| 75 | /* No smp-sram in DT, fall back to hardcoded address */ |
| 76 | res = (struct resource)DEFINE_RES_MEM(ICRAM1, |
| 77 | shmobile_boot_size); |
| 78 | goto map; |
| 79 | } |
| 80 | |
| 81 | error = of_address_to_resource(np, 0, &res); |
| 82 | if (error) { |
| 83 | pr_err("Failed to get smp-sram address: %d\n", error); |
| 84 | return; |
| 85 | } |
| 86 | |
| 87 | map: |
| 88 | /* RAM for jump stub, because BAR requires 256KB aligned address */ |
| 89 | if (res.start & (256 * 1024 - 1) || |
| 90 | resource_size(&res) < shmobile_boot_size) { |
| 91 | pr_err("Invalid smp-sram region\n"); |
| 92 | return; |
| 93 | } |
| 94 | |
| 95 | p = ioremap(res.start, resource_size(&res)); |
| 96 | if (!p) |
| 97 | return; |
| 98 | /* |
| 99 | * install the reset vector, use the largest version if we have enough |
| 100 | * memory available |
| 101 | */ |
| 102 | if (resource_size(&res) >= shmobile_boot_size_gen2) { |
| 103 | shmobile_boot_cpu_gen2 = read_cpuid_mpidr(); |
| 104 | memcpy_toio(p, shmobile_boot_vector_gen2, |
| 105 | shmobile_boot_size_gen2); |
| 106 | } else { |
| 107 | memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size); |
| 108 | } |
| 109 | iounmap(p); |
| 110 | |
| 111 | /* setup reset vectors */ |
| 112 | p = ioremap_nocache(RST, 0x63); |
| 113 | bar = phys_to_sbar(res.start); |
| 114 | if (has_a15) { |
| 115 | writel_relaxed(bar, p + CA15BAR); |
| 116 | writel_relaxed(bar | SBAR_BAREN, p + CA15BAR); |
| 117 | |
| 118 | /* de-assert reset for CA15 CPUs */ |
| 119 | writel_relaxed((readl_relaxed(p + CA15RESCNT) & |
| 120 | ~CA15RESCNT_CPUS) | CA15RESCNT_CODE, |
| 121 | p + CA15RESCNT); |
| 122 | } |
| 123 | if (has_a7) { |
| 124 | writel_relaxed(bar, p + CA7BAR); |
| 125 | writel_relaxed(bar | SBAR_BAREN, p + CA7BAR); |
| 126 | |
| 127 | /* de-assert reset for CA7 CPUs */ |
| 128 | writel_relaxed((readl_relaxed(p + CA7RESCNT) & |
| 129 | ~CA7RESCNT_CPUS) | CA7RESCNT_CODE, |
| 130 | p + CA7RESCNT); |
| 131 | } |
| 132 | iounmap(p); |
| 133 | |
| 134 | shmobile_smp_apmu_suspend_init(); |
| 135 | } |