| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | Introduction |
| 2 | ============ |
| 3 | |
| 4 | The FPGA subsystem supports reprogramming FPGAs dynamically under |
| 5 | Linux. Some of the core intentions of the FPGA subsystems are: |
| 6 | |
| 7 | * The FPGA subsystem is vendor agnostic. |
| 8 | |
| 9 | * The FPGA subsystem separates upper layers (userspace interfaces and |
| 10 | enumeration) from lower layers that know how to program a specific |
| 11 | FPGA. |
| 12 | |
| 13 | * Code should not be shared between upper and lower layers. This |
| 14 | should go without saying. If that seems necessary, there's probably |
| 15 | framework functionality that can be added that will benefit |
| 16 | other users. Write the linux-fpga mailing list and maintainers and |
| 17 | seek out a solution that expands the framework for broad reuse. |
| 18 | |
| 19 | * Generally, when adding code, think of the future. Plan for reuse. |
| 20 | |
| 21 | The framework in the kernel is divided into: |
| 22 | |
| 23 | FPGA Manager |
| 24 | ------------ |
| 25 | |
| 26 | If you are adding a new FPGA or a new method of programming an FPGA, |
| 27 | this is the subsystem for you. Low level FPGA manager drivers contain |
| 28 | the knowledge of how to program a specific device. This subsystem |
| 29 | includes the framework in fpga-mgr.c and the low level drivers that |
| 30 | are registered with it. |
| 31 | |
| 32 | FPGA Bridge |
| 33 | ----------- |
| 34 | |
| 35 | FPGA Bridges prevent spurious signals from going out of an FPGA or a |
| 36 | region of an FPGA during programming. They are disabled before |
| 37 | programming begins and re-enabled afterwards. An FPGA bridge may be |
| 38 | actual hard hardware that gates a bus to a CPU or a soft ("freeze") |
| 39 | bridge in FPGA fabric that surrounds a partial reconfiguration region |
| 40 | of an FPGA. This subsystem includes fpga-bridge.c and the low level |
| 41 | drivers that are registered with it. |
| 42 | |
| 43 | FPGA Region |
| 44 | ----------- |
| 45 | |
| 46 | If you are adding a new interface to the FPGA framework, add it on top |
| 47 | of an FPGA region to allow the most reuse of your interface. |
| 48 | |
| 49 | The FPGA Region framework (fpga-region.c) associates managers and |
| 50 | bridges as reconfigurable regions. A region may refer to the whole |
| 51 | FPGA in full reconfiguration or to a partial reconfiguration region. |
| 52 | |
| 53 | The Device Tree FPGA Region support (of-fpga-region.c) handles |
| 54 | reprogramming FPGAs when device tree overlays are applied. |