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David Brazdil0f672f62019-12-10 10:32:29 +00001/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2017-2018, Intel Corporation
4 */
5
6#ifndef __STRATIX10_SMC_H
7#define __STRATIX10_SMC_H
8
9#include <linux/arm-smccc.h>
10#include <linux/bitops.h>
11
12/**
13 * This file defines the Secure Monitor Call (SMC) message protocol used for
14 * service layer driver in normal world (EL1) to communicate with secure
15 * monitor software in Secure Monitor Exception Level 3 (EL3).
16 *
17 * This file is shared with secure firmware (FW) which is out of kernel tree.
18 *
19 * An ARM SMC instruction takes a function identifier and up to 6 64-bit
20 * register values as arguments, and can return up to 4 64-bit register
21 * value. The operation of the secure monitor is determined by the parameter
22 * values passed in through registers.
23 *
24 * EL1 and EL3 communicates pointer as physical address rather than the
25 * virtual address.
26 *
27 * Functions specified by ARM SMC Calling convention:
28 *
29 * FAST call executes atomic operations, returns when the requested operation
30 * has completed.
31 * STD call starts a operation which can be preempted by a non-secure
32 * interrupt. The call can return before the requested operation has
33 * completed.
34 *
35 * a0..a7 is used as register names in the descriptions below, on arm32
36 * that translates to r0..r7 and on arm64 to w0..w7.
37 */
38
39/**
40 * @func_num: function ID
41 */
42#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
43 ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
44 ARM_SMCCC_OWNER_SIP, (func_num))
45
46#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
47 ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
48 ARM_SMCCC_OWNER_SIP, (func_num))
49
50/**
51 * Return values in INTEL_SIP_SMC_* call
52 *
53 * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION:
54 * Secure monitor software doesn't recognize the request.
55 *
56 * INTEL_SIP_SMC_STATUS_OK:
Olivier Deprez157378f2022-04-04 15:47:50 +020057 * Secure monitor software accepts the service client's request.
David Brazdil0f672f62019-12-10 10:32:29 +000058 *
Olivier Deprez157378f2022-04-04 15:47:50 +020059 * INTEL_SIP_SMC_STATUS_BUSY:
60 * Secure monitor software is still processing service client's request.
David Brazdil0f672f62019-12-10 10:32:29 +000061 *
Olivier Deprez157378f2022-04-04 15:47:50 +020062 * INTEL_SIP_SMC_STATUS_REJECTED:
63 * Secure monitor software reject the service client's request.
David Brazdil0f672f62019-12-10 10:32:29 +000064 *
Olivier Deprez157378f2022-04-04 15:47:50 +020065 * INTEL_SIP_SMC_STATUS_ERROR:
66 * There is error during the process of service request.
David Brazdil0f672f62019-12-10 10:32:29 +000067 *
68 * INTEL_SIP_SMC_RSU_ERROR:
Olivier Deprez157378f2022-04-04 15:47:50 +020069 * There is error during the process of remote status update request.
David Brazdil0f672f62019-12-10 10:32:29 +000070 */
71#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION 0xFFFFFFFF
72#define INTEL_SIP_SMC_STATUS_OK 0x0
Olivier Deprez157378f2022-04-04 15:47:50 +020073#define INTEL_SIP_SMC_STATUS_BUSY 0x1
74#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
75#define INTEL_SIP_SMC_STATUS_ERROR 0x4
David Brazdil0f672f62019-12-10 10:32:29 +000076#define INTEL_SIP_SMC_RSU_ERROR 0x7
77
78/**
79 * Request INTEL_SIP_SMC_FPGA_CONFIG_START
80 *
81 * Sync call used by service driver at EL1 to request the FPGA in EL3 to
82 * be prepare to receive a new configuration.
83 *
84 * Call register usage:
85 * a0: INTEL_SIP_SMC_FPGA_CONFIG_START.
86 * a1: flag for full or partial configuration. 0 for full and 1 for partial
87 * configuration.
88 * a2-7: not used.
89 *
90 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +020091 * a0: INTEL_SIP_SMC_STATUS_OK, or INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +000092 * a1-3: not used.
93 */
94#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START 1
95#define INTEL_SIP_SMC_FPGA_CONFIG_START \
96 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_START)
97
98/**
99 * Request INTEL_SIP_SMC_FPGA_CONFIG_WRITE
100 *
101 * Async call used by service driver at EL1 to provide FPGA configuration data
102 * to secure world.
103 *
104 * Call register usage:
105 * a0: INTEL_SIP_SMC_FPGA_CONFIG_WRITE.
106 * a1: 64bit physical address of the configuration data memory block
107 * a2: Size of configuration data block.
108 * a3-7: not used.
109 *
110 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +0200111 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
112 * INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +0000113 * a1: 64bit physical address of 1st completed memory block if any completed
114 * block, otherwise zero value.
115 * a2: 64bit physical address of 2nd completed memory block if any completed
116 * block, otherwise zero value.
117 * a3: 64bit physical address of 3rd completed memory block if any completed
118 * block, otherwise zero value.
119 */
120#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE 2
121#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE \
122 INTEL_SIP_SMC_STD_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_WRITE)
123
124/**
125 * Request INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE
126 *
127 * Sync call used by service driver at EL1 to track the completed write
128 * transactions. This request is called after INTEL_SIP_SMC_FPGA_CONFIG_WRITE
Olivier Deprez157378f2022-04-04 15:47:50 +0200129 * call returns INTEL_SIP_SMC_STATUS_BUSY.
David Brazdil0f672f62019-12-10 10:32:29 +0000130 *
131 * Call register usage:
132 * a0: INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE.
133 * a1-7: not used.
134 *
135 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +0200136 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_FPGA_BUSY or
137 * INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +0000138 * a1: 64bit physical address of 1st completed memory block.
139 * a2: 64bit physical address of 2nd completed memory block if
140 * any completed block, otherwise zero value.
141 * a3: 64bit physical address of 3rd completed memory block if
142 * any completed block, otherwise zero value.
143 */
144#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE 3
145#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE \
146INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
147
148/**
149 * Request INTEL_SIP_SMC_FPGA_CONFIG_ISDONE
150 *
151 * Sync call used by service driver at EL1 to inform secure world that all
152 * data are sent, to check whether or not the secure world had completed
153 * the FPGA configuration process.
154 *
155 * Call register usage:
156 * a0: INTEL_SIP_SMC_FPGA_CONFIG_ISDONE.
157 * a1-7: not used.
158 *
159 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +0200160 * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_STATUS_BUSY or
161 * INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +0000162 * a1-3: not used.
163 */
164#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE 4
165#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE \
166 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_ISDONE)
167
168/**
169 * Request INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM
170 *
171 * Sync call used by service driver at EL1 to query the physical address of
172 * memory block reserved by secure monitor software.
173 *
174 * Call register usage:
175 * a0:INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM.
176 * a1-7: not used.
177 *
178 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +0200179 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +0000180 * a1: start of physical address of reserved memory block.
181 * a2: size of reserved memory block.
182 * a3: not used.
183 */
184#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM 5
185#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM \
186 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_GET_MEM)
187
188/**
189 * Request INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK
190 *
191 * For SMC loop-back mode only, used for internal integration, debugging
192 * or troubleshooting.
193 *
194 * Call register usage:
195 * a0: INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK.
196 * a1-7: not used.
197 *
198 * Return status:
Olivier Deprez157378f2022-04-04 15:47:50 +0200199 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_STATUS_ERROR.
David Brazdil0f672f62019-12-10 10:32:29 +0000200 * a1-3: not used.
201 */
202#define INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK 6
203#define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
204 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
205
206/**
207 * Request INTEL_SIP_SMC_REG_READ
208 *
209 * Read a protected register at EL3
210 *
211 * Call register usage:
212 * a0: INTEL_SIP_SMC_REG_READ.
213 * a1: register address.
214 * a2-7: not used.
215 *
216 * Return status:
217 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
218 * a1: value in the register
219 * a2-3: not used.
220 */
221#define INTEL_SIP_SMC_FUNCID_REG_READ 7
222#define INTEL_SIP_SMC_REG_READ \
223 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
224
225/**
226 * Request INTEL_SIP_SMC_REG_WRITE
227 *
228 * Write a protected register at EL3
229 *
230 * Call register usage:
231 * a0: INTEL_SIP_SMC_REG_WRITE.
232 * a1: register address
233 * a2: value to program into register.
234 * a3-7: not used.
235 *
236 * Return status:
237 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
238 * a1-3: not used.
239 */
240#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
241#define INTEL_SIP_SMC_REG_WRITE \
242 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
243
244/**
245 * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
246 *
247 * Update one or more bits in a protected register at EL3 using a
248 * read-modify-write operation.
249 *
250 * Call register usage:
251 * a0: INTEL_SIP_SMC_REG_UPDATE.
252 * a1: register address
253 * a2: write Mask.
254 * a3: value to write.
255 * a4-7: not used.
256 *
257 * Return status:
258 * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
259 * a1-3: Not used.
260 */
261#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
262#define INTEL_SIP_SMC_REG_UPDATE \
263 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
264
265/**
266 * Request INTEL_SIP_SMC_RSU_STATUS
267 *
268 * Request remote status update boot log, call is synchronous.
269 *
270 * Call register usage:
271 * a0 INTEL_SIP_SMC_RSU_STATUS
272 * a1-7 not used
273 *
274 * Return status
275 * a0: Current Image
276 * a1: Last Failing Image
277 * a2: Version | State
278 * a3: Error details | Error location
279 *
280 * Or
281 *
282 * a0: INTEL_SIP_SMC_RSU_ERROR
283 */
284#define INTEL_SIP_SMC_FUNCID_RSU_STATUS 11
285#define INTEL_SIP_SMC_RSU_STATUS \
286 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_STATUS)
287
288/**
289 * Request INTEL_SIP_SMC_RSU_UPDATE
290 *
291 * Request to set the offset of the bitstream to boot after reboot, call
292 * is synchronous.
293 *
294 * Call register usage:
295 * a0 INTEL_SIP_SMC_RSU_UPDATE
296 * a1 64bit physical address of the configuration data memory in flash
297 * a2-7 not used
298 *
299 * Return status
300 * a0 INTEL_SIP_SMC_STATUS_OK
301 */
302#define INTEL_SIP_SMC_FUNCID_RSU_UPDATE 12
303#define INTEL_SIP_SMC_RSU_UPDATE \
304 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_UPDATE)
305
306/**
307 * Request INTEL_SIP_SMC_ECC_DBE
308 *
309 * Sync call used by service driver at EL1 to alert EL3 that a Double
310 * Bit ECC error has occurred.
311 *
312 * Call register usage:
313 * a0 INTEL_SIP_SMC_ECC_DBE
314 * a1 SysManager Double Bit Error value
315 * a2-7 not used
316 *
317 * Return status
318 * a0 INTEL_SIP_SMC_STATUS_OK
319 */
320#define INTEL_SIP_SMC_FUNCID_ECC_DBE 13
321#define INTEL_SIP_SMC_ECC_DBE \
322 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_ECC_DBE)
323
324#endif
325
326/**
327 * Request INTEL_SIP_SMC_RSU_NOTIFY
328 *
329 * Sync call used by service driver at EL1 to report hard processor
330 * system execution stage to firmware
331 *
332 * Call register usage:
333 * a0 INTEL_SIP_SMC_RSU_NOTIFY
334 * a1 32bit value representing hard processor system execution stage
335 * a2-7 not used
336 *
337 * Return status
338 * a0 INTEL_SIP_SMC_STATUS_OK
339 */
340#define INTEL_SIP_SMC_FUNCID_RSU_NOTIFY 14
341#define INTEL_SIP_SMC_RSU_NOTIFY \
342 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_NOTIFY)
343
344/**
345 * Request INTEL_SIP_SMC_RSU_RETRY_COUNTER
346 *
347 * Sync call used by service driver at EL1 to query RSU retry counter
348 *
349 * Call register usage:
350 * a0 INTEL_SIP_SMC_RSU_RETRY_COUNTER
351 * a1-7 not used
352 *
353 * Return status
354 * a0 INTEL_SIP_SMC_STATUS_OK
355 * a1 the retry counter
356 *
357 * Or
358 *
359 * a0 INTEL_SIP_SMC_RSU_ERROR
360 */
361#define INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER 15
362#define INTEL_SIP_SMC_RSU_RETRY_COUNTER \
363 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_RETRY_COUNTER)
Olivier Deprez157378f2022-04-04 15:47:50 +0200364
365/**
366 * Request INTEL_SIP_SMC_RSU_DCMF_VERSION
367 *
368 * Sync call used by service driver at EL1 to query DCMF (Decision
369 * Configuration Management Firmware) version from FW
370 *
371 * Call register usage:
372 * a0 INTEL_SIP_SMC_RSU_DCMF_VERSION
373 * a1-7 not used
374 *
375 * Return status
376 * a0 INTEL_SIP_SMC_STATUS_OK
377 * a1 dcmf1 | dcmf0
378 * a2 dcmf3 | dcmf2
379 *
380 * Or
381 *
382 * a0 INTEL_SIP_SMC_RSU_ERROR
383 */
384#define INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION 16
385#define INTEL_SIP_SMC_RSU_DCMF_VERSION \
386 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_DCMF_VERSION)
387
388/**
389 * Request INTEL_SIP_SMC_RSU_MAX_RETRY
390 *
391 * Sync call used by service driver at EL1 to query max retry value from FW
392 *
393 * Call register usage:
394 * a0 INTEL_SIP_SMC_RSU_MAX_RETRY
395 * a1-7 not used
396 *
397 * Return status
398 * a0 INTEL_SIP_SMC_STATUS_OK
399 * a1 max retry value
400 *
401 * Or
402 * a0 INTEL_SIP_SMC_RSU_ERROR
403 */
404#define INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY 18
405#define INTEL_SIP_SMC_RSU_MAX_RETRY \
406 INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_RSU_MAX_RETRY)