Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | #include <asm-generic/vmlinux.lds.h> |
| 3 | |
| 4 | #ifdef CONFIG_HOTPLUG_CPU |
| 5 | #define ARM_CPU_DISCARD(x) |
| 6 | #define ARM_CPU_KEEP(x) x |
| 7 | #else |
| 8 | #define ARM_CPU_DISCARD(x) x |
| 9 | #define ARM_CPU_KEEP(x) |
| 10 | #endif |
| 11 | |
| 12 | #if (defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)) || \ |
| 13 | defined(CONFIG_GENERIC_BUG) || defined(CONFIG_JUMP_LABEL) |
| 14 | #define ARM_EXIT_KEEP(x) x |
| 15 | #define ARM_EXIT_DISCARD(x) |
| 16 | #else |
| 17 | #define ARM_EXIT_KEEP(x) |
| 18 | #define ARM_EXIT_DISCARD(x) x |
| 19 | #endif |
| 20 | |
| 21 | #ifdef CONFIG_MMU |
| 22 | #define ARM_MMU_KEEP(x) x |
| 23 | #define ARM_MMU_DISCARD(x) |
| 24 | #else |
| 25 | #define ARM_MMU_KEEP(x) |
| 26 | #define ARM_MMU_DISCARD(x) x |
| 27 | #endif |
| 28 | |
| 29 | /* |
| 30 | * ld.lld does not support NOCROSSREFS: |
| 31 | * https://github.com/ClangBuiltLinux/linux/issues/1609 |
| 32 | */ |
| 33 | #ifdef CONFIG_LD_IS_LLD |
| 34 | #define NOCROSSREFS |
| 35 | #endif |
| 36 | |
| 37 | /* Set start/end symbol names to the LMA for the section */ |
| 38 | #define ARM_LMA(sym, section) \ |
| 39 | sym##_start = LOADADDR(section); \ |
| 40 | sym##_end = LOADADDR(section) + SIZEOF(section) |
| 41 | |
| 42 | #define PROC_INFO \ |
| 43 | . = ALIGN(4); \ |
| 44 | __proc_info_begin = .; \ |
| 45 | *(.proc.info.init) \ |
| 46 | __proc_info_end = .; |
| 47 | |
| 48 | #define IDMAP_TEXT \ |
| 49 | ALIGN_FUNCTION(); \ |
| 50 | __idmap_text_start = .; \ |
| 51 | *(.idmap.text) \ |
| 52 | __idmap_text_end = .; \ |
| 53 | |
| 54 | #define ARM_DISCARD \ |
| 55 | *(.ARM.exidx.exit.text) \ |
| 56 | *(.ARM.extab.exit.text) \ |
| 57 | *(.ARM.exidx.text.exit) \ |
| 58 | *(.ARM.extab.text.exit) \ |
| 59 | ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text)) \ |
| 60 | ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text)) \ |
| 61 | ARM_EXIT_DISCARD(EXIT_TEXT) \ |
| 62 | ARM_EXIT_DISCARD(EXIT_DATA) \ |
| 63 | EXIT_CALL \ |
| 64 | ARM_MMU_DISCARD(*(.text.fixup)) \ |
| 65 | ARM_MMU_DISCARD(*(__ex_table)) \ |
| 66 | COMMON_DISCARDS |
| 67 | |
| 68 | /* |
| 69 | * Sections that should stay zero sized, which is safer to explicitly |
| 70 | * check instead of blindly discarding. |
| 71 | */ |
| 72 | #define ARM_ASSERTS \ |
| 73 | .plt : { \ |
| 74 | *(.iplt) *(.rel.iplt) *(.iplt) *(.igot.plt) \ |
| 75 | } \ |
| 76 | ASSERT(SIZEOF(.plt) == 0, \ |
| 77 | "Unexpected run-time procedure linkages detected!") |
| 78 | |
| 79 | #define ARM_DETAILS \ |
| 80 | ELF_DETAILS \ |
| 81 | .ARM.attributes 0 : { *(.ARM.attributes) } |
| 82 | |
| 83 | #define ARM_STUBS_TEXT \ |
| 84 | *(.gnu.warning) \ |
| 85 | *(.glue_7) \ |
| 86 | *(.glue_7t) \ |
| 87 | *(.vfp11_veneer) \ |
| 88 | *(.v4_bx) |
| 89 | |
| 90 | #define ARM_TEXT \ |
| 91 | IDMAP_TEXT \ |
| 92 | __entry_text_start = .; \ |
| 93 | *(.entry.text) \ |
| 94 | __entry_text_end = .; \ |
| 95 | IRQENTRY_TEXT \ |
| 96 | SOFTIRQENTRY_TEXT \ |
| 97 | TEXT_TEXT \ |
| 98 | SCHED_TEXT \ |
| 99 | CPUIDLE_TEXT \ |
| 100 | LOCK_TEXT \ |
| 101 | KPROBES_TEXT \ |
| 102 | ARM_STUBS_TEXT \ |
| 103 | . = ALIGN(4); \ |
| 104 | *(.got) /* Global offset table */ \ |
| 105 | ARM_CPU_KEEP(PROC_INFO) |
| 106 | |
| 107 | /* Stack unwinding tables */ |
| 108 | #define ARM_UNWIND_SECTIONS \ |
| 109 | . = ALIGN(8); \ |
| 110 | .ARM.unwind_idx : { \ |
| 111 | __start_unwind_idx = .; \ |
| 112 | *(.ARM.exidx*) \ |
| 113 | __stop_unwind_idx = .; \ |
| 114 | } \ |
| 115 | .ARM.unwind_tab : { \ |
| 116 | __start_unwind_tab = .; \ |
| 117 | *(.ARM.extab*) \ |
| 118 | __stop_unwind_tab = .; \ |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | * The vectors and stubs are relocatable code, and the |
| 123 | * only thing that matters is their relative offsets |
| 124 | */ |
| 125 | #define ARM_VECTORS \ |
| 126 | __vectors_lma = .; \ |
| 127 | OVERLAY 0xffff0000 : NOCROSSREFS AT(__vectors_lma) { \ |
| 128 | .vectors { \ |
| 129 | *(.vectors) \ |
| 130 | } \ |
| 131 | .vectors.bhb.loop8 { \ |
| 132 | *(.vectors.bhb.loop8) \ |
| 133 | } \ |
| 134 | .vectors.bhb.bpiall { \ |
| 135 | *(.vectors.bhb.bpiall) \ |
| 136 | } \ |
| 137 | } \ |
| 138 | ARM_LMA(__vectors, .vectors); \ |
| 139 | ARM_LMA(__vectors_bhb_loop8, .vectors.bhb.loop8); \ |
| 140 | ARM_LMA(__vectors_bhb_bpiall, .vectors.bhb.bpiall); \ |
| 141 | . = __vectors_lma + SIZEOF(.vectors) + \ |
| 142 | SIZEOF(.vectors.bhb.loop8) + \ |
| 143 | SIZEOF(.vectors.bhb.bpiall); \ |
| 144 | \ |
| 145 | __stubs_lma = .; \ |
| 146 | .stubs ADDR(.vectors) + 0x1000 : AT(__stubs_lma) { \ |
| 147 | *(.stubs) \ |
| 148 | } \ |
| 149 | ARM_LMA(__stubs, .stubs); \ |
| 150 | . = __stubs_lma + SIZEOF(.stubs); \ |
| 151 | \ |
| 152 | PROVIDE(vector_fiq_offset = vector_fiq - ADDR(.vectors)); |
| 153 | |
| 154 | #define ARM_TCM \ |
| 155 | __itcm_start = ALIGN(4); \ |
| 156 | .text_itcm ITCM_OFFSET : AT(__itcm_start - LOAD_OFFSET) { \ |
| 157 | __sitcm_text = .; \ |
| 158 | *(.tcm.text) \ |
| 159 | *(.tcm.rodata) \ |
| 160 | . = ALIGN(4); \ |
| 161 | __eitcm_text = .; \ |
| 162 | } \ |
| 163 | . = __itcm_start + SIZEOF(.text_itcm); \ |
| 164 | \ |
| 165 | __dtcm_start = .; \ |
| 166 | .data_dtcm DTCM_OFFSET : AT(__dtcm_start - LOAD_OFFSET) { \ |
| 167 | __sdtcm_data = .; \ |
| 168 | *(.tcm.data) \ |
| 169 | . = ALIGN(4); \ |
| 170 | __edtcm_data = .; \ |
| 171 | } \ |
| 172 | . = __dtcm_start + SIZEOF(.data_dtcm); |