| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 1 | * LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C |
| 2 | |
| 3 | Required properties: |
| 4 | - compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3". |
| 5 | Example "<vendor>,<type>" values: |
| 6 | "samsung,K3QF2F20DB" |
| 7 | |
| 8 | - density : <u32> representing density in Mb (Mega bits) |
| 9 | - io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64 |
| 10 | - #address-cells: Must be set to 1 |
| 11 | - #size-cells: Must be set to 0 |
| 12 | |
| 13 | Optional properties: |
| 14 | |
| 15 | The following optional properties represent the minimum value of some AC |
| 16 | timing parameters of the DDR device in terms of number of clock cycles. |
| 17 | These values shall be obtained from the device data-sheet. |
| 18 | - tRFC-min-tck |
| 19 | - tRRD-min-tck |
| 20 | - tRPab-min-tck |
| 21 | - tRPpb-min-tck |
| 22 | - tRCD-min-tck |
| 23 | - tRC-min-tck |
| 24 | - tRAS-min-tck |
| 25 | - tWTR-min-tck |
| 26 | - tWR-min-tck |
| 27 | - tRTP-min-tck |
| 28 | - tW2W-C2C-min-tck |
| 29 | - tR2R-C2C-min-tck |
| 30 | - tWL-min-tck |
| 31 | - tDQSCK-min-tck |
| 32 | - tRL-min-tck |
| 33 | - tFAW-min-tck |
| 34 | - tXSR-min-tck |
| 35 | - tXP-min-tck |
| 36 | - tCKE-min-tck |
| 37 | - tCKESR-min-tck |
| 38 | - tMRD-min-tck |
| 39 | |
| 40 | Child nodes: |
| 41 | - The lpddr3 node may have one or more child nodes of type "lpddr3-timings". |
| 42 | "lpddr3-timings" provides AC timing parameters of the device for |
| 43 | a given speed-bin. Please see Documentation/devicetree/ |
| 44 | bindings/ddr/lpddr3-timings.txt for more information on "lpddr3-timings" |
| 45 | |
| 46 | Example: |
| 47 | |
| 48 | samsung_K3QF2F20DB: lpddr3 { |
| 49 | compatible = "samsung,K3QF2F20DB", "jedec,lpddr3"; |
| 50 | density = <16384>; |
| 51 | io-width = <32>; |
| 52 | #address-cells = <1>; |
| 53 | #size-cells = <0>; |
| 54 | |
| 55 | tRFC-min-tck = <17>; |
| 56 | tRRD-min-tck = <2>; |
| 57 | tRPab-min-tck = <2>; |
| 58 | tRPpb-min-tck = <2>; |
| 59 | tRCD-min-tck = <3>; |
| 60 | tRC-min-tck = <6>; |
| 61 | tRAS-min-tck = <5>; |
| 62 | tWTR-min-tck = <2>; |
| 63 | tWR-min-tck = <7>; |
| 64 | tRTP-min-tck = <2>; |
| 65 | tW2W-C2C-min-tck = <0>; |
| 66 | tR2R-C2C-min-tck = <0>; |
| 67 | tWL-min-tck = <8>; |
| 68 | tDQSCK-min-tck = <5>; |
| 69 | tRL-min-tck = <14>; |
| 70 | tFAW-min-tck = <5>; |
| 71 | tXSR-min-tck = <12>; |
| 72 | tXP-min-tck = <2>; |
| 73 | tCKE-min-tck = <2>; |
| 74 | tCKESR-min-tck = <2>; |
| 75 | tMRD-min-tck = <5>; |
| 76 | |
| 77 | timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { |
| 78 | compatible = "jedec,lpddr3-timings"; |
| 79 | /* workaround: 'reg' shows max-freq */ |
| 80 | reg = <800000000>; |
| 81 | min-freq = <100000000>; |
| 82 | tRFC = <65000>; |
| 83 | tRRD = <6000>; |
| 84 | tRPab = <12000>; |
| 85 | tRPpb = <12000>; |
| 86 | tRCD = <10000>; |
| 87 | tRC = <33750>; |
| 88 | tRAS = <23000>; |
| 89 | tWTR = <3750>; |
| 90 | tWR = <7500>; |
| 91 | tRTP = <3750>; |
| 92 | tW2W-C2C = <0>; |
| 93 | tR2R-C2C = <0>; |
| 94 | tFAW = <25000>; |
| 95 | tXSR = <70000>; |
| 96 | tXP = <3750>; |
| 97 | tCKE = <3750>; |
| 98 | tCKESR = <3750>; |
| 99 | tMRD = <7000>; |
| 100 | }; |
| 101 | } |