| Olivier Deprez | 157378f | 2022-04-04 15:47:50 +0200 | [diff] [blame^] | 1 | * AC timing parameters of LPDDR3 memories for a given speed-bin. |
| 2 | |
| 3 | The structures are based on LPDDR2 and extended where needed. |
| 4 | |
| 5 | Required properties: |
| 6 | - compatible : Should be "jedec,lpddr3-timings" |
| 7 | - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32> |
| 8 | - reg : maximum DDR clock frequency for the speed-bin. Type is <u32> |
| 9 | |
| 10 | Optional properties: |
| 11 | |
| 12 | The following properties represent AC timing parameters from the memory |
| 13 | data-sheet of the device for a given speed-bin. All these properties are |
| 14 | of type <u32> and the default unit is ps (pico seconds). |
| 15 | - tRFC |
| 16 | - tRRD |
| 17 | - tRPab |
| 18 | - tRPpb |
| 19 | - tRCD |
| 20 | - tRC |
| 21 | - tRAS |
| 22 | - tWTR |
| 23 | - tWR |
| 24 | - tRTP |
| 25 | - tW2W-C2C |
| 26 | - tR2R-C2C |
| 27 | - tFAW |
| 28 | - tXSR |
| 29 | - tXP |
| 30 | - tCKE |
| 31 | - tCKESR |
| 32 | - tMRD |
| 33 | |
| 34 | Example: |
| 35 | |
| 36 | timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 { |
| 37 | compatible = "jedec,lpddr3-timings"; |
| 38 | reg = <800000000>; /* workaround: it shows max-freq */ |
| 39 | min-freq = <100000000>; |
| 40 | tRFC = <65000>; |
| 41 | tRRD = <6000>; |
| 42 | tRPab = <12000>; |
| 43 | tRPpb = <12000>; |
| 44 | tRCD = <10000>; |
| 45 | tRC = <33750>; |
| 46 | tRAS = <23000>; |
| 47 | tWTR = <3750>; |
| 48 | tWR = <7500>; |
| 49 | tRTP = <3750>; |
| 50 | tW2W-C2C = <0>; |
| 51 | tR2R-C2C = <0>; |
| 52 | tFAW = <25000>; |
| 53 | tXSR = <70000>; |
| 54 | tXP = <3750>; |
| 55 | tCKE = <3750>; |
| 56 | tCKESR = <3750>; |
| 57 | tMRD = <7000>; |
| 58 | }; |