| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | #ifndef __SOUND_PHASE_H |
| 3 | #define __SOUND_PHASE_H |
| 4 | |
| 5 | /* |
| 6 | * ALSA driver for ICEnsemble ICE1712 (Envy24) |
| 7 | * |
| 8 | * Lowlevel functions for Terratec PHASE 22 |
| 9 | * |
| 10 | * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\ |
| 14 | "{Terratec,Phase 28},"\ |
| 15 | "{Terrasoniq,TS22}," |
| 16 | |
| 17 | #define VT1724_SUBDEVICE_PHASE22 0x3b155011 |
| 18 | #define VT1724_SUBDEVICE_PHASE28 0x3b154911 |
| 19 | #define VT1724_SUBDEVICE_TS22 0x3b157b11 |
| 20 | |
| 21 | /* entry point */ |
| 22 | extern struct snd_ice1712_card_info snd_vt1724_phase_cards[]; |
| 23 | |
| 24 | /* PHASE28 GPIO bits */ |
| 25 | #define PHASE28_SPI_MISO (1 << 21) |
| 26 | #define PHASE28_WM_RESET (1 << 20) |
| 27 | #define PHASE28_SPI_CLK (1 << 19) |
| 28 | #define PHASE28_SPI_MOSI (1 << 18) |
| 29 | #define PHASE28_WM_RW (1 << 17) |
| 30 | #define PHASE28_AC97_RESET (1 << 16) |
| 31 | #define PHASE28_DIGITAL_SEL1 (1 << 15) |
| 32 | #define PHASE28_HP_SEL (1 << 14) |
| 33 | #define PHASE28_WM_CS (1 << 12) |
| 34 | #define PHASE28_AC97_COMMIT (1 << 11) |
| 35 | #define PHASE28_AC97_ADDR (1 << 10) |
| 36 | #define PHASE28_AC97_DATA_LOW (1 << 9) |
| 37 | #define PHASE28_AC97_DATA_HIGH (1 << 8) |
| 38 | #define PHASE28_AC97_DATA_MASK 0xFF |
| 39 | #endif /* __SOUND_PHASE */ |