| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Header file for device driver Hi6421 PMIC |
| 4 | * |
| 5 | * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd. |
| 6 | * http://www.hisilicon.com |
| 7 | * Copyright (c) <2013-2014> Linaro Ltd. |
| 8 | * http://www.linaro.org |
| 9 | * |
| 10 | * Author: Guodong Xu <guodong.xu@linaro.org> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef __HI6421_PMIC_H |
| 14 | #define __HI6421_PMIC_H |
| 15 | |
| 16 | /* Hi6421 registers are mapped to memory bus in 4 bytes stride */ |
| 17 | #define HI6421_REG_TO_BUS_ADDR(x) (x << 2) |
| 18 | |
| 19 | /* Hi6421 maximum register number */ |
| 20 | #define HI6421_REG_MAX 0xFF |
| 21 | |
| 22 | /* Hi6421 OCP (over current protection) and DEB (debounce) control register */ |
| 23 | #define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51) |
| 24 | #define HI6421_OCP_DEB_SEL_MASK 0x0C |
| 25 | #define HI6421_OCP_DEB_SEL_8MS 0x00 |
| 26 | #define HI6421_OCP_DEB_SEL_16MS 0x04 |
| 27 | #define HI6421_OCP_DEB_SEL_32MS 0x08 |
| 28 | #define HI6421_OCP_DEB_SEL_64MS 0x0C |
| 29 | #define HI6421_OCP_EN_DEBOUNCE_MASK 0x02 |
| 30 | #define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02 |
| 31 | #define HI6421_OCP_AUTO_STOP_MASK 0x01 |
| 32 | #define HI6421_OCP_AUTO_STOP_ENABLE 0x01 |
| 33 | |
| 34 | struct hi6421_pmic { |
| 35 | struct regmap *regmap; |
| 36 | }; |
| 37 | |
| 38 | enum hi6421_type { |
| 39 | HI6421 = 0, |
| 40 | HI6421_V530, |
| 41 | }; |
| 42 | |
| 43 | #endif /* __HI6421_PMIC_H */ |