David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2015-2016 MediaTek Inc. |
| 4 | * Author: Honghui Zhang <honghui.zhang@mediatek.com> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _MTK_IOMMU_H_ |
| 8 | #define _MTK_IOMMU_H_ |
| 9 | |
| 10 | #include <linux/clk.h> |
| 11 | #include <linux/component.h> |
| 12 | #include <linux/device.h> |
| 13 | #include <linux/io.h> |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 14 | #include <linux/io-pgtable.h> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 15 | #include <linux/iommu.h> |
| 16 | #include <linux/list.h> |
| 17 | #include <linux/spinlock.h> |
| 18 | #include <soc/mediatek/smi.h> |
| 19 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 20 | struct mtk_iommu_suspend_reg { |
| 21 | u32 standard_axi_mode; |
| 22 | u32 dcm_dis; |
| 23 | u32 ctrl_reg; |
| 24 | u32 int_control0; |
| 25 | u32 int_main_control; |
| 26 | u32 ivrp_paddr; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 27 | u32 vld_pa_rng; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 28 | }; |
| 29 | |
| 30 | enum mtk_iommu_plat { |
| 31 | M4U_MT2701, |
| 32 | M4U_MT2712, |
| 33 | M4U_MT8173, |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 34 | M4U_MT8183, |
| 35 | }; |
| 36 | |
| 37 | struct mtk_iommu_plat_data { |
| 38 | enum mtk_iommu_plat m4u_plat; |
| 39 | bool has_4gb_mode; |
| 40 | |
| 41 | /* HW will use the EMI clock if there isn't the "bclk". */ |
| 42 | bool has_bclk; |
| 43 | bool has_vld_pa_rng; |
| 44 | bool reset_axi; |
| 45 | unsigned char larbid_remap[MTK_LARB_NR_MAX]; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | struct mtk_iommu_domain; |
| 49 | |
| 50 | struct mtk_iommu_data { |
| 51 | void __iomem *base; |
| 52 | int irq; |
| 53 | struct device *dev; |
| 54 | struct clk *bclk; |
| 55 | phys_addr_t protect_base; /* protect memory base */ |
| 56 | struct mtk_iommu_suspend_reg reg; |
| 57 | struct mtk_iommu_domain *m4u_dom; |
| 58 | struct iommu_group *m4u_group; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 59 | bool enable_4GB; |
| 60 | bool tlb_flush_active; |
| 61 | |
| 62 | struct iommu_device iommu; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 63 | const struct mtk_iommu_plat_data *plat_data; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 64 | |
| 65 | struct list_head list; |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 66 | struct mtk_smi_larb_iommu larb_imu[MTK_LARB_NR_MAX]; |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 67 | }; |
| 68 | |
| 69 | static inline int compare_of(struct device *dev, void *data) |
| 70 | { |
| 71 | return dev->of_node == data; |
| 72 | } |
| 73 | |
| 74 | static inline void release_of(struct device *dev, void *data) |
| 75 | { |
| 76 | of_node_put(data); |
| 77 | } |
| 78 | |
| 79 | static inline int mtk_iommu_bind(struct device *dev) |
| 80 | { |
| 81 | struct mtk_iommu_data *data = dev_get_drvdata(dev); |
| 82 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 83 | return component_bind_all(dev, &data->larb_imu); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 84 | } |
| 85 | |
| 86 | static inline void mtk_iommu_unbind(struct device *dev) |
| 87 | { |
| 88 | struct mtk_iommu_data *data = dev_get_drvdata(dev); |
| 89 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 90 | component_unbind_all(dev, &data->larb_imu); |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | #endif |