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David Brazdil0f672f62019-12-10 10:32:29 +00001# SPDX-License-Identifier: GPL-2.0-only
Andrew Scullb4b6d4a2019-01-02 15:54:55 +00002config CRYPTO_DEV_CCP_DD
3 tristate "Secure Processor device driver"
4 depends on CPU_SUP_AMD || ARM64
5 default m
6 help
7 Provides AMD Secure Processor device driver.
8 If you choose 'M' here, this module will be called ccp.
9
10config CRYPTO_DEV_SP_CCP
11 bool "Cryptographic Coprocessor device"
12 default y
13 depends on CRYPTO_DEV_CCP_DD
14 select HW_RANDOM
15 select DMA_ENGINE
16 select DMADEVICES
17 select CRYPTO_SHA1
18 select CRYPTO_SHA256
19 help
20 Provides the support for AMD Cryptographic Coprocessor (CCP) device
21 which can be used to offload encryption operations such as SHA, AES
22 and more.
23
24config CRYPTO_DEV_CCP_CRYPTO
25 tristate "Encryption and hashing offload support"
26 default m
27 depends on CRYPTO_DEV_CCP_DD
28 depends on CRYPTO_DEV_SP_CCP
29 select CRYPTO_HASH
30 select CRYPTO_BLKCIPHER
31 select CRYPTO_AUTHENC
32 select CRYPTO_RSA
David Brazdil0f672f62019-12-10 10:32:29 +000033 select CRYPTO_LIB_AES
Andrew Scullb4b6d4a2019-01-02 15:54:55 +000034 help
35 Support for using the cryptographic API with the AMD Cryptographic
36 Coprocessor. This module supports offload of SHA and AES algorithms.
37 If you choose 'M' here, this module will be called ccp_crypto.
38
39config CRYPTO_DEV_SP_PSP
40 bool "Platform Security Processor (PSP) device"
41 default y
42 depends on CRYPTO_DEV_CCP_DD && X86_64
43 help
44 Provide support for the AMD Platform Security Processor (PSP).
45 The PSP is a dedicated processor that provides support for key
46 management commands in Secure Encrypted Virtualization (SEV) mode,
47 along with software-based Trusted Execution Environment (TEE) to
48 enable third-party trusted applications.
David Brazdil0f672f62019-12-10 10:32:29 +000049
50config CRYPTO_DEV_CCP_DEBUGFS
51 bool "Enable CCP Internals in DebugFS"
52 default n
53 depends on CRYPTO_DEV_SP_CCP
54 help
55 Expose CCP device information such as operation statistics, feature
56 information, and descriptor queue contents.