David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Regents of the University of California |
| 4 | * Copyright (C) 2014 Darius Rad <darius@bluespec.com> |
| 5 | * Copyright (C) 2017 SiFive |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <linux/syscalls.h> |
| 9 | #include <asm/unistd.h> |
| 10 | #include <asm/cacheflush.h> |
| 11 | |
| 12 | static long riscv_sys_mmap(unsigned long addr, unsigned long len, |
| 13 | unsigned long prot, unsigned long flags, |
| 14 | unsigned long fd, off_t offset, |
| 15 | unsigned long page_shift_offset) |
| 16 | { |
| 17 | if (unlikely(offset & (~PAGE_MASK >> page_shift_offset))) |
| 18 | return -EINVAL; |
| 19 | return ksys_mmap_pgoff(addr, len, prot, flags, fd, |
| 20 | offset >> (PAGE_SHIFT - page_shift_offset)); |
| 21 | } |
| 22 | |
| 23 | #ifdef CONFIG_64BIT |
| 24 | SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len, |
| 25 | unsigned long, prot, unsigned long, flags, |
| 26 | unsigned long, fd, off_t, offset) |
| 27 | { |
| 28 | return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 0); |
| 29 | } |
| 30 | #else |
| 31 | SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, |
| 32 | unsigned long, prot, unsigned long, flags, |
| 33 | unsigned long, fd, off_t, offset) |
| 34 | { |
| 35 | /* |
| 36 | * Note that the shift for mmap2 is constant (12), |
| 37 | * regardless of PAGE_SIZE |
| 38 | */ |
| 39 | return riscv_sys_mmap(addr, len, prot, flags, fd, offset, 12); |
| 40 | } |
| 41 | #endif /* !CONFIG_64BIT */ |
| 42 | |
| 43 | /* |
| 44 | * Allows the instruction cache to be flushed from userspace. Despite RISC-V |
| 45 | * having a direct 'fence.i' instruction available to userspace (which we |
| 46 | * can't trap!), that's not actually viable when running on Linux because the |
| 47 | * kernel might schedule a process on another hart. There is no way for |
| 48 | * userspace to handle this without invoking the kernel (as it doesn't know the |
| 49 | * thread->hart mappings), so we've defined a RISC-V specific system call to |
| 50 | * flush the instruction cache. |
| 51 | * |
| 52 | * sys_riscv_flush_icache() is defined to flush the instruction cache over an |
| 53 | * address range, with the flush applying to either all threads or just the |
| 54 | * caller. We don't currently do anything with the address range, that's just |
| 55 | * in there for forwards compatibility. |
| 56 | */ |
| 57 | SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end, |
| 58 | uintptr_t, flags) |
| 59 | { |
| 60 | /* Check the reserved flags. */ |
| 61 | if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL)) |
| 62 | return -EINVAL; |
| 63 | |
| 64 | flush_icache_mm(current->mm, flags & SYS_RISCV_FLUSH_ICACHE_LOCAL); |
| 65 | |
| 66 | return 0; |
| 67 | } |