David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Carsten Langgaard, carstenl@mips.com |
| 4 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 5 | * |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | * Setting up the clock on the MIPS boards. |
| 7 | */ |
| 8 | |
| 9 | #include <linux/init.h> |
| 10 | #include <linux/kernel_stat.h> |
| 11 | #include <linux/ptrace.h> |
| 12 | #include <linux/sched.h> |
| 13 | #include <linux/spinlock.h> |
| 14 | #include <linux/mc146818rtc.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/timex.h> |
| 17 | |
| 18 | #include <asm/mipsregs.h> |
| 19 | #include <asm/time.h> |
| 20 | #include <asm/mach-rc32434/rc32434.h> |
| 21 | |
| 22 | extern unsigned int idt_cpu_freq; |
| 23 | |
| 24 | /* |
| 25 | * Figure out the r4k offset, the amount to increment the compare |
| 26 | * register for each time tick. There is no RTC available. |
| 27 | * |
| 28 | * The RC32434 counts at half the CPU *core* speed. |
| 29 | */ |
| 30 | static unsigned long __init cal_r4koff(void) |
| 31 | { |
| 32 | mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2; |
| 33 | |
| 34 | return mips_hpt_frequency / HZ; |
| 35 | } |
| 36 | |
| 37 | void __init plat_time_init(void) |
| 38 | { |
| 39 | unsigned int est_freq; |
| 40 | unsigned long flags, r4k_offset; |
| 41 | |
| 42 | local_irq_save(flags); |
| 43 | |
| 44 | printk(KERN_INFO "calculating r4koff... "); |
| 45 | r4k_offset = cal_r4koff(); |
| 46 | printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); |
| 47 | |
| 48 | est_freq = 2 * r4k_offset * HZ; |
| 49 | est_freq += 5000; /* round */ |
| 50 | est_freq -= est_freq % 10000; |
| 51 | printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, |
| 52 | (est_freq % 1000000) * 100 / 1000000); |
| 53 | local_irq_restore(flags); |
| 54 | } |