| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Setting up the clock on MSP SOCs. No RTC typically. |
| 4 | * |
| 5 | * Carsten Langgaard, carstenl@mips.com |
| 6 | * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. |
| 7 | * |
| 8 | * ######################################################################## |
| 9 | * |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 10 | * ######################################################################## |
| 11 | */ |
| 12 | |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/kernel_stat.h> |
| 15 | #include <linux/sched.h> |
| 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/ptrace.h> |
| 18 | |
| 19 | #include <asm/cevt-r4k.h> |
| 20 | #include <asm/mipsregs.h> |
| 21 | #include <asm/time.h> |
| 22 | |
| 23 | #include <msp_prom.h> |
| 24 | #include <msp_int.h> |
| 25 | #include <msp_regs.h> |
| 26 | |
| 27 | #define get_current_vpe() \ |
| 28 | ((read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) & TCBIND_CURVPE) |
| 29 | |
| 30 | static struct irqaction timer_vpe1; |
| 31 | static int tim_installed; |
| 32 | |
| 33 | void __init plat_time_init(void) |
| 34 | { |
| 35 | char *endp, *s; |
| 36 | unsigned long cpu_rate = 0; |
| 37 | |
| 38 | if (cpu_rate == 0) { |
| 39 | s = prom_getenv("clkfreqhz"); |
| 40 | cpu_rate = simple_strtoul(s, &endp, 10); |
| 41 | if (endp != NULL && *endp != 0) { |
| 42 | printk(KERN_ERR |
| 43 | "Clock rate in Hz parse error: %s\n", s); |
| 44 | cpu_rate = 0; |
| 45 | } |
| 46 | } |
| 47 | |
| 48 | if (cpu_rate == 0) { |
| 49 | s = prom_getenv("clkfreq"); |
| 50 | cpu_rate = 1000 * simple_strtoul(s, &endp, 10); |
| 51 | if (endp != NULL && *endp != 0) { |
| 52 | printk(KERN_ERR |
| 53 | "Clock rate in MHz parse error: %s\n", s); |
| 54 | cpu_rate = 0; |
| 55 | } |
| 56 | } |
| 57 | |
| 58 | if (cpu_rate == 0) { |
| 59 | #if defined(CONFIG_PMC_MSP7120_EVAL) \ |
| 60 | || defined(CONFIG_PMC_MSP7120_GW) |
| 61 | cpu_rate = 400000000; |
| 62 | #elif defined(CONFIG_PMC_MSP7120_FPGA) |
| 63 | cpu_rate = 25000000; |
| 64 | #else |
| 65 | cpu_rate = 150000000; |
| 66 | #endif |
| 67 | printk(KERN_ERR |
| 68 | "Failed to determine CPU clock rate, " |
| 69 | "assuming %ld hz ...\n", cpu_rate); |
| 70 | } |
| 71 | |
| 72 | printk(KERN_WARNING "Clock rate set to %ld\n", cpu_rate); |
| 73 | |
| 74 | /* timer frequency is 1/2 clock rate */ |
| 75 | mips_hpt_frequency = cpu_rate/2; |
| 76 | } |
| 77 | |
| 78 | unsigned int get_c0_compare_int(void) |
| 79 | { |
| 80 | /* MIPS_MT modes may want timer for second VPE */ |
| 81 | if ((get_current_vpe()) && !tim_installed) { |
| 82 | memcpy(&timer_vpe1, &c0_compare_irqaction, sizeof(timer_vpe1)); |
| 83 | setup_irq(MSP_INT_VPE1_TIMER, &timer_vpe1); |
| 84 | tim_installed++; |
| 85 | } |
| 86 | |
| 87 | return get_current_vpe() ? MSP_INT_VPE1_TIMER : MSP_INT_VPE0_TIMER; |
| 88 | } |