| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Secondary CPU startup routine source file. |
| 4 | * |
| 5 | * Copyright (C) 2009-2014 Texas Instruments, Inc. |
| 6 | * |
| 7 | * Author: |
| 8 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 9 | * |
| 10 | * Interface functions needed for the SMP. This file is based on arm |
| 11 | * realview smp platform. |
| 12 | * Copyright (c) 2003 ARM Limited. |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <linux/linkage.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <asm/assembler.h> |
| 18 | |
| 19 | #include "omap44xx.h" |
| 20 | |
| 21 | /* Physical address needed since MMU not enabled yet on secondary core */ |
| 22 | #define AUX_CORE_BOOT0_PA 0x48281800 |
| 23 | #define API_HYP_ENTRY 0x102 |
| 24 | |
| 25 | ENTRY(omap_secondary_startup) |
| 26 | #ifdef CONFIG_SMP |
| 27 | b secondary_startup |
| 28 | #else |
| 29 | /* Should never get here */ |
| 30 | again: wfi |
| 31 | b again |
| 32 | #endif |
| 33 | #ENDPROC(omap_secondary_startup) |
| 34 | |
| 35 | /* |
| 36 | * OMAP5 specific entry point for secondary CPU to jump from ROM |
| 37 | * code. This routine also provides a holding flag into which |
| 38 | * secondary core is held until we're ready for it to initialise. |
| 39 | * The primary core will update this flag using a hardware |
| 40 | * register AuxCoreBoot0. |
| 41 | */ |
| 42 | ENTRY(omap5_secondary_startup) |
| 43 | wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 |
| 44 | ldr r0, [r2] |
| 45 | mov r0, r0, lsr #5 |
| 46 | mrc p15, 0, r4, c0, c0, 5 |
| 47 | and r4, r4, #0x0f |
| 48 | cmp r0, r4 |
| 49 | bne wait |
| 50 | b omap_secondary_startup |
| 51 | ENDPROC(omap5_secondary_startup) |
| 52 | /* |
| 53 | * Same as omap5_secondary_startup except we call into the ROM to |
| 54 | * enable HYP mode first. This is called instead of |
| 55 | * omap5_secondary_startup if the primary CPU was put into HYP mode by |
| 56 | * the boot loader. |
| 57 | */ |
| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 58 | .arch armv7-a |
| 59 | .arch_extension sec |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 60 | ENTRY(omap5_secondary_hyp_startup) |
| 61 | wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 |
| 62 | ldr r0, [r2] |
| 63 | mov r0, r0, lsr #5 |
| 64 | mrc p15, 0, r4, c0, c0, 5 |
| 65 | and r4, r4, #0x0f |
| 66 | cmp r0, r4 |
| 67 | bne wait_2 |
| 68 | ldr r12, =API_HYP_ENTRY |
| 69 | badr r0, hyp_boot |
| 70 | smc #0 |
| 71 | hyp_boot: |
| 72 | b omap_secondary_startup |
| 73 | ENDPROC(omap5_secondary_hyp_startup) |
| 74 | /* |
| 75 | * OMAP4 specific entry point for secondary CPU to jump from ROM |
| 76 | * code. This routine also provides a holding flag into which |
| 77 | * secondary core is held until we're ready for it to initialise. |
| 78 | * The primary core will update this flag using a hardware |
| 79 | * register AuxCoreBoot0. |
| 80 | */ |
| 81 | ENTRY(omap4_secondary_startup) |
| 82 | hold: ldr r12,=0x103 |
| 83 | dsb |
| 84 | smc #0 @ read from AuxCoreBoot0 |
| 85 | mov r0, r0, lsr #9 |
| 86 | mrc p15, 0, r4, c0, c0, 5 |
| 87 | and r4, r4, #0x0f |
| 88 | cmp r0, r4 |
| 89 | bne hold |
| 90 | |
| 91 | /* |
| 92 | * we've been released from the wait loop,secondary_stack |
| 93 | * should now contain the SVC stack for this core |
| 94 | */ |
| 95 | b omap_secondary_startup |
| 96 | ENDPROC(omap4_secondary_startup) |
| 97 | |
| 98 | ENTRY(omap4460_secondary_startup) |
| 99 | hold_2: ldr r12,=0x103 |
| 100 | dsb |
| 101 | smc #0 @ read from AuxCoreBoot0 |
| 102 | mov r0, r0, lsr #9 |
| 103 | mrc p15, 0, r4, c0, c0, 5 |
| 104 | and r4, r4, #0x0f |
| 105 | cmp r0, r4 |
| 106 | bne hold_2 |
| 107 | |
| 108 | /* |
| 109 | * GIC distributor control register has changed between |
| 110 | * CortexA9 r1pX and r2pX. The Control Register secure |
| 111 | * banked version is now composed of 2 bits: |
| 112 | * bit 0 == Secure Enable |
| 113 | * bit 1 == Non-Secure Enable |
| 114 | * The Non-Secure banked register has not changed |
| 115 | * Because the ROM Code is based on the r1pX GIC, the CPU1 |
| 116 | * GIC restoration will cause a problem to CPU0 Non-Secure SW. |
| 117 | * The workaround must be: |
| 118 | * 1) Before doing the CPU1 wakeup, CPU0 must disable |
| 119 | * the GIC distributor |
| 120 | * 2) CPU1 must re-enable the GIC distributor on |
| 121 | * it's wakeup path. |
| 122 | */ |
| 123 | ldr r1, =OMAP44XX_GIC_DIST_BASE |
| 124 | ldr r0, [r1] |
| 125 | orr r0, #1 |
| 126 | str r0, [r1] |
| 127 | |
| 128 | /* |
| 129 | * we've been released from the wait loop,secondary_stack |
| 130 | * should now contain the SVC stack for this core |
| 131 | */ |
| 132 | b omap_secondary_startup |
| 133 | ENDPROC(omap4460_secondary_startup) |