| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * OMAP2+ Clock Management prototypes |
| 4 | * |
| 5 | * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. |
| 6 | * Copyright (C) 2007-2009 Nokia Corporation |
| 7 | * |
| 8 | * Written by Paul Walmsley |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 9 | */ |
| 10 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H |
| 11 | #define __ARCH_ASM_MACH_OMAP2_CM_H |
| 12 | |
| 13 | /* |
| 14 | * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the |
| 15 | * PRCM to request that a module exit the inactive state in the case of |
| 16 | * OMAP2 & 3. |
| 17 | * In the case of OMAP4 this is the max duration in microseconds for the |
| 18 | * module to reach the functionnal state from an inactive state. |
| 19 | */ |
| 20 | #define MAX_MODULE_READY_TIME 2000 |
| 21 | |
| 22 | # ifndef __ASSEMBLER__ |
| 23 | #include <linux/clk/ti.h> |
| 24 | |
| 25 | #include "prcm-common.h" |
| 26 | |
| 27 | extern struct omap_domain_base cm_base; |
| 28 | extern struct omap_domain_base cm2_base; |
| 29 | extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); |
| 30 | # endif |
| 31 | |
| 32 | /* |
| 33 | * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for |
| 34 | * the PRCM to request that a module enter the inactive state in the |
| 35 | * case of OMAP2 & 3. In the case of OMAP4 this is the max duration |
| 36 | * in microseconds for the module to reach the inactive state from |
| 37 | * a functional state. |
| 38 | * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during |
| 39 | * kernel init. |
| 40 | */ |
| 41 | #define MAX_MODULE_DISABLE_TIME 5000 |
| 42 | |
| 43 | # ifndef __ASSEMBLER__ |
| 44 | |
| 45 | /** |
| 46 | * struct cm_ll_data - fn ptrs to per-SoC CM function implementations |
| 47 | * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl |
| 48 | * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl |
| 49 | * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl |
| 50 | * @module_enable: ptr to the SoC CM-specific module_enable impl |
| 51 | * @module_disable: ptr to the SoC CM-specific module_disable impl |
| 52 | * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl |
| 53 | */ |
| 54 | struct cm_ll_data { |
| 55 | int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, |
| 56 | u8 *idlest_reg_id); |
| 57 | int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, |
| 58 | u8 idlest_shift); |
| 59 | int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg, |
| 60 | u8 idlest_shift); |
| 61 | void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); |
| 62 | void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); |
| 63 | u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); |
| 64 | }; |
| 65 | |
| 66 | extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, |
| 67 | u8 *idlest_reg_id); |
| 68 | int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg, |
| 69 | u8 idlest_shift); |
| 70 | int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, |
| 71 | u8 idlest_shift); |
| 72 | int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); |
| 73 | int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); |
| 74 | u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs); |
| 75 | extern int cm_register(const struct cm_ll_data *cld); |
| 76 | extern int cm_unregister(const struct cm_ll_data *cld); |
| 77 | int omap_cm_init(void); |
| 78 | int omap2_cm_base_init(void); |
| 79 | |
| 80 | # endif |
| 81 | |
| 82 | #endif |