| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * MMP2 Power Management Routines |
| 4 | * |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 5 | * (C) Copyright 2010 Marvell International Ltd. |
| 6 | * All Rights Reserved |
| 7 | */ |
| 8 | |
| 9 | #ifndef __MMP2_PM_H__ |
| 10 | #define __MMP2_PM_H__ |
| 11 | |
| 12 | #include "addr-map.h" |
| 13 | |
| 14 | #define APMU_PJ_IDLE_CFG APMU_REG(0x018) |
| 15 | #define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) |
| 16 | #define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) |
| 17 | #define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) |
| 18 | #define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) |
| 19 | #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) |
| 20 | |
| 21 | #define APMU_SRAM_PWR_DWN APMU_REG(0x08c) |
| 22 | |
| 23 | #define MPMU_SCCR MPMU_REG(0x038) |
| 24 | #define MPMU_PCR_PJ MPMU_REG(0x1000) |
| 25 | #define MPMU_PCR_PJ_AXISD (1 << 31) |
| 26 | #define MPMU_PCR_PJ_SLPEN (1 << 29) |
| 27 | #define MPMU_PCR_PJ_SPSD (1 << 28) |
| 28 | #define MPMU_PCR_PJ_DDRCORSD (1 << 27) |
| 29 | #define MPMU_PCR_PJ_APBSD (1 << 26) |
| 30 | #define MPMU_PCR_PJ_INTCLR (1 << 24) |
| 31 | #define MPMU_PCR_PJ_SLPWP0 (1 << 23) |
| 32 | #define MPMU_PCR_PJ_SLPWP1 (1 << 22) |
| 33 | #define MPMU_PCR_PJ_SLPWP2 (1 << 21) |
| 34 | #define MPMU_PCR_PJ_SLPWP3 (1 << 20) |
| 35 | #define MPMU_PCR_PJ_VCTCXOSD (1 << 19) |
| 36 | #define MPMU_PCR_PJ_SLPWP4 (1 << 18) |
| 37 | #define MPMU_PCR_PJ_SLPWP5 (1 << 17) |
| 38 | #define MPMU_PCR_PJ_SLPWP6 (1 << 16) |
| 39 | #define MPMU_PCR_PJ_SLPWP7 (1 << 15) |
| 40 | |
| 41 | #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) |
| 42 | #define MPMU_CGR_PJ MPMU_REG(0x1024) |
| 43 | #define MPMU_WUCRM_PJ MPMU_REG(0x104c) |
| 44 | #define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) |
| 45 | #define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) |
| 46 | |
| 47 | enum { |
| 48 | POWER_MODE_ACTIVE = 0, |
| 49 | POWER_MODE_CORE_INTIDLE, |
| 50 | POWER_MODE_CORE_EXTIDLE, |
| 51 | POWER_MODE_APPS_IDLE, |
| 52 | POWER_MODE_APPS_SLEEP, |
| 53 | POWER_MODE_CHIP_SLEEP, |
| 54 | POWER_MODE_SYS_SLEEP, |
| 55 | }; |
| 56 | |
| 57 | extern void mmp2_pm_enter_lowpower_mode(int state); |
| 58 | extern int mmp2_set_wake(struct irq_data *d, unsigned int on); |
| 59 | #endif |