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review.trustedfirmware.org / hafnium / third_party / linux.git / 0f672f6c0b52b7b0700b0915c72b540721af4465 / . / arch / arm / mach-lpc32xx / serial.c
blob: 3e765c4bf986091eb881fd588e549165d3edf7f3 [file] [log] [blame]
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0-or-later
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]2/*
3 * arch/arm/mach-lpc32xx/serial.c
4 *
5 * Author: Kevin Wells <kevin.wells@nxp.com>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]8 */
9
10#include <linux/kernel.h>
11#include <linux/types.h>
12#include <linux/serial.h>
13#include <linux/serial_core.h>
14#include <linux/serial_reg.h>
15#include <linux/serial_8250.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]19#include "lpc32xx.h"
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]20#include "common.h"
21
22#define LPC32XX_SUART_FIFO_SIZE 64
23
24struct uartinit {
25 char *uart_ck_name;
26 u32 ck_mode_mask;
27 void __iomem *pdiv_clk_reg;
28 resource_size_t mapbase;
29};
30
31static struct uartinit uartinit_data[] __initdata = {
32 {
33 .uart_ck_name = "uart5_ck",
34 .ck_mode_mask =
35 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
36 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
37 .mapbase = LPC32XX_UART5_BASE,
38 },
39 {
40 .uart_ck_name = "uart3_ck",
41 .ck_mode_mask =
42 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
43 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
44 .mapbase = LPC32XX_UART3_BASE,
45 },
46 {
47 .uart_ck_name = "uart4_ck",
48 .ck_mode_mask =
49 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
50 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
51 .mapbase = LPC32XX_UART4_BASE,
52 },
53 {
54 .uart_ck_name = "uart6_ck",
55 .ck_mode_mask =
56 LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
57 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
58 .mapbase = LPC32XX_UART6_BASE,
59 },
60};
61
David Brazdil0f672f62019-12-10 10:32:29 +0000[diff] [blame^]62/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
63void lpc32xx_loopback_set(resource_size_t mapbase, int state)
64{
65 int bit;
66 u32 tmp;
67
68 switch (mapbase) {
69 case LPC32XX_HS_UART1_BASE:
70 bit = 0;
71 break;
72 case LPC32XX_HS_UART2_BASE:
73 bit = 1;
74 break;
75 case LPC32XX_HS_UART7_BASE:
76 bit = 6;
77 break;
78 default:
79 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
80 return;
81 }
82
83 tmp = readl(LPC32XX_UARTCTL_CLOOP);
84 if (state)
85 tmp |= (1 << bit);
86 else
87 tmp &= ~(1 << bit);
88 writel(tmp, LPC32XX_UARTCTL_CLOOP);
89}
90EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
91
Andrew Scullb4b6d4a2019-01-02 15:54:55 +0000[diff] [blame]92void __init lpc32xx_serial_init(void)
93{
94 u32 tmp, clkmodes = 0;
95 struct clk *clk;
96 unsigned int puart;
97 int i, j;
98
99 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
100 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
101 if (!IS_ERR(clk)) {
102 clk_enable(clk);
103 }
104
105 /* Setup UART clock modes for all UARTs, disable autoclock */
106 clkmodes |= uartinit_data[i].ck_mode_mask;
107
108 /* pre-UART clock divider set to 1 */
109 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
110
111 /*
112 * Force a flush of the RX FIFOs to work around a
113 * HW bug
114 */
115 puart = uartinit_data[i].mapbase;
116 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
117 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
118 j = LPC32XX_SUART_FIFO_SIZE;
119 while (j--)
120 tmp = __raw_readl(
121 LPC32XX_UART_DLL_FIFO(puart));
122 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
123 }
124
125 /* This needs to be done after all UART clocks are setup */
126 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
127 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
128 /* Force a flush of the RX FIFOs to work around a HW bug */
129 puart = uartinit_data[i].mapbase;
130 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
131 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
132 j = LPC32XX_SUART_FIFO_SIZE;
133 while (j--)
134 tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
135 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
136 }
137
138 /* Disable IrDA pulsing support on UART6 */
139 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
140 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
141 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
142
143 /* Disable UART5->USB transparent mode or USB won't work */
144 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
145 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
146 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
147}