David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * arch/arm/mach-ixp4xx/ixdpg425-pci.c |
| 4 | * |
| 5 | * PCI setup routines for Intel IXDPG425 Platform |
| 6 | * |
| 7 | * Copyright (C) 2004 MontaVista Softwrae, Inc. |
| 8 | * |
| 9 | * Maintainer: Deepak Saxena <dsaxena@plexity.net> |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/init.h> |
| 15 | #include <linux/irq.h> |
| 16 | |
| 17 | #include <asm/mach-types.h> |
| 18 | #include <mach/hardware.h> |
| 19 | |
| 20 | #include <asm/mach/pci.h> |
| 21 | |
David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 22 | #include "irqs.h" |
| 23 | |
Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 24 | void __init ixdpg425_pci_preinit(void) |
| 25 | { |
| 26 | irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); |
| 27 | irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); |
| 28 | |
| 29 | ixp4xx_pci_preinit(); |
| 30 | } |
| 31 | |
| 32 | static int __init ixdpg425_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
| 33 | { |
| 34 | if (slot == 12 || slot == 13) |
| 35 | return IRQ_IXP4XX_GPIO7; |
| 36 | else if (slot == 14) |
| 37 | return IRQ_IXP4XX_GPIO6; |
| 38 | else return -1; |
| 39 | } |
| 40 | |
| 41 | struct hw_pci ixdpg425_pci __initdata = { |
| 42 | .nr_controllers = 1, |
| 43 | .ops = &ixp4xx_ops, |
| 44 | .preinit = ixdpg425_pci_preinit, |
| 45 | .setup = ixp4xx_setup, |
| 46 | .map_irq = ixdpg425_map_irq, |
| 47 | }; |
| 48 | |
| 49 | int __init ixdpg425_pci_init(void) |
| 50 | { |
| 51 | if (machine_is_ixdpg425()) |
| 52 | pci_common_init(&ixdpg425_pci); |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | subsys_initcall(ixdpg425_pci_init); |