| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Debugging macro include header |
| 4 | * |
| 5 | * Copyright (C) 2011 Xilinx |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 6 | */ |
| 7 | #define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ |
| 8 | #define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ |
| 9 | #define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ |
| 10 | |
| 11 | #define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ |
| 12 | #define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ |
| 13 | |
| 14 | #define UART0_PHYS 0xE0000000 |
| 15 | #define UART0_VIRT 0xF0800000 |
| 16 | #define UART1_PHYS 0xE0001000 |
| 17 | #define UART1_VIRT 0xF0801000 |
| 18 | |
| 19 | #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) |
| 20 | # define LL_UART_PADDR UART1_PHYS |
| 21 | # define LL_UART_VADDR UART1_VIRT |
| 22 | #else |
| 23 | # define LL_UART_PADDR UART0_PHYS |
| 24 | # define LL_UART_VADDR UART0_VIRT |
| 25 | #endif |
| 26 | |
| 27 | .macro addruart, rp, rv, tmp |
| 28 | ldr \rp, =LL_UART_PADDR @ physical |
| 29 | ldr \rv, =LL_UART_VADDR @ virtual |
| 30 | .endm |
| 31 | |
| 32 | .macro senduart,rd,rx |
| 33 | strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA |
| 34 | .endm |
| 35 | |
| 36 | .macro waituart,rd,rx |
| 37 | 1001: ldr \rd, [\rx, #UART_SR_OFFSET] |
| 38 | ARM_BE8( rev \rd, \rd ) |
| 39 | tst \rd, #UART_SR_TXEMPTY |
| 40 | beq 1001b |
| 41 | .endm |
| 42 | |
| 43 | .macro busyuart,rd,rx |
| 44 | 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register |
| 45 | ARM_BE8( rev \rd, \rd ) |
| 46 | tst \rd, #UART_SR_TXFULL @ |
| 47 | bne 1002b @ wait if FIFO is full |
| 48 | .endm |