| David Brazdil | 0f672f6 | 2019-12-10 10:32:29 +0000 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * |
| 4 | * Copyright (C) 2007 Google, Inc. |
| 5 | * Copyright (c) 2011, Code Aurora Forum. All rights reserved. |
| 6 | * Author: Brian Swetland <swetland@google.com> |
| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | .macro addruart, rp, rv, tmp |
| 10 | ldr \rp, =CONFIG_DEBUG_UART_PHYS |
| 11 | ldr \rv, =CONFIG_DEBUG_UART_VIRT |
| 12 | .endm |
| 13 | |
| 14 | .macro senduart, rd, rx |
| 15 | ARM_BE8(rev \rd, \rd ) |
| 16 | @ Write the 1 character to UARTDM_TF |
| 17 | str \rd, [\rx, #0x70] |
| 18 | .endm |
| 19 | |
| 20 | .macro waituart, rd, rx |
| 21 | @ check for TX_EMT in UARTDM_SR |
| 22 | ldr \rd, [\rx, #0x08] |
| 23 | ARM_BE8(rev \rd, \rd ) |
| 24 | tst \rd, #0x08 |
| 25 | bne 1002f |
| 26 | @ wait for TXREADY in UARTDM_ISR |
| 27 | 1001: ldr \rd, [\rx, #0x14] |
| 28 | ARM_BE8(rev \rd, \rd ) |
| 29 | tst \rd, #0x80 |
| 30 | beq 1001b |
| 31 | 1002: |
| 32 | @ Clear TX_READY by writing to the UARTDM_CR register |
| 33 | mov \rd, #0x300 |
| 34 | ARM_BE8(rev \rd, \rd ) |
| 35 | str \rd, [\rx, #0x10] |
| 36 | @ Write 0x1 to NCF register |
| 37 | mov \rd, #0x1 |
| 38 | ARM_BE8(rev \rd, \rd ) |
| 39 | str \rd, [\rx, #0x40] |
| 40 | @ UARTDM reg. Read to induce delay |
| 41 | ldr \rd, [\rx, #0x08] |
| 42 | .endm |
| 43 | |
| 44 | .macro busyuart, rd, rx |
| 45 | .endm |