arch/arm/boot/dts/qcom-msm8974.dtsi

// SPDX-License-Identifier: GPL-2.0
/dts-v1/;

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/clock/qcom,mmcc-msm8974.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/reset/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mpss@8000000 {
			reg = <0x08000000 0x5100000>;
			no-map;
		};

		mba@d100000 {
			reg = <0x0d100000 0x100000>;
			no-map;
		};

		reserved@d200000 {
			reg = <0x0d200000 0xa00000>;
			no-map;
		};

		adsp_region: adsp@dc00000 {
			reg = <0x0dc00000 0x1900000>;
			no-map;
		};

		venus@f500000 {
			reg = <0x0f500000 0x500000>;
			no-map;
		};

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};

		tz@fc00000 {
			reg = <0x0fc00000 0x160000>;
			no-map;
		};

		rfsa@fd60000 {
			reg = <0x0fd60000 0x20000>;
			no-map;
		};

		rmtfs@fd80000 {
			reg = <0x0fd80000 0x180000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <GIC_PPI 9 0xf04>;

		CPU0: cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU1: cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU2: cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		CPU3: cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x0>;
	};

	thermal-zones {
		cpu-thermal0 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 5>;

			trips {
				cpu_alert0: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit0: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 6>;

			trips {
				cpu_alert1: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit1: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 7>;

			trips {
				cpu_alert2: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit2: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		cpu-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 8>;

			trips {
				cpu_alert3: trip0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu_crit3: trip1 {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <GIC_PPI 7 0xf04>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 2 0xf08>,
			     <GIC_PPI 3 0xf08>,
			     <GIC_PPI 4 0xf08>,
			     <GIC_PPI 1 0xf08>;
		clock-frequency = <19200000>;
	};

	adsp-pil {
		compatible = "qcom,msm8974-adsp-pil";

		interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
				      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

		cx-supply = <&pm8841_s2>;

		clocks = <&xo_board>;
		clock-names = "xo";

		memory-region = <&adsp_region>;

		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 10>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 14>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,smem-state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-2 = <&apcs 8 9>;
		qcom,ipc-3 = <&apcs 8 19>;

		apps_smsm: apps@0 {
			reg = <0>;

			#qcom,smem-state-cells = <1>;
		};

		modem_smsm: modem@1 {
			reg = <1>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		adsp_smsm: adsp@2 {
			reg = <2>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@7 {
			reg = <7>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm";
			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
			clock-names = "core", "bus", "iface";
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		qfprom: qfprom@fc4bc000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "qcom,qfprom";
			reg = <0xfc4bc000 0x1000>;
			tsens_calib: calib@d0 {
				reg = <0xd0 0x18>;
			};
			tsens_backup: backup@440 {
				reg = <0x440 0x10>;
			};
		};

		tsens: thermal-sensor@fc4a9000 {
			compatible = "qcom,msm8974-tsens";
			reg = <0xfc4a9000 0x1000>, /* TM */
			      <0xfc4a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_calib>, <&tsens_backup>;
			nvmem-cell-names = "calib", "calib_backup";
			#qcom,sensors = <11>;
			#thermal-sensor-cells = <1>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr: syscon@fd4a0000 {
			compatible = "syscon";
			reg = <0xfd4a0000 0x10000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		blsp1_uart1: serial@f991d000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991d000 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		sdhci@f9864900 {
			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
				 <&gcc GCC_SDCC3_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		otg: usb@f9a55000 {
			compatible = "qcom,ci-hdrc";
			reg = <0xf9a55000 0x200>,
			      <0xf9a55200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <75000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs1_phy: phy@a {
					compatible = "qcom,usb-hs-phy-msm8974",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
					reset-names = "phy", "por";
					status = "disabled";
				};

				usb_hs2_phy: phy@b {
					compatible = "qcom,usb-hs-phy-msm8974",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
					reset-names = "phy", "por";
					status = "disabled";
				};
			};
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c@f9923000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9923000 0x1000>;
			interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		i2c@f9924000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9924000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp_i2c3: i2c@f9925000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9925000 0x1000>;
			interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp_i2c8: i2c@f9964000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9964000 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
			dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
			dma-names = "tx", "rx";
		};

		blsp_i2c12: i2c@f9968000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9968000 0x1000>;
			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		blsp2_dma: dma-controller@f9944000 {
			compatible = "qcom,bam-v1.4.0";
			reg = <0xf9944000 0x19000>;
			interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		etr@fc322000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0xfc322000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint = <&replicator_out0>;
					};
				};
			};
		};

		tpiu@fc318000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0xfc318000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint = <&replicator_out1>;
					};
				 };
			};
		};

		replicator@fc31c000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0xfc31c000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&etf_out>;
					};
				};
			};
		};

		etf@fc307000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0xfc307000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint = <&replicator_in>;
					};
				};
			};

			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint = <&merger_out>;
					};
				};
			};
		};

		funnel@fc31b000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0xfc31b000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/*
				 * Not described input ports:
				 * 0 - connected trought funnel to Audio, Modem and
				 *     Resource and Power Manager CPU's
				 * 2...7 - not-connected
				 */
				port@1 {
					reg = <1>;
					merger_in1: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					merger_out: endpoint {
						remote-endpoint = <&etf_in>;
					};
				};
			};
		};

		funnel@fc31a000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0xfc31a000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/*
				 * Not described input ports:
				 * 0 - not-connected
				 * 1 - connected trought funnel to Multimedia CPU
				 * 2 - connected to Wireless CPU
				 * 3 - not-connected
				 * 4 - not-connected
				 * 6 - not-connected
				 * 7 - connected to STM
				 */
				port@5 {
					reg = <5>;
					funnel1_in5: endpoint {
						remote-endpoint = <&kpss_out>;
					};
				};
			};

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&merger_in1>;
					};
				};
			};
		};

		funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0xfc345000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					kpss_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
				port@1 {
					reg = <1>;
					kpss_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
				port@2 {
					reg = <2>;
					kpss_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
				port@3 {
					reg = <3>;
					kpss_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};

			out-ports {
				port {
					kpss_out: endpoint {
						remote-endpoint = <&funnel1_in5>;
					};
				};
			};
		};

		etm@fc33c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0xfc33c000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU0>;

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&kpss_in0>;
					};
				};
			};
		};

		etm@fc33d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0xfc33d000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU1>;

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&kpss_in1>;
					};
				};
			};
		};

		etm@fc33e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0xfc33e000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU2>;

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&kpss_in2>;
					};
				};
			};
		};

		etm@fc33f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0xfc33f000 0x1000>;

			clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU3>;

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&kpss_in3>;
					};
				};
			};
		};

		mdss: mdss@fd900000 {
			status = "disabled";

			compatible = "qcom,mdss";
			reg = <0xfd900000 0x100>,
			      <0xfd924000 0x1000>;
			reg-names = "mdss_phys",
			            "vbif_phys";

			power-domains = <&mmcc MDSS_GDSC>;

			clocks = <&mmcc MDSS_AHB_CLK>,
			         <&mmcc MDSS_AXI_CLK>,
			         <&mmcc MDSS_VSYNC_CLK>;
			clock-names = "iface",
			              "bus",
			              "vsync";

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;
			#interrupt-cells = <1>;

			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			mdp: mdp@fd900000 {
				status = "disabled";

				compatible = "qcom,mdp5";
				reg = <0xfd900100 0x22000>;
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
				interrupts = <0 0>;

				clocks = <&mmcc MDSS_AHB_CLK>,
					 <&mmcc MDSS_AXI_CLK>,
					 <&mmcc MDSS_MDP_CLK>,
					 <&mmcc MDSS_VSYNC_CLK>;
				clock-names = "iface",
				              "bus",
				              "core",
				              "vsync";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						mdp5_intf1_out: endpoint {
							remote-endpoint = <&dsi0_in>;
						};
					};
				};
			};

			dsi0: dsi@fd922800 {
				status = "disabled";

				compatible = "qcom,mdss-dsi-ctrl";
				reg = <0xfd922800 0x1f8>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;

				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
				                  <&mmcc PCLK0_CLK_SRC>;
				assigned-clock-parents = <&dsi_phy0 0>,
				                         <&dsi_phy0 1>;

				clocks = <&mmcc MDSS_MDP_CLK>,
				         <&mmcc MDSS_AHB_CLK>,
				         <&mmcc MDSS_AXI_CLK>,
				         <&mmcc MDSS_BYTE0_CLK>,
				         <&mmcc MDSS_PCLK0_CLK>,
				         <&mmcc MDSS_ESC0_CLK>,
				         <&mmcc MMSS_MISC_AHB_CLK>;
				clock-names = "mdp_core",
				              "iface",
				              "bus",
				              "byte",
				              "pixel",
				              "core",
				              "core_mmss";

				phys = <&dsi_phy0>;
				phy-names = "dsi-phy";

				ports {
					#address-cells = <1>;
					#size-cells = <0>;

					port@0 {
						reg = <0>;
						dsi0_in: endpoint {
							remote-endpoint = <&mdp5_intf1_out>;
						};
					};

					port@1 {
						reg = <1>;
						dsi0_out: endpoint {
						};
					};
				};
			};

			dsi_phy0: dsi-phy@fd922a00 {
				status = "disabled";

				compatible = "qcom,dsi-phy-28nm-hpm";
				reg = <0xfd922a00 0xd4>,
				      <0xfd922b00 0x280>,
				      <0xfd922d80 0x30>;
				reg-names = "dsi_pll",
				            "dsi_phy",
				            "dsi_phy_regulator";

				#clock-cells = <1>;
				#phy-cells = <0>;
				qcom,dsi-phy-index = <0>;

				clocks = <&mmcc MDSS_AHB_CLK>;
				clock-names = "iface";
			};
		};
	};

	smd {
		compatible = "qcom,smd";

		adsp {
			interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&apcs 8 8>;
			qcom,smd-edge = <1>;
		};

		modem {
			interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;

			qcom,ipc = <&apcs 8 12>;
			qcom,smd-edge = <0>;
		};

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8974";
				qcom,smd-channels = "rpm_requests";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
					#clock-cells = <1>;
				};

				pm8841-regulators {
					compatible = "qcom,rpm-pm8841-regulators";

					pm8841_s1: s1 {};
					pm8841_s2: s2 {};
					pm8841_s3: s3 {};
					pm8841_s4: s4 {};
					pm8841_s5: s5 {};
					pm8841_s6: s6 {};
					pm8841_s7: s7 {};
					pm8841_s8: s8 {};
				};

				pm8941-regulators {
					compatible = "qcom,rpm-pm8941-regulators";

					pm8941_s1: s1 {};
					pm8941_s2: s2 {};
					pm8941_s3: s3 {};

					pm8941_l1: l1 {};
					pm8941_l2: l2 {};
					pm8941_l3: l3 {};
					pm8941_l4: l4 {};
					pm8941_l5: l5 {};
					pm8941_l6: l6 {};
					pm8941_l7: l7 {};
					pm8941_l8: l8 {};
					pm8941_l9: l9 {};
					pm8941_l10: l10 {};
					pm8941_l11: l11 {};
					pm8941_l12: l12 {};
					pm8941_l13: l13 {};
					pm8941_l14: l14 {};
					pm8941_l15: l15 {};
					pm8941_l16: l16 {};
					pm8941_l17: l17 {};
					pm8941_l18: l18 {};
					pm8941_l19: l19 {};
					pm8941_l20: l20 {};
					pm8941_l21: l21 {};
					pm8941_l22: l22 {};
					pm8941_l23: l23 {};
					pm8941_l24: l24 {};

					pm8941_lvs1: lvs1 {};
					pm8941_lvs2: lvs2 {};
					pm8941_lvs3: lvs3 {};
				};
			};
		};
	};

	vreg_boost: vreg-boost {
		compatible = "regulator-fixed";

		regulator-name = "vreg-boost";
		regulator-min-microvolt = <3150000>;
		regulator-max-microvolt = <3150000>;

		regulator-always-on;
		regulator-boot-on;

		gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
		enable-active-high;

		pinctrl-names = "default";
		pinctrl-0 = <&boost_bypass_n_pin>;
	};
	vreg_vph_pwr: vreg-vph-pwr {
		compatible = "regulator-fixed";
		regulator-name = "vph-pwr";

		regulator-min-microvolt = <3600000>;
		regulator-max-microvolt = <3600000>;

		regulator-always-on;
	};
};