| Andrew Scull | b4b6d4a | 2019-01-02 15:54:55 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | // |
| 3 | // Copyright (c) 2010 Samsung Electronics Co., Ltd. |
| 4 | // http://www.samsung.com/ |
| 5 | // |
| 6 | // S3C64XX setup information for IDE |
| 7 | |
| 8 | #include <linux/kernel.h> |
| 9 | #include <linux/gpio.h> |
| 10 | #include <linux/io.h> |
| 11 | |
| 12 | #include <mach/map.h> |
| 13 | #include <mach/regs-clock.h> |
| 14 | #include <plat/gpio-cfg.h> |
| 15 | #include <mach/gpio-samsung.h> |
| 16 | #include <linux/platform_data/ata-samsung_cf.h> |
| 17 | |
| 18 | void s3c64xx_ide_setup_gpio(void) |
| 19 | { |
| 20 | u32 reg; |
| 21 | |
| 22 | reg = readl(S3C_MEM_SYS_CFG) & (~0x3f); |
| 23 | |
| 24 | /* Independent CF interface, CF chip select configuration */ |
| 25 | writel(reg | MEM_SYS_CFG_INDEP_CF | |
| 26 | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG); |
| 27 | |
| 28 | s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4)); |
| 29 | |
| 30 | /* Set XhiDATA[15:0] pins as CF Data[15:0] */ |
| 31 | s3c_gpio_cfgpin_range(S3C64XX_GPK(0), 16, S3C_GPIO_SFN(5)); |
| 32 | |
| 33 | /* Set XhiADDR[2:0] pins as CF ADDR[2:0] */ |
| 34 | s3c_gpio_cfgpin_range(S3C64XX_GPL(0), 3, S3C_GPIO_SFN(6)); |
| 35 | |
| 36 | /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ |
| 37 | s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1)); |
| 38 | s3c_gpio_cfgpin_range(S3C64XX_GPM(0), 5, S3C_GPIO_SFN(6)); |
| 39 | } |