blob: 08ad42dda3eb643ce0b5377751a5f613d6521d2c [file] [log] [blame]
Andrew Scull5e1ddfa2018-08-14 10:06:54 +01001//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements a target parser to recognise hardware features such as
11// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_SUPPORT_TARGETPARSER_H
16#define LLVM_SUPPORT_TARGETPARSER_H
17
18// FIXME: vector is used because that's what clang uses for subtarget feature
19// lists, but SmallVector would probably be better
20#include "llvm/ADT/Triple.h"
21#include <vector>
22
23namespace llvm {
24class StringRef;
25
26// Target specific information into their own namespaces. These should be
27// generated from TableGen because the information is already there, and there
28// is where new information about targets will be added.
29// FIXME: To TableGen this we need to make some table generated files available
30// even if the back-end is not compiled with LLVM, plus we need to create a new
31// back-end to TableGen to create these clean tables.
32namespace ARM {
33
34// FPU Version
35enum class FPUVersion {
36 NONE,
37 VFPV2,
38 VFPV3,
39 VFPV3_FP16,
40 VFPV4,
41 VFPV5
42};
43
44// An FPU name restricts the FPU in one of three ways:
45enum class FPURestriction {
46 None = 0, ///< No restriction
47 D16, ///< Only 16 D registers
48 SP_D16 ///< Only single-precision instructions, with 16 D registers
49};
50
51// An FPU name implies one of three levels of Neon support:
52enum class NeonSupportLevel {
53 None = 0, ///< No Neon
54 Neon, ///< Neon
55 Crypto ///< Neon with Crypto
56};
57
58// FPU names.
59enum FPUKind {
60#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) KIND,
61#include "ARMTargetParser.def"
62 FK_LAST
63};
64
65// Arch names.
66enum class ArchKind {
67#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
68#include "ARMTargetParser.def"
69};
70
71// Arch extension modifiers for CPUs.
72enum ArchExtKind : unsigned {
73 AEK_INVALID = 0,
74 AEK_NONE = 1,
75 AEK_CRC = 1 << 1,
76 AEK_CRYPTO = 1 << 2,
77 AEK_FP = 1 << 3,
78 AEK_HWDIVTHUMB = 1 << 4,
79 AEK_HWDIVARM = 1 << 5,
80 AEK_MP = 1 << 6,
81 AEK_SIMD = 1 << 7,
82 AEK_SEC = 1 << 8,
83 AEK_VIRT = 1 << 9,
84 AEK_DSP = 1 << 10,
85 AEK_FP16 = 1 << 11,
86 AEK_RAS = 1 << 12,
87 AEK_SVE = 1 << 13,
88 AEK_DOTPROD = 1 << 14,
Andrew Scullcdfcccc2018-10-05 20:58:37 +010089 AEK_SHA2 = 1 << 15,
90 AEK_AES = 1 << 16,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +010091 // Unsupported extensions.
92 AEK_OS = 0x8000000,
93 AEK_IWMMXT = 0x10000000,
94 AEK_IWMMXT2 = 0x20000000,
95 AEK_MAVERICK = 0x40000000,
96 AEK_XSCALE = 0x80000000,
97};
98
99// ISA kinds.
100enum class ISAKind { INVALID = 0, ARM, THUMB, AARCH64 };
101
102// Endianness
103// FIXME: BE8 vs. BE32?
104enum class EndianKind { INVALID = 0, LITTLE, BIG };
105
106// v6/v7/v8 Profile
107enum class ProfileKind { INVALID = 0, A, R, M };
108
109StringRef getCanonicalArchName(StringRef Arch);
110
111// Information by ID
112StringRef getFPUName(unsigned FPUKind);
113FPUVersion getFPUVersion(unsigned FPUKind);
114NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
115FPURestriction getFPURestriction(unsigned FPUKind);
116
117// FIXME: These should be moved to TargetTuple once it exists
118bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
119bool getHWDivFeatures(unsigned HWDivKind, std::vector<StringRef> &Features);
120bool getExtensionFeatures(unsigned Extensions,
121 std::vector<StringRef> &Features);
122
123StringRef getArchName(ArchKind AK);
124unsigned getArchAttr(ArchKind AK);
125StringRef getCPUAttr(ArchKind AK);
126StringRef getSubArch(ArchKind AK);
127StringRef getArchExtName(unsigned ArchExtKind);
128StringRef getArchExtFeature(StringRef ArchExt);
129StringRef getHWDivName(unsigned HWDivKind);
130
131// Information by Name
132unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
133unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
134StringRef getDefaultCPU(StringRef Arch);
135
136// Parser
137unsigned parseHWDiv(StringRef HWDiv);
138unsigned parseFPU(StringRef FPU);
139ArchKind parseArch(StringRef Arch);
140unsigned parseArchExt(StringRef ArchExt);
141ArchKind parseCPUArch(StringRef CPU);
142void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
143ISAKind parseArchISA(StringRef Arch);
144EndianKind parseArchEndian(StringRef Arch);
145ProfileKind parseArchProfile(StringRef Arch);
146unsigned parseArchVersion(StringRef Arch);
147
148StringRef computeDefaultTargetABI(const Triple &TT, StringRef CPU);
149
150} // namespace ARM
151
152// FIXME:This should be made into class design,to avoid dupplication.
153namespace AArch64 {
154
155// Arch names.
156enum class ArchKind {
157#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
158#include "AArch64TargetParser.def"
159};
160
161// Arch extension modifiers for CPUs.
162enum ArchExtKind : unsigned {
163 AEK_INVALID = 0,
164 AEK_NONE = 1,
165 AEK_CRC = 1 << 1,
166 AEK_CRYPTO = 1 << 2,
167 AEK_FP = 1 << 3,
168 AEK_SIMD = 1 << 4,
169 AEK_FP16 = 1 << 5,
170 AEK_PROFILE = 1 << 6,
171 AEK_RAS = 1 << 7,
172 AEK_LSE = 1 << 8,
173 AEK_SVE = 1 << 9,
174 AEK_DOTPROD = 1 << 10,
175 AEK_RCPC = 1 << 11,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100176 AEK_RDM = 1 << 12,
177 AEK_SM4 = 1 << 13,
178 AEK_SHA3 = 1 << 14,
179 AEK_SHA2 = 1 << 15,
180 AEK_AES = 1 << 16,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100181};
182
183StringRef getCanonicalArchName(StringRef Arch);
184
185// Information by ID
186StringRef getFPUName(unsigned FPUKind);
187ARM::FPUVersion getFPUVersion(unsigned FPUKind);
188ARM::NeonSupportLevel getFPUNeonSupportLevel(unsigned FPUKind);
189ARM::FPURestriction getFPURestriction(unsigned FPUKind);
190
191// FIXME: These should be moved to TargetTuple once it exists
192bool getFPUFeatures(unsigned FPUKind, std::vector<StringRef> &Features);
193bool getExtensionFeatures(unsigned Extensions,
194 std::vector<StringRef> &Features);
195bool getArchFeatures(ArchKind AK, std::vector<StringRef> &Features);
196
197StringRef getArchName(ArchKind AK);
198unsigned getArchAttr(ArchKind AK);
199StringRef getCPUAttr(ArchKind AK);
200StringRef getSubArch(ArchKind AK);
201StringRef getArchExtName(unsigned ArchExtKind);
202StringRef getArchExtFeature(StringRef ArchExt);
203unsigned checkArchVersion(StringRef Arch);
204
205// Information by Name
206unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
207unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
208StringRef getDefaultCPU(StringRef Arch);
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100209AArch64::ArchKind getCPUArchKind(StringRef CPU);
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100210
211// Parser
212unsigned parseFPU(StringRef FPU);
213AArch64::ArchKind parseArch(StringRef Arch);
214ArchExtKind parseArchExt(StringRef ArchExt);
215ArchKind parseCPUArch(StringRef CPU);
216void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
217ARM::ISAKind parseArchISA(StringRef Arch);
218ARM::EndianKind parseArchEndian(StringRef Arch);
219ARM::ProfileKind parseArchProfile(StringRef Arch);
220unsigned parseArchVersion(StringRef Arch);
221
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100222bool isX18ReservedByDefault(const Triple &TT);
223
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100224} // namespace AArch64
225
226namespace X86 {
227
228// This should be kept in sync with libcc/compiler-rt as its included by clang
229// as a proxy for what's in libgcc/compiler-rt.
230enum ProcessorVendors : unsigned {
231 VENDOR_DUMMY,
232#define X86_VENDOR(ENUM, STRING) \
233 ENUM,
234#include "llvm/Support/X86TargetParser.def"
235 VENDOR_OTHER
236};
237
238// This should be kept in sync with libcc/compiler-rt as its included by clang
239// as a proxy for what's in libgcc/compiler-rt.
240enum ProcessorTypes : unsigned {
241 CPU_TYPE_DUMMY,
242#define X86_CPU_TYPE(ARCHNAME, ENUM) \
243 ENUM,
244#include "llvm/Support/X86TargetParser.def"
245 CPU_TYPE_MAX
246};
247
248// This should be kept in sync with libcc/compiler-rt as its included by clang
249// as a proxy for what's in libgcc/compiler-rt.
250enum ProcessorSubtypes : unsigned {
251 CPU_SUBTYPE_DUMMY,
252#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \
253 ENUM,
254#include "llvm/Support/X86TargetParser.def"
255 CPU_SUBTYPE_MAX
256};
257
258// This should be kept in sync with libcc/compiler-rt as it should be used
259// by clang as a proxy for what's in libgcc/compiler-rt.
260enum ProcessorFeatures {
261#define X86_FEATURE(VAL, ENUM) \
262 ENUM = VAL,
263#include "llvm/Support/X86TargetParser.def"
264
265};
266
267} // namespace X86
268
269} // namespace llvm
270
271#endif