| Andrew Scull | 0372a57 | 2018-11-16 15:47:06 +0000 | [diff] [blame] | 1 | //===- IntrinsicsRISCV.td - Defines RISCV intrinsics -------*- tablegen -*-===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines all of the RISCV-specific intrinsics. |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | let TargetPrefix = "riscv" in { |
| 15 | |
| 16 | //===----------------------------------------------------------------------===// |
| 17 | // Atomics |
| 18 | |
| 19 | class MaskedAtomicRMW32Intrinsic |
| 20 | : Intrinsic<[llvm_i32_ty], |
| 21 | [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], |
| 22 | [IntrArgMemOnly, NoCapture<0>]>; |
| 23 | |
| 24 | class MaskedAtomicRMW32WithSextIntrinsic |
| 25 | : Intrinsic<[llvm_i32_ty], |
| 26 | [llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, |
| 27 | llvm_i32_ty], |
| 28 | [IntrArgMemOnly, NoCapture<0>]>; |
| 29 | |
| 30 | def int_riscv_masked_atomicrmw_xchg_i32 : MaskedAtomicRMW32Intrinsic; |
| 31 | def int_riscv_masked_atomicrmw_add_i32 : MaskedAtomicRMW32Intrinsic; |
| 32 | def int_riscv_masked_atomicrmw_sub_i32 : MaskedAtomicRMW32Intrinsic; |
| 33 | def int_riscv_masked_atomicrmw_nand_i32 : MaskedAtomicRMW32Intrinsic; |
| 34 | def int_riscv_masked_atomicrmw_max_i32 : MaskedAtomicRMW32WithSextIntrinsic; |
| 35 | def int_riscv_masked_atomicrmw_min_i32 : MaskedAtomicRMW32WithSextIntrinsic; |
| 36 | def int_riscv_masked_atomicrmw_umax_i32 : MaskedAtomicRMW32Intrinsic; |
| 37 | def int_riscv_masked_atomicrmw_umin_i32 : MaskedAtomicRMW32Intrinsic; |
| 38 | |
| 39 | } // TargetPrefix = "riscv" |