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Andrew Walbran16937d02019-10-22 13:54:20 +01001//===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file implements a target parser to recognise AArch64 hardware features
10// such as FPU/CPU/ARCH and extension names.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_SUPPORT_AARCH64TARGETPARSERCOMMON_H
15#define LLVM_SUPPORT_AARCH64TARGETPARSERCOMMON_H
16
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/Support/ARMTargetParser.h"
20#include <vector>
21
22// FIXME:This should be made into class design,to avoid dupplication.
23namespace llvm {
24namespace AArch64 {
25
26// Arch extension modifiers for CPUs.
27enum ArchExtKind : unsigned {
28 AEK_INVALID = 0,
29 AEK_NONE = 1,
30 AEK_CRC = 1 << 1,
31 AEK_CRYPTO = 1 << 2,
32 AEK_FP = 1 << 3,
33 AEK_SIMD = 1 << 4,
34 AEK_FP16 = 1 << 5,
35 AEK_PROFILE = 1 << 6,
36 AEK_RAS = 1 << 7,
37 AEK_LSE = 1 << 8,
38 AEK_SVE = 1 << 9,
39 AEK_DOTPROD = 1 << 10,
40 AEK_RCPC = 1 << 11,
41 AEK_RDM = 1 << 12,
42 AEK_SM4 = 1 << 13,
43 AEK_SHA3 = 1 << 14,
44 AEK_SHA2 = 1 << 15,
45 AEK_AES = 1 << 16,
46 AEK_FP16FML = 1 << 17,
47 AEK_RAND = 1 << 18,
48 AEK_MTE = 1 << 19,
49 AEK_SSBS = 1 << 20,
50 AEK_SB = 1 << 21,
51 AEK_PREDRES = 1 << 22,
52};
53
54enum class ArchKind {
55#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
56#include "AArch64TargetParser.def"
57};
58
59const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {
60#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, \
61 ARCH_BASE_EXT) \
62 {NAME, \
63 sizeof(NAME) - 1, \
64 CPU_ATTR, \
65 sizeof(CPU_ATTR) - 1, \
66 SUB_ARCH, \
67 sizeof(SUB_ARCH) - 1, \
68 ARM::FPUKind::ARCH_FPU, \
69 ARCH_BASE_EXT, \
70 AArch64::ArchKind::ID, \
71 ARCH_ATTR},
72#include "AArch64TargetParser.def"
73};
74
75const ARM::ExtName AArch64ARCHExtNames[] = {
76#define AARCH64_ARCH_EXT_NAME(NAME, ID, FEATURE, NEGFEATURE) \
77 {NAME, sizeof(NAME) - 1, ID, FEATURE, NEGFEATURE},
78#include "AArch64TargetParser.def"
79};
80
81const ARM::CpuNames<ArchKind> AArch64CPUNames[] = {
82#define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
83 {NAME, sizeof(NAME) - 1, AArch64::ArchKind::ID, IS_DEFAULT, DEFAULT_EXT},
84#include "AArch64TargetParser.def"
85};
86
87const ArchKind ArchKinds[] = {
88#define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) \
89 ArchKind::ID,
90#include "AArch64TargetParser.def"
91};
92
93// FIXME: These should be moved to TargetTuple once it exists
94bool getExtensionFeatures(unsigned Extensions,
95 std::vector<StringRef> &Features);
96bool getArchFeatures(ArchKind AK, std::vector<StringRef> &Features);
97
98StringRef getArchName(ArchKind AK);
99unsigned getArchAttr(ArchKind AK);
100StringRef getCPUAttr(ArchKind AK);
101StringRef getSubArch(ArchKind AK);
102StringRef getArchExtName(unsigned ArchExtKind);
103StringRef getArchExtFeature(StringRef ArchExt);
104
105// Information by Name
106unsigned getDefaultFPU(StringRef CPU, ArchKind AK);
107unsigned getDefaultExtensions(StringRef CPU, ArchKind AK);
108StringRef getDefaultCPU(StringRef Arch);
109ArchKind getCPUArchKind(StringRef CPU);
110
111// Parser
112ArchKind parseArch(StringRef Arch);
113ArchExtKind parseArchExt(StringRef ArchExt);
114ArchKind parseCPUArch(StringRef CPU);
115// Used by target parser tests
116void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values);
117
118bool isX18ReservedByDefault(const Triple &TT);
119
120} // namespace AArch64
121} // namespace llvm
122
123#endif