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Andrew Scull5e1ddfa2018-08-14 10:06:54 +01001//==- llvm/CodeGen/MachineMemOperand.h - MachineMemOperand class -*- C++ -*-==//
2//
Andrew Walbran16937d02019-10-22 13:54:20 +01003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Andrew Scull5e1ddfa2018-08-14 10:06:54 +01006//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the declaration of the MachineMemOperand class, which is a
10// description of a memory reference. It is used to help track dependencies
11// in the backend.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_CODEGEN_MACHINEMEMOPERAND_H
16#define LLVM_CODEGEN_MACHINEMEMOPERAND_H
17
18#include "llvm/ADT/BitmaskEnum.h"
19#include "llvm/ADT/PointerUnion.h"
20#include "llvm/CodeGen/PseudoSourceValue.h"
21#include "llvm/IR/Instructions.h"
22#include "llvm/IR/Metadata.h"
23#include "llvm/IR/Value.h" // PointerLikeTypeTraits<Value*>
24#include "llvm/Support/AtomicOrdering.h"
25#include "llvm/Support/DataTypes.h"
26
27namespace llvm {
28
29class FoldingSetNodeID;
30class MDNode;
31class raw_ostream;
32class MachineFunction;
33class ModuleSlotTracker;
34
35/// This class contains a discriminated union of information about pointers in
36/// memory operands, relating them back to LLVM IR or to virtual locations (such
37/// as frame indices) that are exposed during codegen.
38struct MachinePointerInfo {
39 /// This is the IR pointer value for the access, or it is null if unknown.
40 /// If this is null, then the access is to a pointer in the default address
41 /// space.
42 PointerUnion<const Value *, const PseudoSourceValue *> V;
43
44 /// Offset - This is an offset from the base Value*.
45 int64_t Offset;
46
47 uint8_t StackID;
48
49 unsigned AddrSpace = 0;
50
51 explicit MachinePointerInfo(const Value *v, int64_t offset = 0,
52 uint8_t ID = 0)
53 : V(v), Offset(offset), StackID(ID) {
54 AddrSpace = v ? v->getType()->getPointerAddressSpace() : 0;
55 }
56
57 explicit MachinePointerInfo(const PseudoSourceValue *v, int64_t offset = 0,
58 uint8_t ID = 0)
59 : V(v), Offset(offset), StackID(ID) {
60 AddrSpace = v ? v->getAddressSpace() : 0;
61 }
62
63 explicit MachinePointerInfo(unsigned AddressSpace = 0)
64 : V((const Value *)nullptr), Offset(0), StackID(0),
65 AddrSpace(AddressSpace) {}
66
67 explicit MachinePointerInfo(
68 PointerUnion<const Value *, const PseudoSourceValue *> v,
69 int64_t offset = 0,
70 uint8_t ID = 0)
71 : V(v), Offset(offset), StackID(ID) {
72 if (V) {
73 if (const auto *ValPtr = V.dyn_cast<const Value*>())
74 AddrSpace = ValPtr->getType()->getPointerAddressSpace();
75 else
76 AddrSpace = V.get<const PseudoSourceValue*>()->getAddressSpace();
77 }
78 }
79
80 MachinePointerInfo getWithOffset(int64_t O) const {
81 if (V.isNull())
82 return MachinePointerInfo(AddrSpace);
83 if (V.is<const Value*>())
84 return MachinePointerInfo(V.get<const Value*>(), Offset+O, StackID);
85 return MachinePointerInfo(V.get<const PseudoSourceValue*>(), Offset+O,
86 StackID);
87 }
88
89 /// Return true if memory region [V, V+Offset+Size) is known to be
90 /// dereferenceable.
91 bool isDereferenceable(unsigned Size, LLVMContext &C,
92 const DataLayout &DL) const;
93
94 /// Return the LLVM IR address space number that this pointer points into.
95 unsigned getAddrSpace() const;
96
97 /// Return a MachinePointerInfo record that refers to the constant pool.
98 static MachinePointerInfo getConstantPool(MachineFunction &MF);
99
100 /// Return a MachinePointerInfo record that refers to the specified
101 /// FrameIndex.
102 static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI,
103 int64_t Offset = 0);
104
105 /// Return a MachinePointerInfo record that refers to a jump table entry.
106 static MachinePointerInfo getJumpTable(MachineFunction &MF);
107
108 /// Return a MachinePointerInfo record that refers to a GOT entry.
109 static MachinePointerInfo getGOT(MachineFunction &MF);
110
111 /// Stack pointer relative access.
112 static MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset,
113 uint8_t ID = 0);
114
115 /// Stack memory without other information.
116 static MachinePointerInfo getUnknownStack(MachineFunction &MF);
117};
118
119
120//===----------------------------------------------------------------------===//
121/// A description of a memory reference used in the backend.
122/// Instead of holding a StoreInst or LoadInst, this class holds the address
123/// Value of the reference along with a byte size and offset. This allows it
124/// to describe lowered loads and stores. Also, the special PseudoSourceValue
125/// objects can be used to represent loads and stores to memory locations
126/// that aren't explicit in the regular LLVM IR.
127///
128class MachineMemOperand {
129public:
130 /// Flags values. These may be or'd together.
131 enum Flags : uint16_t {
132 // No flags set.
133 MONone = 0,
134 /// The memory access reads data.
135 MOLoad = 1u << 0,
136 /// The memory access writes data.
137 MOStore = 1u << 1,
138 /// The memory access is volatile.
139 MOVolatile = 1u << 2,
140 /// The memory access is non-temporal.
141 MONonTemporal = 1u << 3,
142 /// The memory access is dereferenceable (i.e., doesn't trap).
143 MODereferenceable = 1u << 4,
144 /// The memory access always returns the same value (or traps).
145 MOInvariant = 1u << 5,
146
147 // Reserved for use by target-specific passes.
148 // Targets may override getSerializableMachineMemOperandTargetFlags() to
149 // enable MIR serialization/parsing of these flags. If more of these flags
150 // are added, the MIR printing/parsing code will need to be updated as well.
151 MOTargetFlag1 = 1u << 6,
152 MOTargetFlag2 = 1u << 7,
153 MOTargetFlag3 = 1u << 8,
154
155 LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ MOTargetFlag3)
156 };
157
158private:
159 /// Atomic information for this memory operation.
160 struct MachineAtomicInfo {
161 /// Synchronization scope ID for this memory operation.
162 unsigned SSID : 8; // SyncScope::ID
163 /// Atomic ordering requirements for this memory operation. For cmpxchg
164 /// atomic operations, atomic ordering requirements when store occurs.
165 unsigned Ordering : 4; // enum AtomicOrdering
166 /// For cmpxchg atomic operations, atomic ordering requirements when store
167 /// does not occur.
168 unsigned FailureOrdering : 4; // enum AtomicOrdering
169 };
170
171 MachinePointerInfo PtrInfo;
172 uint64_t Size;
173 Flags FlagVals;
174 uint16_t BaseAlignLog2; // log_2(base_alignment) + 1
175 MachineAtomicInfo AtomicInfo;
176 AAMDNodes AAInfo;
177 const MDNode *Ranges;
178
179public:
180 /// Construct a MachineMemOperand object with the specified PtrInfo, flags,
181 /// size, and base alignment. For atomic operations the synchronization scope
182 /// and atomic ordering requirements must also be specified. For cmpxchg
183 /// atomic operations the atomic ordering requirements when store does not
184 /// occur must also be specified.
185 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
Andrew Scullcdfcccc2018-10-05 20:58:37 +0100186 uint64_t a,
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100187 const AAMDNodes &AAInfo = AAMDNodes(),
188 const MDNode *Ranges = nullptr,
189 SyncScope::ID SSID = SyncScope::System,
190 AtomicOrdering Ordering = AtomicOrdering::NotAtomic,
191 AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic);
192
193 const MachinePointerInfo &getPointerInfo() const { return PtrInfo; }
194
195 /// Return the base address of the memory access. This may either be a normal
196 /// LLVM IR Value, or one of the special values used in CodeGen.
197 /// Special values are those obtained via
198 /// PseudoSourceValue::getFixedStack(int), PseudoSourceValue::getStack, and
199 /// other PseudoSourceValue member functions which return objects which stand
200 /// for frame/stack pointer relative references and other special references
201 /// which are not representable in the high-level IR.
202 const Value *getValue() const { return PtrInfo.V.dyn_cast<const Value*>(); }
203
204 const PseudoSourceValue *getPseudoValue() const {
205 return PtrInfo.V.dyn_cast<const PseudoSourceValue*>();
206 }
207
208 const void *getOpaqueValue() const { return PtrInfo.V.getOpaqueValue(); }
209
210 /// Return the raw flags of the source value, \see Flags.
211 Flags getFlags() const { return FlagVals; }
212
213 /// Bitwise OR the current flags with the given flags.
214 void setFlags(Flags f) { FlagVals |= f; }
215
216 /// For normal values, this is a byte offset added to the base address.
217 /// For PseudoSourceValue::FPRel values, this is the FrameIndex number.
218 int64_t getOffset() const { return PtrInfo.Offset; }
219
220 unsigned getAddrSpace() const { return PtrInfo.getAddrSpace(); }
221
222 /// Return the size in bytes of the memory reference.
223 uint64_t getSize() const { return Size; }
224
225 /// Return the minimum known alignment in bytes of the actual memory
226 /// reference.
227 uint64_t getAlignment() const;
228
229 /// Return the minimum known alignment in bytes of the base address, without
230 /// the offset.
231 uint64_t getBaseAlignment() const { return (1u << BaseAlignLog2) >> 1; }
232
233 /// Return the AA tags for the memory reference.
234 AAMDNodes getAAInfo() const { return AAInfo; }
235
236 /// Return the range tag for the memory reference.
237 const MDNode *getRanges() const { return Ranges; }
238
239 /// Returns the synchronization scope ID for this memory operation.
240 SyncScope::ID getSyncScopeID() const {
241 return static_cast<SyncScope::ID>(AtomicInfo.SSID);
242 }
243
244 /// Return the atomic ordering requirements for this memory operation. For
245 /// cmpxchg atomic operations, return the atomic ordering requirements when
246 /// store occurs.
247 AtomicOrdering getOrdering() const {
248 return static_cast<AtomicOrdering>(AtomicInfo.Ordering);
249 }
250
251 /// For cmpxchg atomic operations, return the atomic ordering requirements
252 /// when store does not occur.
253 AtomicOrdering getFailureOrdering() const {
254 return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
255 }
256
257 bool isLoad() const { return FlagVals & MOLoad; }
258 bool isStore() const { return FlagVals & MOStore; }
259 bool isVolatile() const { return FlagVals & MOVolatile; }
260 bool isNonTemporal() const { return FlagVals & MONonTemporal; }
261 bool isDereferenceable() const { return FlagVals & MODereferenceable; }
262 bool isInvariant() const { return FlagVals & MOInvariant; }
263
264 /// Returns true if this operation has an atomic ordering requirement of
265 /// unordered or higher, false otherwise.
266 bool isAtomic() const { return getOrdering() != AtomicOrdering::NotAtomic; }
267
268 /// Returns true if this memory operation doesn't have any ordering
Andrew Walbran16937d02019-10-22 13:54:20 +0100269 /// constraints other than normal aliasing. Volatile and (ordered) atomic
270 /// memory operations can't be reordered.
271 bool isUnordered() const {
272 return (getOrdering() == AtomicOrdering::NotAtomic ||
273 getOrdering() == AtomicOrdering::Unordered) &&
274 !isVolatile();
275 }
Andrew Scull5e1ddfa2018-08-14 10:06:54 +0100276
277 /// Update this MachineMemOperand to reflect the alignment of MMO, if it has a
278 /// greater alignment. This must only be used when the new alignment applies
279 /// to all users of this MachineMemOperand.
280 void refineAlignment(const MachineMemOperand *MMO);
281
282 /// Change the SourceValue for this MachineMemOperand. This should only be
283 /// used when an object is being relocated and all references to it are being
284 /// updated.
285 void setValue(const Value *NewSV) { PtrInfo.V = NewSV; }
286 void setValue(const PseudoSourceValue *NewSV) { PtrInfo.V = NewSV; }
287 void setOffset(int64_t NewOffset) { PtrInfo.Offset = NewOffset; }
288
289 /// Profile - Gather unique data for the object.
290 ///
291 void Profile(FoldingSetNodeID &ID) const;
292
293 /// Support for operator<<.
294 /// @{
295 void print(raw_ostream &OS) const;
296 void print(raw_ostream &OS, ModuleSlotTracker &MST) const;
297 void print(raw_ostream &OS, ModuleSlotTracker &MST,
298 SmallVectorImpl<StringRef> &SSNs, const LLVMContext &Context,
299 const MachineFrameInfo *MFI, const TargetInstrInfo *TII) const;
300 /// @}
301
302 friend bool operator==(const MachineMemOperand &LHS,
303 const MachineMemOperand &RHS) {
304 return LHS.getValue() == RHS.getValue() &&
305 LHS.getPseudoValue() == RHS.getPseudoValue() &&
306 LHS.getSize() == RHS.getSize() &&
307 LHS.getOffset() == RHS.getOffset() &&
308 LHS.getFlags() == RHS.getFlags() &&
309 LHS.getAAInfo() == RHS.getAAInfo() &&
310 LHS.getRanges() == RHS.getRanges() &&
311 LHS.getAlignment() == RHS.getAlignment() &&
312 LHS.getAddrSpace() == RHS.getAddrSpace();
313 }
314
315 friend bool operator!=(const MachineMemOperand &LHS,
316 const MachineMemOperand &RHS) {
317 return !(LHS == RHS);
318 }
319};
320
321inline raw_ostream &operator<<(raw_ostream &OS, const MachineMemOperand &MRO) {
322 MRO.print(OS);
323 return OS;
324}
325
326} // End llvm namespace
327
328#endif