Update clang to r339409.
Change-Id: I800772d2d838223be1f6b40d490c4591b937fca2
diff --git a/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h b/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
index dd3e1df..0777add 100644
--- a/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
+++ b/linux-x64/clang/include/llvm/MC/MCInstrAnalysis.h
@@ -22,6 +22,9 @@
namespace llvm {
+class MCRegisterInfo;
+class Triple;
+
class MCInstrAnalysis {
protected:
friend class Target;
@@ -60,11 +63,56 @@
return Info->get(Inst.getOpcode()).isTerminator();
}
- /// \brief Given a branch instruction try to get the address the branch
+ /// Returns true if at least one of the register writes performed by
+ /// \param Inst implicitly clears the upper portion of all super-registers.
+ ///
+ /// Example: on X86-64, a write to EAX implicitly clears the upper half of
+ /// RAX. Also (still on x86) an XMM write perfomed by an AVX 128-bit
+ /// instruction implicitly clears the upper portion of the correspondent
+ /// YMM register.
+ ///
+ /// This method also updates an APInt which is used as mask of register
+ /// writes. There is one bit for every explicit/implicit write performed by
+ /// the instruction. If a write implicitly clears its super-registers, then
+ /// the corresponding bit is set (vic. the corresponding bit is cleared).
+ ///
+ /// The first bits in the APint are related to explicit writes. The remaining
+ /// bits are related to implicit writes. The sequence of writes follows the
+ /// machine operand sequence. For implicit writes, the sequence is defined by
+ /// the MCInstrDesc.
+ ///
+ /// The assumption is that the bit-width of the APInt is correctly set by
+ /// the caller. The default implementation conservatively assumes that none of
+ /// the writes clears the upper portion of a super-register.
+ virtual bool clearsSuperRegisters(const MCRegisterInfo &MRI,
+ const MCInst &Inst,
+ APInt &Writes) const;
+
+ /// Returns true if \param Inst is a dependency breaking instruction for the
+ /// given subtarget.
+ ///
+ /// The value computed by a dependency breaking instruction is not dependent
+ /// on the inputs. An example of dependency breaking instruction on X86 is
+ /// `XOR %eax, %eax`.
+ /// TODO: In future, we could implement an alternative approach where this
+ /// method returns `true` if the input instruction is not dependent on
+ /// some/all of its input operands. An APInt mask could then be used to
+ /// identify independent operands.
+ virtual bool isDependencyBreaking(const MCSubtargetInfo &STI,
+ const MCInst &Inst) const;
+
+ /// Given a branch instruction try to get the address the branch
/// targets. Return true on success, and the address in Target.
virtual bool
evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
uint64_t &Target) const;
+
+ /// Returns (PLT virtual address, GOT virtual address) pairs for PLT entries.
+ virtual std::vector<std::pair<uint64_t, uint64_t>>
+ findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
+ uint64_t GotPltSectionVA, const Triple &TargetTriple) const {
+ return {};
+ }
};
} // end namespace llvm