| /dts-v1/; |
| |
| /memreserve/ 0x0000000080000000 0x0000000000010000; |
| / { |
| model = "FVP Base"; |
| compatible = "arm,fvp-base\0arm,vexpress"; |
| interrupt-parent = <0x01>; |
| #address-cells = <0x02>; |
| #size-cells = <0x02>; |
| |
| interrupt-controller@2f000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <0x03>; |
| #address-cells = <0x01>; |
| #size-cells = <0x01>; |
| ranges = <0x00 0x00 0x2f000000 0x100000>; |
| interrupt-controller; |
| reg = <0x00 0x2f000000 0x00 0x10000 0x00 0x2f100000 0x00 0x200000 0x00 0x2c000000 0x00 0x2000 0x00 0x2c010000 0x00 0x2000 0x00 0x2c02f000 0x00 0x2000>; |
| interrupts = <0x01 0x09 0x04>; |
| phandle = <0x01>; |
| |
| msi-controller@2f020000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| #msi-cells = <0x01>; |
| reg = <0x20000 0x20000>; |
| }; |
| }; |
| |
| clk24mhz { |
| compatible = "fixed-clock"; |
| #clock-cells = <0x00>; |
| clock-frequency = <0x16e3600>; |
| clock-output-names = "v2m:clk24mhz"; |
| phandle = <0x05>; |
| }; |
| |
| refclk1mhz { |
| compatible = "fixed-clock"; |
| #clock-cells = <0x00>; |
| clock-frequency = <0xf4240>; |
| clock-output-names = "v2m:refclk1mhz"; |
| phandle = <0x04>; |
| }; |
| |
| refclk32khz { |
| compatible = "fixed-clock"; |
| #clock-cells = <0x00>; |
| clock-frequency = <0x8000>; |
| clock-output-names = "v2m:refclk32khz"; |
| phandle = <0x03>; |
| }; |
| |
| v2m-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "3V3"; |
| regulator-min-microvolt = <0x325aa0>; |
| regulator-max-microvolt = <0x325aa0>; |
| regulator-always-on; |
| phandle = <0x07>; |
| }; |
| |
| mcc { |
| compatible = "arm,vexpress,config-bus"; |
| arm,vexpress,config-bridge = <0x02>; |
| |
| oscclk1 { |
| compatible = "arm,vexpress-osc"; |
| arm,vexpress-sysreg,func = <0x01 0x01>; |
| freq-range = <0x16a6570 0x3c8eee0>; |
| #clock-cells = <0x00>; |
| clock-output-names = "v2m:oscclk1"; |
| phandle = <0x08>; |
| }; |
| |
| reset { |
| compatible = "arm,vexpress-reset"; |
| arm,vexpress-sysreg,func = <0x05 0x00>; |
| }; |
| |
| muxfpga { |
| compatible = "arm,vexpress-muxfpga"; |
| arm,vexpress-sysreg,func = <0x07 0x00>; |
| }; |
| |
| shutdown { |
| compatible = "arm,vexpress-shutdown"; |
| arm,vexpress-sysreg,func = <0x08 0x00>; |
| }; |
| |
| reboot { |
| compatible = "arm,vexpress-reboot"; |
| arm,vexpress-sysreg,func = <0x09 0x00>; |
| }; |
| |
| dvimode { |
| compatible = "arm,vexpress-dvimode"; |
| arm,vexpress-sysreg,func = <0x0b 0x00>; |
| }; |
| }; |
| |
| bus@8000000 { |
| compatible = "simple-bus"; |
| #address-cells = <0x02>; |
| #size-cells = <0x01>; |
| ranges = <0x00 0x8000000 0x00 0x8000000 0x18000000>; |
| #interrupt-cells = <0x01>; |
| interrupt-map-mask = <0x00 0x00 0x3f>; |
| interrupt-map = <0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x04 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x04 0x00 0x00 0x02 0x01 0x00 0x00 0x02 0x04 0x00 0x00 0x03 0x01 0x00 0x00 0x03 0x04 0x00 0x00 0x04 0x01 0x00 0x00 0x04 0x04 0x00 0x00 0x05 0x01 0x00 0x00 0x05 0x04 0x00 0x00 0x06 0x01 0x00 0x00 0x06 0x04 0x00 0x00 0x07 0x01 0x00 0x00 0x07 0x04 0x00 0x00 0x08 0x01 0x00 0x00 0x08 0x04 0x00 0x00 0x09 0x01 0x00 0x00 0x09 0x04 0x00 0x00 0x0a 0x01 0x00 0x00 0x0a 0x04 0x00 0x00 0x0b 0x01 0x00 0x00 0x0b 0x04 0x00 0x00 0x0c 0x01 0x00 0x00 0x0c 0x04 0x00 0x00 0x0d 0x01 0x00 0x00 0x0d 0x04 0x00 0x00 0x0e 0x01 0x00 0x00 0x0e 0x04 0x00 0x00 0x0f 0x01 0x00 0x00 0x0f 0x04 0x00 0x00 0x10 0x01 0x00 0x00 0x10 0x04 0x00 0x00 0x11 0x01 0x00 0x00 0x11 0x04 0x00 0x00 0x12 0x01 0x00 0x00 0x12 0x04 0x00 0x00 0x13 0x01 0x00 0x00 0x13 0x04 0x00 0x00 0x14 0x01 0x00 0x00 0x14 0x04 0x00 0x00 0x15 0x01 0x00 0x00 0x15 0x04 0x00 0x00 0x16 0x01 0x00 0x00 0x16 0x04 0x00 0x00 0x17 0x01 0x00 0x00 0x17 0x04 0x00 0x00 0x18 0x01 0x00 0x00 0x18 0x04 0x00 0x00 0x19 0x01 0x00 0x00 0x19 0x04 0x00 0x00 0x1a 0x01 0x00 0x00 0x1a 0x04 0x00 0x00 0x1b 0x01 0x00 0x00 0x1b 0x04 0x00 0x00 0x1c 0x01 0x00 0x00 0x1c 0x04 0x00 0x00 0x1d 0x01 0x00 0x00 0x1d 0x04 0x00 0x00 0x1e 0x01 0x00 0x00 0x1e 0x04 0x00 0x00 0x1f 0x01 0x00 0x00 0x1f 0x04 0x00 0x00 0x20 0x01 0x00 0x00 0x20 0x04 0x00 0x00 0x21 0x01 0x00 0x00 0x21 0x04 0x00 0x00 0x22 0x01 0x00 0x00 0x22 0x04 0x00 0x00 0x23 0x01 0x00 0x00 0x23 0x04 0x00 0x00 0x24 0x01 0x00 0x00 0x24 0x04 0x00 0x00 0x25 0x01 0x00 0x00 0x25 0x04 0x00 0x00 0x26 0x01 0x00 0x00 0x26 0x04 0x00 0x00 0x27 0x01 0x00 0x00 0x27 0x04 0x00 0x00 0x28 0x01 0x00 0x00 0x28 0x04 0x00 0x00 0x29 0x01 0x00 0x00 0x29 0x04 0x00 0x00 0x2a 0x01 0x00 0x00 0x2a 0x04>; |
| |
| motherboard-bus@8000000 { |
| compatible = "arm,vexpress,v2m-p1\0simple-bus"; |
| #address-cells = <0x02>; |
| #size-cells = <0x01>; |
| ranges = <0x00 0x00 0x00 0x8000000 0x4000000 0x01 0x00 0x00 0x14000000 0x4000000 0x02 0x00 0x00 0x18000000 0x4000000 0x03 0x00 0x00 0x1c000000 0x4000000 0x04 0x00 0x00 0xc000000 0x4000000 0x05 0x00 0x00 0x10000000 0x4000000>; |
| |
| flash@0 { |
| compatible = "arm,vexpress-flash\0cfi-flash"; |
| reg = <0x00 0x00 0x4000000 0x04 0x00 0x4000000>; |
| bank-width = <0x04>; |
| }; |
| |
| ethernet@202000000 { |
| compatible = "smsc,lan91c111"; |
| reg = <0x02 0x2000000 0x10000>; |
| interrupts = <0x0f>; |
| }; |
| |
| iofpga-bus@300000000 { |
| compatible = "simple-bus"; |
| #address-cells = <0x01>; |
| #size-cells = <0x01>; |
| ranges = <0x00 0x03 0x00 0x210000>; |
| |
| sysreg@10000 { |
| compatible = "arm,vexpress-sysreg"; |
| reg = <0x10000 0x1000>; |
| gpio-controller; |
| #gpio-cells = <0x02>; |
| phandle = <0x02>; |
| }; |
| |
| sysctl@20000 { |
| compatible = "arm,sp810\0arm,primecell"; |
| reg = <0x20000 0x1000>; |
| clocks = <0x03 0x04 0x05>; |
| clock-names = "refclk\0timclk\0apb_pclk"; |
| #clock-cells = <0x01>; |
| clock-output-names = "timerclken0\0timerclken1\0timerclken2\0timerclken3"; |
| assigned-clocks = <0x06 0x00 0x06 0x01 0x06 0x03 0x06 0x03>; |
| assigned-clock-parents = <0x04 0x04 0x04 0x04>; |
| phandle = <0x06>; |
| }; |
| |
| aaci@40000 { |
| compatible = "arm,pl041\0arm,primecell"; |
| reg = <0x40000 0x1000>; |
| interrupts = <0x0b>; |
| clocks = <0x05>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| mmc@50000 { |
| compatible = "arm,pl180\0arm,primecell"; |
| reg = <0x50000 0x1000>; |
| interrupts = <0x09 0x0a>; |
| cd-gpios = <0x02 0x00 0x00>; |
| wp-gpios = <0x02 0x01 0x00>; |
| max-frequency = <0xb71b00>; |
| vmmc-supply = <0x07>; |
| clocks = <0x05 0x05>; |
| clock-names = "mclk\0apb_pclk"; |
| }; |
| |
| kmi@60000 { |
| compatible = "arm,pl050\0arm,primecell"; |
| reg = <0x60000 0x1000>; |
| interrupts = <0x0c>; |
| clocks = <0x05 0x05>; |
| clock-names = "KMIREFCLK\0apb_pclk"; |
| }; |
| |
| kmi@70000 { |
| compatible = "arm,pl050\0arm,primecell"; |
| reg = <0x70000 0x1000>; |
| interrupts = <0x0d>; |
| clocks = <0x05 0x05>; |
| clock-names = "KMIREFCLK\0apb_pclk"; |
| }; |
| |
| serial@90000 { |
| compatible = "arm,pl011\0arm,primecell"; |
| reg = <0x90000 0x1000>; |
| interrupts = <0x05>; |
| clocks = <0x05 0x05>; |
| clock-names = "uartclk\0apb_pclk"; |
| }; |
| |
| serial@a0000 { |
| compatible = "arm,pl011\0arm,primecell"; |
| reg = <0xa0000 0x1000>; |
| interrupts = <0x06>; |
| clocks = <0x05 0x05>; |
| clock-names = "uartclk\0apb_pclk"; |
| }; |
| |
| serial@b0000 { |
| compatible = "arm,pl011\0arm,primecell"; |
| reg = <0xb0000 0x1000>; |
| interrupts = <0x07>; |
| clocks = <0x05 0x05>; |
| clock-names = "uartclk\0apb_pclk"; |
| }; |
| |
| serial@c0000 { |
| compatible = "arm,pl011\0arm,primecell"; |
| reg = <0xc0000 0x1000>; |
| interrupts = <0x08>; |
| clocks = <0x05 0x05>; |
| clock-names = "uartclk\0apb_pclk"; |
| }; |
| |
| watchdog@f0000 { |
| compatible = "arm,sp805\0arm,primecell"; |
| reg = <0xf0000 0x1000>; |
| interrupts = <0x00>; |
| clocks = <0x03 0x05>; |
| clock-names = "wdog_clk\0apb_pclk"; |
| }; |
| |
| timer@110000 { |
| compatible = "arm,sp804\0arm,primecell"; |
| reg = <0x110000 0x1000>; |
| interrupts = <0x02>; |
| clocks = <0x06 0x00 0x06 0x01 0x05>; |
| clock-names = "timclken1\0timclken2\0apb_pclk"; |
| }; |
| |
| timer@120000 { |
| compatible = "arm,sp804\0arm,primecell"; |
| reg = <0x120000 0x1000>; |
| interrupts = <0x03>; |
| clocks = <0x06 0x02 0x06 0x03 0x05>; |
| clock-names = "timclken1\0timclken2\0apb_pclk"; |
| }; |
| |
| virtio@130000 { |
| compatible = "virtio,mmio"; |
| reg = <0x130000 0x200>; |
| interrupts = <0x2a>; |
| }; |
| |
| rtc@170000 { |
| compatible = "arm,pl031\0arm,primecell"; |
| reg = <0x170000 0x1000>; |
| interrupts = <0x04>; |
| clocks = <0x05>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| clcd@1f0000 { |
| compatible = "arm,pl111\0arm,primecell"; |
| reg = <0x1f0000 0x1000>; |
| interrupt-names = "combined"; |
| interrupts = <0x0e>; |
| clocks = <0x08 0x05>; |
| clock-names = "clcdclk\0apb_pclk"; |
| memory-region = <0x09>; |
| |
| port { |
| |
| endpoint { |
| remote-endpoint = <0x0a>; |
| arm,pl11x,tft-r0g0b0-pads = <0x00 0x08 0x10>; |
| phandle = <0x16>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| chosen { |
| }; |
| |
| aliases { |
| serial0 = "/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000"; |
| serial1 = "/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@a0000"; |
| serial2 = "/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@b0000"; |
| serial3 = "/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@c0000"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0\0arm,psci-0.2"; |
| method = "smc"; |
| max-pwr-lvl = <0x02>; |
| }; |
| |
| cpus { |
| #address-cells = <0x02>; |
| #size-cells = <0x00>; |
| |
| cpu-map { |
| |
| cluster0 { |
| |
| core0 { |
| cpu = <0x0b>; |
| }; |
| |
| core1 { |
| cpu = <0x0c>; |
| }; |
| |
| core2 { |
| cpu = <0x0d>; |
| }; |
| |
| core3 { |
| cpu = <0x0e>; |
| }; |
| }; |
| |
| cluster1 { |
| |
| core0 { |
| cpu = <0x0f>; |
| }; |
| |
| core1 { |
| cpu = <0x10>; |
| }; |
| |
| core2 { |
| cpu = <0x11>; |
| }; |
| |
| core3 { |
| cpu = <0x12>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| cpu-sleep-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x10000>; |
| entry-latency-us = <0x28>; |
| exit-latency-us = <0x64>; |
| min-residency-us = <0x96>; |
| phandle = <0x13>; |
| }; |
| |
| cluster-sleep-0 { |
| compatible = "arm,idle-state"; |
| local-timer-stop; |
| arm,psci-suspend-param = <0x1010000>; |
| entry-latency-us = <0x1f4>; |
| exit-latency-us = <0x3e8>; |
| min-residency-us = <0x9c4>; |
| phandle = <0x14>; |
| }; |
| }; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x00>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x0b>; |
| }; |
| |
| cpu@10300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x10300>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x12>; |
| }; |
| |
| cpu@10200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x10200>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x11>; |
| }; |
| |
| cpu@10100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x10100>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x10>; |
| }; |
| |
| cpu@10000 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x10000>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x0f>; |
| }; |
| |
| cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x300>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x0e>; |
| }; |
| |
| cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x200>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x0d>; |
| }; |
| |
| cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x00 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <0x13 0x14>; |
| next-level-cache = <0x15>; |
| phandle = <0x0c>; |
| }; |
| |
| l2-cache0 { |
| compatible = "cache"; |
| phandle = <0x15>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x00 0x80000000 0x00 0x7f000000 0x08 0x80000000 0x00 0x80000000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <0x02>; |
| #size-cells = <0x02>; |
| ranges; |
| |
| vram@18000000 { |
| compatible = "shared-dma-pool"; |
| reg = <0x00 0x18000000 0x00 0x800000>; |
| no-map; |
| phandle = <0x09>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <0x01 0x0d 0xff08 0x01 0x0e 0xff08 0x01 0x0b 0xff08 0x01 0x0a 0xff08>; |
| clock-frequency = <0x5f5e100>; |
| }; |
| |
| timer@2a810000 { |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x00 0x2a810000 0x00 0x10000>; |
| clock-frequency = <0x5f5e100>; |
| #address-cells = <0x01>; |
| #size-cells = <0x01>; |
| ranges = <0x00 0x00 0x2a810000 0x100000>; |
| |
| frame@2a830000 { |
| frame-number = <0x01>; |
| interrupts = <0x00 0x1a 0x04>; |
| reg = <0x20000 0x10000>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <0x00 0x3c 0x04 0x00 0x3d 0x04 0x00 0x3e 0x04 0x00 0x3f 0x04>; |
| }; |
| |
| panel { |
| compatible = "arm,rtsm-display"; |
| |
| port { |
| |
| endpoint { |
| remote-endpoint = <0x16>; |
| phandle = <0x0a>; |
| }; |
| }; |
| }; |
| }; |